2007-02-01 00:47:23 +01:00
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---------- Begin Simulation Statistics ----------
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2011-07-10 19:56:09 +02:00
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sim_seconds 0.090885 # Number of seconds simulated
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sim_ticks 90884909500 # Number of ticks simulated
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2007-02-01 00:47:23 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-07-10 19:56:09 +02:00
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host_inst_rate 96810 # Simulator instruction rate (inst/s)
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host_tick_rate 23426991 # Simulator tick rate (ticks/s)
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host_mem_usage 252820 # Number of bytes of host memory used
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host_seconds 3879.50 # Real time elapsed on the host
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sim_insts 375574794 # Number of instructions simulated
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 105630800 # DTB read hits
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system.cpu.dtb.read_misses 100510 # DTB read misses
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system.cpu.dtb.read_acv 48612 # DTB read access violations
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system.cpu.dtb.read_accesses 105731310 # DTB read accesses
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system.cpu.dtb.write_hits 79936147 # DTB write hits
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system.cpu.dtb.write_misses 1547 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 79937694 # DTB write accesses
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system.cpu.dtb.data_hits 185566947 # DTB hits
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system.cpu.dtb.data_misses 102057 # DTB misses
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system.cpu.dtb.data_acv 48612 # DTB access violations
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system.cpu.dtb.data_accesses 185669004 # DTB accesses
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system.cpu.itb.fetch_hits 58326026 # ITB hits
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system.cpu.itb.fetch_misses 337 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 58326363 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 215 # Number of system calls
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system.cpu.numCycles 181769821 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.BPredUnit.lookups 57225452 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 33446848 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 3610875 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 40879451 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 32187006 # Number of BTB hits
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2009-03-07 23:30:55 +01:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2011-07-10 19:56:09 +02:00
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system.cpu.BPredUnit.usedRAS 10725194 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 1200 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 60337386 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 506200677 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 57225452 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 42912200 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 94142068 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 13173843 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 17624322 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 179 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 7572 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 58326026 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 1118192 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 181648006 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.786712 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.242035 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 87505938 48.17% 48.17% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 8084169 4.45% 52.62% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 9812284 5.40% 58.03% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 6556715 3.61% 61.64% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 13799395 7.60% 69.23% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 9400037 5.17% 74.41% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 5907170 3.25% 77.66% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 3477374 1.91% 79.57% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 37104924 20.43% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 181648006 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.314824 # Number of branch fetches per cycle
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system.cpu.fetch.rate 2.784844 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 66587043 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 13622871 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 88021771 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 3884112 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 9532209 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 10337474 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 4322 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 494122650 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 12073 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 9532209 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 71008708 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 4690007 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 394366 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 87374252 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 8648464 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 480990212 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 42769 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 7153610 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.RenamedOperands 312500874 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 630714726 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 332574792 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 298139934 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 259532319 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 52968555 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 38325 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 292 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 23912108 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 111095455 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 85873017 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 14526105 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 8463039 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 435543273 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 257 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 420425800 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 1773859 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 58536245 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 32877731 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 42 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 181648006 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 2.314508 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.994579 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::0 45216412 24.89% 24.89% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 30232996 16.64% 41.54% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 28617209 15.75% 57.29% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 25676408 14.14% 71.43% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 23156698 12.75% 84.17% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 15699012 8.64% 92.82% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 7807681 4.30% 97.11% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 3971496 2.19% 99.30% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 1270094 0.70% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::total 181648006 # Number of insts issued each cycle
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntAlu 135221 1.15% 1.15% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 0 0.00% 1.15% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 1.15% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 39442 0.34% 1.49% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 7017 0.06% 1.55% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 13904 0.12% 1.67% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 2001949 17.09% 18.77% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 880826 7.52% 26.29% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 26.29% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 26.29% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 26.29% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 26.29% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 26.29% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 26.29% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 26.29% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 26.29% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 26.29% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 26.29% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 26.29% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 26.29% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 26.29% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 26.29% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 26.29% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 26.29% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 26.29% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 26.29% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 26.29% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.29% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 26.29% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 5776712 49.33% 75.61% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 2855706 24.39% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued
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system.cpu.iq.FU_type_0::IntAlu 164795138 39.20% 39.21% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 2124451 0.51% 39.71% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.71% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatAdd 34088388 8.11% 47.82% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCmp 8064196 1.92% 49.74% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCvt 3086941 0.73% 50.47% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatMult 16853454 4.01% 54.48% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatDiv 1579988 0.38% 54.86% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.86% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.86% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.86% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.86% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.86% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.86% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.86% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.86% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.86% # Type of FU issued
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|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.86% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.86% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.86% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.86% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.86% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.86% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.86% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.86% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.86% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.86% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.86% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.86% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemRead 108302425 25.76% 80.62% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 81497238 19.38% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::total 420425800 # Type of FU issued
|
|
|
|
|
system.cpu.iq.rate 2.312957 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 11710777 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.027855 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 685991050 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 291244200 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 242469849 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 349993192 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 202862270 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 165589366 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_alu_accesses 253586541 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 178516455 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 13913922 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 16340969 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 171857 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 26790 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 12352289 # Number of stores squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 176199 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 2 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
|
|
|
system.cpu.iew.iewSquashCycles 9532209 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 2220194 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 306578 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 461167180 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 2274758 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 111095455 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 85873017 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 257 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 130 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 14 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 26790 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 3503569 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 569738 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 4073307 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 411738121 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 105779948 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 8687679 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
|
|
|
system.cpu.iew.exec_nop 25623650 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_refs 185717662 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 48391334 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 79937714 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 2.265162 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 409282340 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 408059215 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 198971045 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 279819296 # num instructions consuming a value
|
|
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.wb_rate 2.244923 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.711070 # average fanout of values written-back
|
|
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
|
|
|
system.cpu.commit.commitCommittedInsts 398664569 # The number of committed instructions
|
|
|
|
|
system.cpu.commit.commitSquashedInsts 62502516 # The number of squashed insts skipped by commit
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.branchMispredicts 3606605 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 172115797 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 2.316258 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 2.838436 # Number of insts commited each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::0 71294232 41.42% 41.42% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 26334848 15.30% 56.72% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 15061233 8.75% 65.47% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 13435550 7.81% 73.28% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 8560921 4.97% 78.25% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 6120977 3.56% 81.81% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 5034670 2.93% 84.74% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 3342912 1.94% 86.68% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 22930454 13.32% 100.00% # Number of insts commited each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::total 172115797 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.count 398664569 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
|
|
|
system.cpu.commit.refs 168275214 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 94754486 # Number of loads committed
|
|
|
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
|
|
|
system.cpu.commit.branches 44587530 # Number of branches committed
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.int_insts 316365825 # Number of committed integer instructions.
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.function_calls 8007752 # Number of function calls committed.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.bw_lim_events 22930454 # number cycles where commit BW limit reached
|
|
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
|
|
|
system.cpu.rob.rob_reads 610349451 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 931879411 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 2704 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 121815 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.committedInsts 375574794 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 375574794 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.cpi 0.483978 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.483978 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 2.066211 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 2.066211 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 410939724 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 176360806 # number of integer regfile writes
|
|
|
|
|
system.cpu.fp_regfile_reads 160541736 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 106688075 # number of floating regfile writes
|
|
|
|
|
system.cpu.misc_regfile_reads 350572 # number of misc regfile reads
|
|
|
|
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
|
|
|
|
system.cpu.icache.replacements 2140 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 1834.625402 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 58320710 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 4067 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 14339.982788 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.occ_blocks::0 1834.625402 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.occ_percent::0 0.895813 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits 58320710 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits 58320710 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits 58320710 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses 5316 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses 5316 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses 5316 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 168223000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency 168223000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency 168223000 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 58326026 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses 58326026 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses 58326026 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000091 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.000091 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.000091 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 31644.657637 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 31644.657637 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 31644.657637 # average overall miss latency
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits 1249 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 1249 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 1249 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 4067 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 4067 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 4067 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 123582000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 123582000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 123582000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000070 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000070 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000070 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 30386.525695 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 30386.525695 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 30386.525695 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.dcache.replacements 788 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 3295.374104 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 165040256 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 4187 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 39417.304992 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.occ_blocks::0 3295.374104 # Average occupied blocks per context
|
|
|
|
|
system.cpu.dcache.occ_percent::0 0.804535 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 91538987 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits 73501262 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits 165040249 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits 165040249 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 1683 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 19466 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses 21149 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses 21149 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 56075000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 568706500 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency 624781500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 624781500 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 91540670 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses 73520728 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses 165061398 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses 165061398 # number of overall (read+write) accesses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.000265 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.000128 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.000128 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 33318.478907 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 29215.375527 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency 29541.893234 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 29541.893234 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 5000 # number of cycles access was blocked
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2500 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.writebacks 662 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 689 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 16273 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits 16962 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 16962 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 994 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 3193 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 4187 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 4187 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 31676000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 113165000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 144841000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 144841000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000011 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000043 # mshr miss rate for WriteReq accesses
|
2008-02-26 08:20:40 +01:00
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31867.203219 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35441.590980 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 34593.026033 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 34593.026033 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.l2cache.replacements 10 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 4007.918811 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 828 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 4847 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 0.170827 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.occ_blocks::0 3630.264414 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 377.654397 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_percent::0 0.110787 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::1 0.011525 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 755 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 662 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits 62 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits 817 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits 817 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 4306 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 3131 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses 7437 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses 7437 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 148211500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 108422000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 256633500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 256633500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 5061 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 662 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses 3193 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses 8254 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 8254 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.850820 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.980583 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.901018 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.901018 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34419.763121 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34628.553178 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34507.664381 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34507.664381 # average overall miss latency
|
2010-09-09 20:40:19 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 4306 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 3131 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 7437 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 7437 # number of overall MSHR misses
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 134349000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 98553500 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 232902500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 232902500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.850820 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.980583 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.901018 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.901018 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31200.418021 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31476.684765 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31316.727175 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31316.727175 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2007-02-01 00:47:23 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
