2007-02-01 00:47:23 +01:00
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---------- Begin Simulation Statistics ----------
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2011-08-19 22:08:08 +02:00
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sim_seconds 0.090006 # Number of seconds simulated
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sim_ticks 90005685500 # Number of ticks simulated
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2007-02-01 00:47:23 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-08-19 22:08:08 +02:00
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host_inst_rate 147306 # Simulator instruction rate (inst/s)
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host_tick_rate 35301564 # Simulator tick rate (ticks/s)
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host_mem_usage 258568 # Number of bytes of host memory used
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host_seconds 2549.62 # Real time elapsed on the host
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2011-07-10 19:56:09 +02:00
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sim_insts 375574794 # Number of instructions simulated
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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2011-08-19 22:08:08 +02:00
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system.cpu.dtb.read_hits 105557144 # DTB read hits
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system.cpu.dtb.read_misses 98530 # DTB read misses
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system.cpu.dtb.read_acv 48617 # DTB read access violations
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system.cpu.dtb.read_accesses 105655674 # DTB read accesses
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system.cpu.dtb.write_hits 79803143 # DTB write hits
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system.cpu.dtb.write_misses 1575 # DTB write misses
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system.cpu.dtb.write_acv 1 # DTB write access violations
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system.cpu.dtb.write_accesses 79804718 # DTB write accesses
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system.cpu.dtb.data_hits 185360287 # DTB hits
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system.cpu.dtb.data_misses 100105 # DTB misses
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system.cpu.dtb.data_acv 48618 # DTB access violations
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system.cpu.dtb.data_accesses 185460392 # DTB accesses
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system.cpu.itb.fetch_hits 58034543 # ITB hits
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system.cpu.itb.fetch_misses 355 # ITB misses
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2011-07-10 19:56:09 +02:00
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system.cpu.itb.fetch_acv 0 # ITB acv
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2011-08-19 22:08:08 +02:00
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system.cpu.itb.fetch_accesses 58034898 # ITB accesses
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2011-07-10 19:56:09 +02:00
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 215 # Number of system calls
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2011-08-19 22:08:08 +02:00
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system.cpu.numCycles 180011373 # number of cpu cycles simulated
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2011-07-10 19:56:09 +02:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2011-08-19 22:08:08 +02:00
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system.cpu.BPredUnit.lookups 56898591 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 33211966 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 3574908 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 40524300 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 31971911 # Number of BTB hits
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2009-03-07 23:30:55 +01:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2011-08-19 22:08:08 +02:00
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system.cpu.BPredUnit.usedRAS 10712923 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 1454 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 60019462 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 503879026 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 56898591 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 42684834 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 93650208 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 12840667 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 16998273 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 182 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 7695 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 58034543 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 1110351 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 179889864 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.801042 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.244247 # Number of instructions fetched each cycle (Total)
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2011-07-10 19:56:09 +02:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2011-08-19 22:08:08 +02:00
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system.cpu.fetch.rateDist::0 86239656 47.94% 47.94% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 7968101 4.43% 52.37% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 9837104 5.47% 57.84% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 6455150 3.59% 61.43% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 13616411 7.57% 69.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 9477434 5.27% 74.26% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 5920004 3.29% 77.56% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 3509603 1.95% 79.51% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 36866401 20.49% 100.00% # Number of instructions fetched each cycle (Total)
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2011-07-10 19:56:09 +02:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2011-08-19 22:08:08 +02:00
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system.cpu.fetch.rateDist::total 179889864 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.316083 # Number of branch fetches per cycle
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system.cpu.fetch.rate 2.799151 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 66046381 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 13163939 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 87675814 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 3794037 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 9209693 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 10269415 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 4478 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 492179347 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 12338 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 9209693 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 70508732 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 4469526 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 393246 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 86965796 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 8342871 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 478964918 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 37494 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 6850524 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.RenamedOperands 311020883 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 627865578 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 331628214 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 296237364 # Number of floating rename lookups
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2011-07-10 19:56:09 +02:00
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system.cpu.rename.CommittedMaps 259532319 # Number of HB maps that are committed
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2011-08-19 22:08:08 +02:00
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system.cpu.rename.UndoneMaps 51488564 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 38437 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 301 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 23116949 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 110811715 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 85594435 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 10526782 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 6196399 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 433477285 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 262 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 418941176 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 1867414 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 56505676 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 32298658 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 179889864 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 2.328876 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 2.003011 # Number of insts issued each cycle
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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2011-08-19 22:08:08 +02:00
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system.cpu.iq.issued_per_cycle::0 44759242 24.88% 24.88% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 29396949 16.34% 41.22% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 28140071 15.64% 56.87% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 26088939 14.50% 71.37% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 22436504 12.47% 83.84% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 15753855 8.76% 92.60% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 8086358 4.50% 97.09% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 3859739 2.15% 99.24% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 1368207 0.76% 100.00% # Number of insts issued each cycle
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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2011-08-19 22:08:08 +02:00
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system.cpu.iq.issued_per_cycle::total 179889864 # Number of insts issued each cycle
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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2011-08-19 22:08:08 +02:00
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system.cpu.iq.fu_full::IntAlu 136828 1.12% 1.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 0 0.00% 1.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 1.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 42966 0.35% 1.48% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 1217 0.01% 1.49% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 10365 0.09% 1.57% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 1870140 15.36% 16.93% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 1752756 14.40% 31.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 31.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 31.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 31.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 31.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.33% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 5345662 43.91% 75.25% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 3013374 24.75% 100.00% # attempts to use FU when none available
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued
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2011-08-19 22:08:08 +02:00
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system.cpu.iq.FU_type_0::IntAlu 164274346 39.21% 39.22% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 2126487 0.51% 39.73% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.73% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatAdd 33733978 8.05% 47.78% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCmp 7896269 1.88% 49.66% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCvt 2902886 0.69% 50.36% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatMult 16725004 3.99% 54.35% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatDiv 1576072 0.38% 54.73% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.73% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.73% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.73% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.73% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.73% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.73% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.73% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.73% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.73% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.73% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.73% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.73% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.73% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.73% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.73% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.73% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.73% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.73% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.73% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.73% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.73% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemRead 108193841 25.83% 80.55% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 81478712 19.45% 100.00% # Type of FU issued
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iq.FU_type_0::total 418941176 # Type of FU issued
|
|
|
|
|
system.cpu.iq.rate 2.327304 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 12173308 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.029057 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 682905692 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 289620140 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 241865929 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 348907246 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 200439541 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 164655906 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_alu_accesses 252869699 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 178211204 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 14135279 # Number of loads that had data forwarded from stores
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 16057229 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 148927 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 77022 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 12073707 # Number of stores squashed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 215342 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 6 # Number of times an access to memory failed due to the cache being blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 9209693 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 2342336 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 345962 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 459173536 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 2310367 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 110811715 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 85594435 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 262 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 272 # Number of times the IQ has become full, causing a stall
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.iewLSQFullEvents 14 # Number of times the LSQ has become full, causing a stall
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.memOrderViolationEvents 77022 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 3457252 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 554336 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 4011588 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 410317513 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 105704327 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 8623663 # Number of squashed instructions skipped in execute
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.exec_nop 25695989 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_refs 185509104 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 48173918 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 79804777 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 2.279398 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 407775826 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 406521835 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 197958297 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 277706216 # num instructions consuming a value
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.iew.wb_rate 2.258312 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.712834 # average fanout of values written-back
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
|
|
|
system.cpu.commit.commitCommittedInsts 398664569 # The number of committed instructions
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.commitSquashedInsts 60526277 # The number of squashed insts skipped by commit
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.branchMispredicts 3570557 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 170680171 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 2.335740 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 2.860101 # Number of insts commited each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::0 71080695 41.65% 41.65% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 25597473 15.00% 56.64% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 15025586 8.80% 65.45% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 12350485 7.24% 72.68% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 8728325 5.11% 77.80% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 6123095 3.59% 81.38% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 5311766 3.11% 84.50% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 3136870 1.84% 86.33% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 23325876 13.67% 100.00% # Number of insts commited each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::total 170680171 # Number of insts commited each cycle
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.count 398664569 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
|
|
|
system.cpu.commit.refs 168275214 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 94754486 # Number of loads committed
|
|
|
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
|
|
|
system.cpu.commit.branches 44587530 # Number of branches committed
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.int_insts 316365825 # Number of committed integer instructions.
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.function_calls 8007752 # Number of function calls committed.
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.commit.bw_lim_events 23325876 # number cycles where commit BW limit reached
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.rob.rob_reads 606542164 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 927610224 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 2703 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 121509 # Total number of cycles that the CPU has spent unscheduled due to idling
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.committedInsts 375574794 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 375574794 # Number of Instructions Simulated
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.cpi 0.479296 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.479296 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 2.086395 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 2.086395 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 410036032 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 175891320 # number of integer regfile writes
|
|
|
|
|
system.cpu.fp_regfile_reads 159397664 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 105955330 # number of floating regfile writes
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.misc_regfile_reads 350572 # number of misc regfile reads
|
|
|
|
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.replacements 2104 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 1835.532395 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 58029268 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 4030 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 14399.322084 # Average number of references to valid blocks.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.occ_blocks::0 1835.532395 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.occ_percent::0 0.896256 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits 58029268 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits 58029268 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits 58029268 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses 5275 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses 5275 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses 5275 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 167800500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency 167800500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency 167800500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 58034543 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses 58034543 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses 58034543 # number of overall (read+write) accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000091 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.000091 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.000091 # miss rate for overall accesses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 31810.521327 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 31810.521327 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 31810.521327 # average overall miss latency
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits 1245 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 1245 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 1245 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 4030 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 4030 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 4030 # number of overall MSHR misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 123364000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 123364000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 123364000 # number of overall MSHR miss cycles
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000069 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000069 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000069 # mshr miss rate for overall accesses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 30611.414392 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 30611.414392 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 30611.414392 # average overall mshr miss latency
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.replacements 783 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 3295.270928 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 164706127 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 4182 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 39384.535390 # Average number of references to valid blocks.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.occ_blocks::0 3295.270928 # Average occupied blocks per context
|
|
|
|
|
system.cpu.dcache.occ_percent::0 0.804510 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 91204849 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits 73501271 # number of WriteReq hits
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.demand_hits 164706120 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits 164706120 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 1662 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 19457 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses 21119 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses 21119 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 55598500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 568882000 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency 624480500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 624480500 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 91206511 # number of ReadReq accesses(hits+misses)
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.WriteReq_accesses 73520728 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses)
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.demand_accesses 164727239 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses 164727239 # number of overall (read+write) accesses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.000265 # miss rate for WriteReq accesses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.demand_miss_rate 0.000128 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.000128 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 33452.767750 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 29237.909236 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency 29569.605568 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 29569.605568 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 3875 # average number of cycles each access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.writebacks 661 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 671 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 16266 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits 16937 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 16937 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 991 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 3191 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 4182 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 4182 # number of overall MSHR misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 31558000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 113135500 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 144693500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 144693500 # number of overall MSHR miss cycles
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000011 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000043 # mshr miss rate for WriteReq accesses
|
2008-02-26 08:20:40 +01:00
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31844.601413 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35454.559699 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 34599.115256 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 34599.115256 # average overall mshr miss latency
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.replacements 9 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 4001.784111 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 795 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 4839 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 0.164290 # Average number of references to valid blocks.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.occ_blocks::0 3624.039188 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 377.744922 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_percent::0 0.110597 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::1 0.011528 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 722 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 661 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits 60 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits 782 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits 782 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 4299 # number of ReadReq misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_misses 3131 # number of ReadExReq misses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.demand_misses 7430 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses 7430 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 147966000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 108412500 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 256378500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 256378500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 5021 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 661 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses 3191 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses 8212 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 8212 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.856204 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.981197 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.904774 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.904774 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34418.702024 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34625.519004 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34505.854643 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34505.854643 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 3000 # number of cycles access was blocked
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3000 # average number of cycles each access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 4299 # number of ReadReq MSHR misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 3131 # number of ReadExReq MSHR misses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_misses 7430 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 7430 # number of overall MSHR misses
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 134126000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 98548000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 232674000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 232674000 # number of overall MSHR miss cycles
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.856204 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.981197 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.904774 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.904774 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31199.348686 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31474.928138 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31315.477793 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31315.477793 # average overall mshr miss latency
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2007-02-01 00:47:23 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
