gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.400983                       # Number of seconds simulated
sim_ticks                                2400982506000                       # Number of ticks simulated
final_tick                               2400982506000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 112943                       # Simulator instruction rate (inst/s)
host_op_rate                                   135898                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             4496473277                       # Simulator tick rate (ticks/s)
host_mem_usage                                 411684                       # Number of bytes of host memory used
host_seconds                                   533.97                       # Real time elapsed on the host
sim_insts                                    60307964                       # Number of instructions simulated
sim_ops                                      72565708                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::realview.clcd    114819072                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           493064                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          6826968                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst            75520                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           799936                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker          704                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst           188416                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data          1451264                       # Number of bytes read from this memory
system.physmem.bytes_read::total            124655200                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       493064                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst        75520                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst       188416                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          757000                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      3741312                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data       1144164                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data        159264                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu2.data       1712388                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6757128                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd      14352384                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             13916                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            106697                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              1180                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             12499                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker           11                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst              2944                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data             22676                       # Number of read requests responded to by this memory
system.physmem.num_reads::total              14512311                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           58458                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data           286041                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data            39816                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu2.data           428097                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               812412                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        47821703                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker            27                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            53                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              205359                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             2843406                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker            27                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               31454                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              333170                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker           293                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst               78475                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data              604446                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                51918412                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         205359                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          31454                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst          78475                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             315288                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1558242                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data             476540                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data              66333                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu2.data             713203                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2814318                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1558242                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       47821703                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker           27                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           53                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             205359                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            3319946                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker           27                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              31454                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             399503                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker          293                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst              78475                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data            1317649                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               54732730                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                      13448319                       # Number of read requests accepted
system.physmem.writeReqs                       485647                       # Number of write requests accepted
system.physmem.readBursts                    13448319                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     485647                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                860692416                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   3019520                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                 109787968                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                3006628                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                  438446                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs           2870                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0              835559                       # Per bank write bursts
system.physmem.perBankRdBursts::1              835684                       # Per bank write bursts
system.physmem.perBankRdBursts::2              835582                       # Per bank write bursts
system.physmem.perBankRdBursts::3              835955                       # Per bank write bursts
system.physmem.perBankRdBursts::4              836860                       # Per bank write bursts
system.physmem.perBankRdBursts::5              838029                       # Per bank write bursts
system.physmem.perBankRdBursts::6              838426                       # Per bank write bursts
system.physmem.perBankRdBursts::7              839444                       # Per bank write bursts
system.physmem.perBankRdBursts::8              841128                       # Per bank write bursts
system.physmem.perBankRdBursts::9              843519                       # Per bank write bursts
system.physmem.perBankRdBursts::10             843777                       # Per bank write bursts
system.physmem.perBankRdBursts::11             843721                       # Per bank write bursts
system.physmem.perBankRdBursts::12             845312                       # Per bank write bursts
system.physmem.perBankRdBursts::13             845603                       # Per bank write bursts
system.physmem.perBankRdBursts::14             845260                       # Per bank write bursts
system.physmem.perBankRdBursts::15             844460                       # Per bank write bursts
system.physmem.perBankWrBursts::0                2621                       # Per bank write bursts
system.physmem.perBankWrBursts::1                2605                       # Per bank write bursts
system.physmem.perBankWrBursts::2                2850                       # Per bank write bursts
system.physmem.perBankWrBursts::3                3117                       # Per bank write bursts
system.physmem.perBankWrBursts::4                3557                       # Per bank write bursts
system.physmem.perBankWrBursts::5                3522                       # Per bank write bursts
system.physmem.perBankWrBursts::6                2837                       # Per bank write bursts
system.physmem.perBankWrBursts::7                2549                       # Per bank write bursts
system.physmem.perBankWrBursts::8                2654                       # Per bank write bursts
system.physmem.perBankWrBursts::9                2632                       # Per bank write bursts
system.physmem.perBankWrBursts::10               2402                       # Per bank write bursts
system.physmem.perBankWrBursts::11               2522                       # Per bank write bursts
system.physmem.perBankWrBursts::12               3817                       # Per bank write bursts
system.physmem.perBankWrBursts::13               3843                       # Per bank write bursts
system.physmem.perBankWrBursts::14               3141                       # Per bank write bursts
system.physmem.perBankWrBursts::15               2511                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    2398981428000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                13409008                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                   39311                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                 467913                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  17734                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    878886                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    855155                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    852902                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                    940592                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                    861312                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                    914649                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                   2399113                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                   2323436                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                   3041002                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                     91615                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                    84284                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                    79661                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                    76726                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                    16593                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                    16236                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                    16118                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       39                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                        99                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                        96                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                        95                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                        93                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                        93                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                        92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                        92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                        92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                        90                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                        90                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                       90                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                       90                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                       90                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                       88                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                       88                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2036                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2365                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     2560                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     2603                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     2671                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     2642                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     2604                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     2620                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     2614                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     2693                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     2702                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     2526                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     2527                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     2628                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     2514                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     2506                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     2513                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     2480                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       866402                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      996.895132                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     964.187701                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     145.697526                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127           8320      0.96%      0.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255         8911      1.03%      1.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6111      0.71%      2.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511          785      0.09%      2.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639          956      0.11%      2.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767          773      0.09%      2.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         7768      0.90%      3.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          290      0.03%      3.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151       832488     96.09%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         866402                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          2583                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean      5206.469222                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev    249565.705681                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-524287         2582     99.96%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1.25829e+07-1.31072e+07            1      0.04%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            2583                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          2583                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        18.265583                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.091885                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        2.157240                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::1                   3      0.12%      0.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::2                   1      0.04%      0.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::3                   2      0.08%      0.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4                   2      0.08%      0.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::5                   1      0.04%      0.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::6                   1      0.04%      0.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8                   2      0.08%      0.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::9                   1      0.04%      0.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::13                  3      0.12%      0.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::15                  4      0.15%      0.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16                537     20.79%     21.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                  7      0.27%     21.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                754     29.19%     51.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19               1050     40.65%     91.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                100      3.87%     95.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 31      1.20%     96.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 20      0.77%     97.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                 15      0.58%     98.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                  9      0.35%     98.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                  3      0.12%     98.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26                  7      0.27%     98.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27                  5      0.19%     99.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28                  5      0.19%     99.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::29                  5      0.19%     99.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30                  6      0.23%     99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::31                  4      0.15%     99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32                  5      0.19%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            2583                       # Writes before turning the bus around for reads
system.physmem.totQLat                   346447958000                       # Total ticks spent queuing
system.physmem.totMemAccLat              598603939250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                  67241595000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       25761.43                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  44511.43                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         358.48                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.26                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       45.73                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.25                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           2.81                       # Data bus utilization in percentage
system.physmem.busUtilRead                       2.80                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         7.91                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         2.57                       # Average write queue length when enqueuing
system.physmem.readRowHits                   12588353                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     40744                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   93.61                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  86.32                       # Row buffer hit rate for writes
system.physmem.avgGap                       172167.88                       # Average gap between requests
system.physmem.pageHitRate                      93.58                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     2165142880250                       # Time in different power states
system.physmem.memoryStateTime::REF       80173860000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT      155659356000                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            8                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                8                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            8                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput                     55731244                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq            13775425                       # Transaction distribution
system.membus.trans_dist::ReadResp           13775425                       # Transaction distribution
system.membus.trans_dist::WriteReq             471057                       # Transaction distribution
system.membus.trans_dist::WriteResp            471057                       # Transaction distribution
system.membus.trans_dist::Writeback             17734                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             2870                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            2870                       # Transaction distribution
system.membus.trans_dist::ReadExReq             31339                       # Transaction distribution
system.membus.trans_dist::ReadExResp            31339                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       722736                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio          440                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1037922                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      1761100                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     26818016                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total     26818016                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               28579116                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave       726717                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio          880                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port      5522532                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total      6250133                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    107272064                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total    107272064                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total           113522197                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus              133809743                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy           411651000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy              449000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy                1500                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer6.occupancy         14677819500                       # Layer occupancy (ticks)
system.membus.reqLayer6.utilization               0.6                       # Layer utilization (%)
system.membus.respLayer1.occupancy         1677943291                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer2.occupancy        33210614750                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              1.4                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.l2c.tags.replacements                    63162                       # number of replacements
system.l2c.tags.tagsinuse                50410.338960                       # Cycle average of tags in use
system.l2c.tags.total_refs                    1759139                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   128553                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    13.684154                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle             2389834567500                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   36865.555388                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker     0.000018                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000123                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4868.284859                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     3674.892610                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.993335                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      794.582710                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data      806.547655                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker     9.832999                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst     1730.563101                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data     1659.086161                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.562524                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.074284                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.056074                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000015                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.012124                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.012307                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000150                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst       0.026406                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data       0.025316                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.769201                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023           11                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        65380                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4           10                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          351                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         3043                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         6074                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        55872                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.000168                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.997620                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 17759906                       # Number of tag accesses
system.l2c.tags.data_accesses                17759906                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker         8189                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         2843                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             435869                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             178927                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker         2011                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker          887                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             119100                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data              59229                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker        19905                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker         6074                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst             331991                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data             135602                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1300627                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          597941                       # number of Writeback hits
system.l2c.Writeback_hits::total               597941                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data               9                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data               4                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data              14                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  27                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            52345                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            17186                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data            43999                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               113530                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker          8189                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          2843                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              435869                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              231272                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          2011                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker           887                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              119100                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data               76415                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker         19905                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker          6074                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst              331991                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data              179601                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1414157                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         8189                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         2843                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             435869                       # number of overall hits
system.l2c.overall_hits::cpu0.data             231272                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         2011                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker          887                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             119100                       # number of overall hits
system.l2c.overall_hits::cpu1.data              76415                       # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker        19905                       # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker         6074                       # number of overall hits
system.l2c.overall_hits::cpu2.inst             331991                       # number of overall hits
system.l2c.overall_hits::cpu2.data             179601                       # number of overall hits
system.l2c.overall_hits::total                1414157                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             7290                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             6276                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             1180                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             1222                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.dtb.walker           11                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst             2947                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data             2622                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                21552                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          1087                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data           481                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data          1336                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2904                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         101003                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          11529                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data          20863                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             133395                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              7290                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            107279                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              1180                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             12751                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.dtb.walker           11                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst              2947                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data             23485                       # number of demand (read+write) misses
system.l2c.demand_misses::total                154947                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             7290                       # number of overall misses
system.l2c.overall_misses::cpu0.data           107279                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             1180                       # number of overall misses
system.l2c.overall_misses::cpu1.data            12751                       # number of overall misses
system.l2c.overall_misses::cpu2.dtb.walker           11                       # number of overall misses
system.l2c.overall_misses::cpu2.inst             2947                       # number of overall misses
system.l2c.overall_misses::cpu2.data            23485                       # number of overall misses
system.l2c.overall_misses::total               154947                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker        74500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst     84908250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data     91869750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker       850000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst    219075000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data    202750495                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total      599527995                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data        46998                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data       162493                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total       209491                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    821599498                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data   1528087699                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   2349687197                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker        74500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst     84908250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    913469248                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.dtb.walker       850000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst    219075000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data   1730838194                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      2949215192                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker        74500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst     84908250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    913469248                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.dtb.walker       850000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst    219075000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data   1730838194                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     2949215192                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker         8190                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         2845                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         443159                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         185203                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker         2012                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker          887                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         120280                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data          60451                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.dtb.walker        19916                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.itb.walker         6074                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst         334938                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data         138224                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1322179                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       597941                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           597941                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         1096                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data          485                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data         1350                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            2931                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       153348                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        28715                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data        64862                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           246925                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         8190                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         2845                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          443159                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          338551                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         2012                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker          887                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          120280                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           89166                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.dtb.walker        19916                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.itb.walker         6074                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst          334938                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data          203086                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1569104                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         8190                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         2845                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         443159                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         338551                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         2012                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker          887                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         120280                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          89166                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.dtb.walker        19916                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.itb.walker         6074                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst         334938                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data         203086                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1569104                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000122                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000703                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.016450                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.033887                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000497                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.009810                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.020215                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.000552                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst      0.008799                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data      0.018969                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.016300                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.991788                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.991753                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data     0.989630                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.990788                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.658652                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.401497                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data     0.321652                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.540225                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000122                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000703                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.016450                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.316877                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000497                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.009810                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.143003                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.dtb.walker     0.000552                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.008799                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.115641                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.098749                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000122                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000703                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.016450                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.316877                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000497                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.009810                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.143003                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.dtb.walker     0.000552                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.008799                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.115641                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.098749                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        74500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 71956.144068                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 75179.828151                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 77272.727273                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 74338.310146                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data 77326.657132                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 27817.742901                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data    97.708940                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data   121.626497                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total    72.138774                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71263.726082                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 73243.910224                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 17614.507268                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        74500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 71956.144068                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 71639.028155                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 77272.727273                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 74338.310146                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 73699.731488                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 19033.703086                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        74500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 71956.144068                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 71639.028155                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 77272.727273                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 74338.310146                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 73699.731488                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 19033.703086                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               58458                       # number of writebacks
system.l2c.writebacks::total                    58458                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu2.inst             3                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu2.data             8                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                11                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst              3                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.data              8                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 11                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst             3                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.data             8                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                11                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         1180                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         1222                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker           11                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst         2944                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data         2614                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total            7972                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data          481                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data         1336                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         1817                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        11529                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data        20863                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         32392                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         1180                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        12751                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.dtb.walker           11                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst         2944                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data        23477                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total            40364                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         1180                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        12751                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.dtb.walker           11                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst         2944                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data        23477                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total           40364                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker        62500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     69967750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data     76634250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker       715000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst    182019500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data    169748495                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total    499147495                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      4810481                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data     13374835                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     18185316                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    675391502                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   1269014301                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   1944405803                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker        62500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst     69967750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    752025752                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker       715000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst    182019500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data   1438762796                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   2443553298                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker        62500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst     69967750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    752025752                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker       715000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst    182019500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data   1438762796                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   2443553298                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  25042687500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data  25560602500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total  50603290000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    991271590                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data   9138698000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total  10129969590                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data  26033959090                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data  34699300500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  60733259590                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000497                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.009810                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.020215                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000552                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.008790                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.018911                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.006029                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.991753                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.989630                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.619925                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.401497                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.321652                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.131182                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000497                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.009810                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.143003                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000552                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.008790                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.115601                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.025724                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000497                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.009810                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.143003                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000552                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.008790                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.115601                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.025724                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59294.703390                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62712.152209                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker        65000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 61827.275815                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 64938.215379                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 62612.580908                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10011.104042                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10008.429279                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58581.967387                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 60826.070124                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 60027.346351                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59294.703390                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58977.786213                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker        65000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 61827.275815                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61283.928781                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 60537.937221                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59294.703390                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58977.786213                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker        65000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 61827.275815                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61283.928781                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 60537.937221                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.toL2Bus.throughput                    59108244                       # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq            1059674                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           1059674                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq            471057                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp           471057                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           275568                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            1835                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp           1835                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq            93577                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp           93577                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side       911138                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2522746                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        20145                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        55378                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               3509407                       # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     29133952                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     38939733                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        27844                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        87712                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total           68189241                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus             141801951                       # Total data (bytes)
system.toL2Bus.snoop_data_through_bus          115908                       # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy         2288858155                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        2052757055                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        1915102818                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy          13212439                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          33686507                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.iobus.throughput                      48817267                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq             13767391                       # Transaction distribution
system.iobus.trans_dist::ReadResp            13767391                       # Transaction distribution
system.iobus.trans_dist::WriteReq                2985                       # Transaction distribution
system.iobus.trans_dist::WriteResp               2985                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        12256                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         3140                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           18                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio          288                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio       706746                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       722736                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     26818016                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total     26818016                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                27540752                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        16027                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio         6280                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio           36                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio          576                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio       703222                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total       726717                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    107272064                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total    107272064                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total            107998781                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus               117209403                       # Total data (bytes)
system.iobus.reqLayer0.occupancy              8657000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy              1570000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                18000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy               144000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy            353820000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer12.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy         13409008000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
system.iobus.respLayer0.occupancy           719751000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy         33775984250                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               1.4                       # Layer utilization (%)
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                     6543805                       # DTB read hits
system.cpu0.dtb.read_misses                      5435                       # DTB read misses
system.cpu0.dtb.write_hits                    6063639                       # DTB write hits
system.cpu0.dtb.write_misses                     1808                       # DTB write misses
system.cpu0.dtb.flush_tlb                         554                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                493                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                     23                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    5223                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   107                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      162                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                 6549240                       # DTB read accesses
system.cpu0.dtb.write_accesses                6065447                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         12607444                       # DTB hits
system.cpu0.dtb.misses                           7243                       # DTB misses
system.cpu0.dtb.accesses                     12614687                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.inst_hits                    30119411                       # ITB inst hits
system.cpu0.itb.inst_misses                      2986                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                         554                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                493                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                     23                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2362                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                30122397                       # ITB inst accesses
system.cpu0.itb.hits                         30119411                       # DTB hits
system.cpu0.itb.misses                           2986                       # DTB misses
system.cpu0.itb.accesses                     30122397                       # DTB accesses
system.cpu0.numCycles                       109377986                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   29708958                       # Number of instructions committed
system.cpu0.committedOps                     36436691                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses             32091710                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                  4289                       # Number of float alu accesses
system.cpu0.num_func_calls                    1119227                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts      3806697                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                    32091710                       # number of integer instructions
system.cpu0.num_fp_insts                         4289                       # number of float instructions
system.cpu0.num_int_register_reads           59433720                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          21150393                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                3327                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes                964                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           109113758                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes           14198144                       # number of times the CC registers were written
system.cpu0.num_mem_refs                     13068134                       # number of memory refs
system.cpu0.num_load_insts                    6718957                       # Number of load instructions
system.cpu0.num_store_insts                   6349177                       # Number of store instructions
system.cpu0.num_idle_cycles              107075141.411044                       # Number of idle cycles
system.cpu0.num_busy_cycles              2302844.588956                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.021054                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.978946                       # Percentage of idle cycles
system.cpu0.Branches                          5297571                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                11842      0.03%      0.03% # Class of executed instruction
system.cpu0.op_class::IntAlu                 23375924     64.04%     64.07% # Class of executed instruction
system.cpu0.op_class::IntMult                   45526      0.12%     64.20% # Class of executed instruction
system.cpu0.op_class::IntDiv                        0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc              1430      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     64.20% # Class of executed instruction
system.cpu0.op_class::MemRead                 6718957     18.41%     82.61% # Class of executed instruction
system.cpu0.op_class::MemWrite                6349177     17.39%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                  36502856                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   82922                       # number of quiesce instructions executed
system.cpu0.icache.tags.replacements           899179                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.616650                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           41225487                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           899691                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            45.821829                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       7765042250                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   495.273634                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst     5.912581                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst    10.430435                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.967331                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.011548                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst     0.020372                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999251                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          137                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          210                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          164                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         43052663                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        43052663                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     29678002                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst      7860593                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst      3686892                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       41225487                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     29678002                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst      7860593                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst      3686892                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        41225487                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     29678002                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst      7860593                       # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst      3686892                       # number of overall hits
system.cpu0.icache.overall_hits::total       41225487                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       443773                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst       120537                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst       363173                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       927483                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       443773                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst       120537                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst       363173                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        927483                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       443773                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst       120537                       # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst       363173                       # number of overall misses
system.cpu0.icache.overall_misses::total       927483                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   1643390750                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   4873068412                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   6516459162                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst   1643390750                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst   4873068412                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   6516459162                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst   1643390750                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst   4873068412                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   6516459162                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     30121775                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst      7981130                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst      4050065                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     42152970                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     30121775                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst      7981130                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst      4050065                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     42152970                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     30121775                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst      7981130                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst      4050065                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     42152970                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014733                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015103                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.089671                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.022003                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014733                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015103                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst     0.089671                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.022003                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014733                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015103                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst     0.089671                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.022003                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13633.911164                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13418.036065                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  7025.960758                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13633.911164                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13418.036065                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  7025.960758                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13633.911164                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13418.036065                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  7025.960758                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         3564                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              217                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    16.423963                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        27790                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        27790                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst        27790                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        27790                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst        27790                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        27790                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       120537                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       335383                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       455920                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       120537                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst       335383                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       455920                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       120537                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst       335383                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       455920                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1401871250                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   3957248170                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   5359119420                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1401871250                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   3957248170                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   5359119420                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1401871250                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   3957248170                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   5359119420                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015103                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.082809                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.010816                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015103                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.082809                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.010816                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015103                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.082809                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.010816                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11630.215204                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11799.191283                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11754.517064                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11630.215204                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11799.191283                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11754.517064                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11630.215204                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11799.191283                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11754.517064                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements           630291                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.997117                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           21342473                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           630803                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            33.833817                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         21757000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   497.608321                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data     7.871908                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data     6.516888                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.971891                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.015375                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data     0.012728                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          194                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          298                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           20                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         92219903                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        92219903                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data      5361652                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data      1457794                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data      4730320                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       11549766                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      5493900                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      1274863                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data      2443484                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       9212247                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data        53400                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data        14515                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu2.data        23676                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total        91591                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       122744                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        31335                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        84381                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       238460                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       128815                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data        32780                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu2.data        85814                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       247409                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     10855552                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data      2732657                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data      7173804                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        20762013                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     10908952                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data      2747172                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data      7197480                       # number of overall hits
system.cpu0.dcache.overall_hits::total       20853604                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       142161                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data        45809                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data       256649                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       444619                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       154444                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data        29861                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data       820607                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1004912                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data        36971                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data        17584                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu2.data        41738                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total        96293                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6071                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         1446                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         4461                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        11978                       # number of LoadLockedReq misses
system.cpu0.dcache.demand_misses::cpu0.data       296605                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data        75670                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data      1077256                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       1449531                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       333576                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data        93254                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data      1118994                       # number of overall misses
system.cpu0.dcache.overall_misses::total      1545824                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data    618572999                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   3601097882                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   4219670881                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1127965983                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  26744225136                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  27872191119                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     19459500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data     65741241                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total     85200741                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data   1746538982                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data  30345323018                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  32091862000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data   1746538982                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data  30345323018                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  32091862000                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      5503813                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data      1503603                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data      4986969                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     11994385                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      5648344                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      1304724                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data      3264091                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     10217159                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data        90371                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        32099                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data        65414                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       187884                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       128815                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        32781                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        88842                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       250438                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       128815                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        32780                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        85814                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       247409                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     11152157                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data      2808327                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data      8251060                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     22211544                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     11242528                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data      2840426                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data      8316474                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     22399428                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.025830                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.030466                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.051464                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.037069                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.027343                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.022887                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.251404                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.098355                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.409102                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.547805                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.638059                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.512513                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.047130                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.044111                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.050213                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.047828                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.026596                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.026945                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data     0.130560                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.065260                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029671                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.032831                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data     0.134551                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.069012                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13503.307189                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14031.217273                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total  9490.532076                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37773.885101                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32590.783574                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 27735.952122                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13457.468880                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14736.884331                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  7113.102438                       # average LoadLockedReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23080.996194                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 28169.091672                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 22139.479597                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18728.837176                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 27118.396540                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 20760.359523                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs        38637                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets         6212                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs             5775                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets            192                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs     6.690390                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    32.354167                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       597941                       # number of writebacks
system.cpu0.dcache.writebacks::total           597941                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           82                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       146159                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       146241                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data          661                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       754425                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total       755086                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data          467                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total          467                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data          743                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data       900584                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total       901327                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data          743                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data       900584                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total       901327                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        45727                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       110490                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       156217                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        29200                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        66182                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total        95382                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        13278                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data        23770                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total        37048                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         1446                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         3994                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         5440                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data        74927                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data       176672                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       251599                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data        88205                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data       200442                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       288647                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data    526256000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   1348662754                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   1874918754                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1036082517                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   2113089467                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   3149171984                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    204786500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data    440091753                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total    644878253                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     16565500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     51817259                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     68382759                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   1562338517                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   3461752221                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   5024090738                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   1767125017                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   3901843974                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total   5668968991                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  27358748000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  27904372000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  55263120000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1501669410                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data  14569249955                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  16070919365                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  28860417410                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  42473621955                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  71334039365                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.030412                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.022156                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.013024                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.022380                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.020276                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.009335                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.413658                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.363378                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.197185                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.044111                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.044956                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.021722                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.026680                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.021412                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.011327                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.031053                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.024102                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.012886                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11508.649157                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12206.197430                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12002.014851                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35482.277979                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 31928.461923                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33016.418024                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15422.992921                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 18514.587842                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17406.560489                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11456.085754                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12973.775413                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12570.360110                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20851.475663                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19594.232368                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19968.643508                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20034.295301                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19466.199569                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19639.798754                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                     1746639                       # DTB read hits
system.cpu1.dtb.read_misses                      1917                       # DTB read misses
system.cpu1.dtb.write_hits                    1378449                       # DTB write hits
system.cpu1.dtb.write_misses                      367                       # DTB write misses
system.cpu1.dtb.flush_tlb                         552                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                251                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                     10                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    1626                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                    33                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                       77                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                 1748556                       # DTB read accesses
system.cpu1.dtb.write_accesses                1378816                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                          3125088                       # DTB hits
system.cpu1.dtb.misses                           2284                       # DTB misses
system.cpu1.dtb.accesses                      3127372                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.inst_hits                     7981130                       # ITB inst hits
system.cpu1.itb.inst_misses                      1058                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                         552                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                251                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                     10                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                     834                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                 7982188                       # ITB inst accesses
system.cpu1.itb.hits                          7981130                       # DTB hits
system.cpu1.itb.misses                           1058                       # DTB misses
system.cpu1.itb.accesses                      7982188                       # DTB accesses
system.cpu1.numCycles                       582833153                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                    7797141                       # Number of instructions committed
system.cpu1.committedOps                      9191219                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses              8219243                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                  1689                       # Number of float alu accesses
system.cpu1.num_func_calls                     289029                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts       993030                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                     8219243                       # number of integer instructions
system.cpu1.num_fp_insts                         1689                       # number of float instructions
system.cpu1.num_int_register_reads           14554839                       # number of times the integer registers were read
system.cpu1.num_int_register_writes           5500250                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                1177                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes                512                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads            33218155                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes            3793046                       # number of times the CC registers were written
system.cpu1.num_mem_refs                      3251661                       # number of memory refs
system.cpu1.num_load_insts                    1804549                       # Number of load instructions
system.cpu1.num_store_insts                   1447112                       # Number of store instructions
system.cpu1.num_idle_cycles              548698663.963538                       # Number of idle cycles
system.cpu1.num_busy_cycles              34134489.036462                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.058566                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.941434                       # Percentage of idle cycles
system.cpu1.Branches                          1360376                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                 4595      0.05%      0.05% # Class of executed instruction
system.cpu1.op_class::IntAlu                  6078995     65.05%     65.10% # Class of executed instruction
system.cpu1.op_class::IntMult                   10163      0.11%     65.20% # Class of executed instruction
system.cpu1.op_class::IntDiv                        0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     65.20% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc               281      0.00%     65.21% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     65.21% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     65.21% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     65.21% # Class of executed instruction
system.cpu1.op_class::MemRead                 1804549     19.31%     84.52% # Class of executed instruction
system.cpu1.op_class::MemWrite                1447112     15.48%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                   9345695                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu2.branchPred.lookups                5844133                       # Number of BP lookups
system.cpu2.branchPred.condPredicted          4389690                       # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect           248799                       # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups             3701982                       # Number of BTB lookups
system.cpu2.branchPred.BTBHits                2861782                       # Number of BTB hits
system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct            77.304050                       # BTB Hit Percentage
system.cpu2.branchPred.usedRAS                 588875                       # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect             15609                       # Number of incorrect RAS predictions.
system.cpu2.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu2.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu2.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu2.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu2.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu2.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu2.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu2.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu2.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu2.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu2.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu2.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu2.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu2.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu2.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu2.dtb.inst_hits                           0                       # ITB inst hits
system.cpu2.dtb.inst_misses                         0                       # ITB inst misses
system.cpu2.dtb.read_hits                    13926534                       # DTB read hits
system.cpu2.dtb.read_misses                     28241                       # DTB read misses
system.cpu2.dtb.write_hits                    3979346                       # DTB write hits
system.cpu2.dtb.write_misses                     9743                       # DTB write misses
system.cpu2.dtb.flush_tlb                         550                       # Number of times complete TLB was flushed
system.cpu2.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu2.dtb.flush_tlb_mva_asid                695                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.dtb.flush_tlb_asid                     30                       # Number of times TLB was flushed by ASID
system.cpu2.dtb.flush_entries                    2739                       # Number of entries that have been flushed from TLB
system.cpu2.dtb.align_faults                      445                       # Number of TLB faults due to alignment restrictions
system.cpu2.dtb.prefetch_faults                   255                       # Number of TLB faults due to prefetch
system.cpu2.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu2.dtb.perms_faults                      656                       # Number of TLB faults due to permissions restrictions
system.cpu2.dtb.read_accesses                13954775                       # DTB read accesses
system.cpu2.dtb.write_accesses                3989089                       # DTB write accesses
system.cpu2.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu2.dtb.hits                         17905880                       # DTB hits
system.cpu2.dtb.misses                          37984                       # DTB misses
system.cpu2.dtb.accesses                     17943864                       # DTB accesses
system.cpu2.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu2.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu2.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu2.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu2.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu2.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu2.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu2.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu2.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu2.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu2.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu2.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu2.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu2.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu2.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu2.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu2.itb.inst_hits                     4053038                       # ITB inst hits
system.cpu2.itb.inst_misses                      6578                       # ITB inst misses
system.cpu2.itb.read_hits                           0                       # DTB read hits
system.cpu2.itb.read_misses                         0                       # DTB read misses
system.cpu2.itb.write_hits                          0                       # DTB write hits
system.cpu2.itb.write_misses                        0                       # DTB write misses
system.cpu2.itb.flush_tlb                         550                       # Number of times complete TLB was flushed
system.cpu2.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu2.itb.flush_tlb_mva_asid                695                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.itb.flush_tlb_asid                     30                       # Number of times TLB was flushed by ASID
system.cpu2.itb.flush_entries                    2058                       # Number of entries that have been flushed from TLB
system.cpu2.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu2.itb.perms_faults                     2441                       # Number of TLB faults due to permissions restrictions
system.cpu2.itb.read_accesses                       0                       # DTB read accesses
system.cpu2.itb.write_accesses                      0                       # DTB write accesses
system.cpu2.itb.inst_accesses                 4059616                       # ITB inst accesses
system.cpu2.itb.hits                          4053038                       # DTB hits
system.cpu2.itb.misses                           6578                       # DTB misses
system.cpu2.itb.accesses                      4059616                       # DTB accesses
system.cpu2.numCycles                        88208146                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles          10487397                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts                      32911643                       # Number of instructions fetch has processed
system.cpu2.fetch.Branches                    5844133                       # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches           3450657                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles                     74966701                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles                 679472                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.TlbCycles                     80302                       # Number of cycles fetch has spent waiting for tlb
system.cpu2.fetch.MiscStallCycles                 630                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles              972                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles        72243                       # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles      1263867                       # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles          410                       # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines                  4050067                       # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes               153217                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.ItlbSquashes                   2804                       # Number of outstanding ITLB misses that were squashed
system.cpu2.fetch.rateDist::samples          87212188                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             0.443226                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            1.629212                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0                79899565     91.62%     91.62% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                  625094      0.72%     92.33% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                  698013      0.80%     93.13% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                  764181      0.88%     94.01% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                  868461      1.00%     95.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                  574503      0.66%     95.66% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                  981504      1.13%     96.79% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                  301305      0.35%     97.13% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                 2499562      2.87%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total            87212188                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate                 0.066254                       # Number of branch fetches per cycle
system.cpu2.fetch.rate                       0.373113                       # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles                 8569138                       # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles             72587758                       # Number of cycles decode is blocked
system.cpu2.decode.RunCycles                  4831209                       # Number of cycles decode is running
system.cpu2.decode.UnblockCycles               941079                       # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles                281926                       # Number of cycles decode is squashing
system.cpu2.decode.BranchResolved              736866                       # Number of times decode resolved a branch
system.cpu2.decode.BranchMispred                58789                       # Number of times decode detected a branch misprediction
system.cpu2.decode.DecodedInsts              34844703                       # Number of instructions handled by decode
system.cpu2.decode.SquashedInsts               196626                       # Number of squashed instructions handled by decode
system.cpu2.rename.SquashCycles                281926                       # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles                 9031224                       # Number of cycles rename is idle
system.cpu2.rename.BlockCycles               19204705                       # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles      13140033                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles                  5253439                       # Number of cycles rename is running
system.cpu2.rename.UnblockCycles             40299841                       # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts              33794581                       # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents                74120                       # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents              29618551                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.LQFullEvents              37683898                       # Number of times rename has blocked due to LQ full
system.cpu2.rename.SQFullEvents               1100267                       # Number of times rename has blocked due to SQ full
system.cpu2.rename.RenamedOperands           36626919                       # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups            154339316                       # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups        41664821                       # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups             4127                       # Number of floating rename lookups
system.cpu2.rename.CommittedMaps             28795876                       # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps                 7831027                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts            344066                       # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts        286541                       # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts                  5082070                       # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads             6089915                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores            4400227                       # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads           719431                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores         1142118                       # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded                  32029170                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded             669683                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued                 38616590                       # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued            44993                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined        5567256                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined     12099893                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved        238978                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples     87212188                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean        0.442789                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev       1.239118                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0           73763195     84.58%     84.58% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1            4095516      4.70%     89.28% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2            2328743      2.67%     91.95% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3            2051674      2.35%     94.30% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4            2976748      3.41%     97.71% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5             798764      0.92%     98.63% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6             739781      0.85%     99.48% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7             293068      0.34%     99.81% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8             164699      0.19%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total       87212188                       # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu                 122993      5.40%      5.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult                     1      0.00%      5.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv                      0      0.00%      5.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      5.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      5.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      5.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult                   0      0.00%      5.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      5.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      5.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      5.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      5.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      5.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      5.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      5.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      5.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult                    0      0.00%      5.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      5.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift                   0      0.00%      5.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      5.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      5.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      5.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      5.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      5.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      5.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      5.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      5.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      5.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      5.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      5.40% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead               1970586     86.46%     91.85% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite               185678      8.15%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass            12081      0.03%      0.03% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu             20207276     52.33%     52.36% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult               34218      0.09%     52.45% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     52.45% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     52.45% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     52.45% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     52.45% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     52.45% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     52.45% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     52.45% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     52.45% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     52.45% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     52.45% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     52.45% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     52.45% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     52.45% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     52.45% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     52.45% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     52.45% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     52.45% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     52.45% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     52.45% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     52.45% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     52.45% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     52.45% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     52.45% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc           404      0.00%     52.45% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     52.45% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     52.45% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     52.45% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead            14176555     36.71%     89.16% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite            4186056     10.84%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total              38616590                       # Type of FU issued
system.cpu2.iq.rate                          0.437789                       # Inst issue rate
system.cpu2.iq.fu_busy_cnt                    2279258                       # FU busy when requested
system.cpu2.iq.fu_busy_rate                  0.059023                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads         166760031                       # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes         38278238                       # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses     29588244                       # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads               9588                       # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes              5150                       # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses         4304                       # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses              40878658                       # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses                   5109                       # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads          176007                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads      1107424                       # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses         2018                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation        18033                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores       469449                       # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads      5207867                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked      3518142                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles                281926                       # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles               17856855                       # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles               716566                       # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts           32817404                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts            57776                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts              6089915                       # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts             4400227                       # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts            491578                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents                 63121                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents               616282                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents         18033                       # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect        121106                       # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect       106258                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts              227364                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts             38297957                       # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts             14051286                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts           280797                       # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
system.cpu2.iew.exec_nop                       118551                       # number of nop insts executed
system.cpu2.iew.exec_refs                    18186993                       # number of memory reference insts executed
system.cpu2.iew.exec_branches                 4220297                       # Number of branches executed
system.cpu2.iew.exec_stores                   4135707                       # Number of stores executed
system.cpu2.iew.exec_rate                    0.434177                       # Inst execution rate
system.cpu2.iew.wb_sent                      34852514                       # cumulative count of insts sent to commit
system.cpu2.iew.wb_count                     29592548                       # cumulative count of insts written-back
system.cpu2.iew.wb_producers                 17266310                       # num instructions producing a value
system.cpu2.iew.wb_consumers                 30698955                       # num instructions consuming a value
system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate                      0.335485                       # insts written-back per cycle
system.cpu2.iew.wb_fanout                    0.562440                       # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts        5479640                       # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls         430705                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts           190919                       # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples     86342246                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean     0.312843                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev     1.237203                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0     77364915     89.60%     89.60% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1      4177735      4.84%     94.44% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2      1290086      1.49%     95.94% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3       753837      0.87%     96.81% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4       490440      0.57%     97.38% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5       381562      0.44%     97.82% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6       374801      0.43%     98.25% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7       197147      0.23%     98.48% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8      1311723      1.52%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total     86342246                       # Number of insts commited each cycle
system.cpu2.commit.committedInsts            22875674                       # Number of instructions committed
system.cpu2.commit.committedOps              27011607                       # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu2.commit.refs                       8913269                       # Number of memory references committed
system.cpu2.commit.loads                      4982491                       # Number of loads committed
system.cpu2.commit.membars                     117220                       # Number of memory barriers committed
system.cpu2.commit.branches                   3644555                       # Number of branches committed
system.cpu2.commit.fp_insts                      4270                       # Number of committed floating point instructions.
system.cpu2.commit.int_insts                 23908542                       # Number of committed integer instructions.
system.cpu2.commit.function_calls              341319                       # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IntAlu        18065773     66.88%     66.88% # Class of committed instruction
system.cpu2.commit.op_class_0::IntMult          32161      0.12%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv               0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMult            0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMult             0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShift            0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMisc          404      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.00% # Class of committed instruction
system.cpu2.commit.op_class_0::MemRead        4982491     18.45%     85.45% # Class of committed instruction
system.cpu2.commit.op_class_0::MemWrite       3930778     14.55%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::total         27011607                       # Class of committed instruction
system.cpu2.commit.bw_lim_events              1311723                       # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads                   116854146                       # The number of ROB reads
system.cpu2.rob.rob_writes                   65855440                       # The number of ROB writes
system.cpu2.timesIdled                         179134                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles                         995958                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles                  3544369510                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts                   22801865                       # Number of Instructions Simulated
system.cpu2.committedOps                     26937798                       # Number of Ops (including micro ops) Simulated
system.cpu2.cpi                              3.868462                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        3.868462                       # CPI: Total CPI of All Threads
system.cpu2.ipc                              0.258501                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        0.258501                       # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads                45014030                       # number of integer regfile reads
system.cpu2.int_regfile_writes               19144459                       # number of integer regfile writes
system.cpu2.fp_regfile_reads                    47113                       # number of floating regfile reads
system.cpu2.fp_regfile_writes                   45464                       # number of floating regfile writes
system.cpu2.cc_regfile_reads                130800569                       # number of cc regfile reads
system.cpu2.cc_regfile_writes                12559359                       # number of cc regfile writes
system.cpu2.misc_regfile_reads              124603397                       # number of misc regfile reads
system.cpu2.misc_regfile_writes                350092                       # number of misc regfile writes
system.iocache.tags.replacements                    0                       # number of replacements
system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
system.iocache.tags.tag_accesses                    0                       # Number of tag accesses
system.iocache.tags.data_accesses                   0                       # Number of data accesses
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1536004079250                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1536004079250                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1536004079250                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1536004079250                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------