2006-09-01 23:59:36 +02:00
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---------- Begin Simulation Statistics ----------
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2012-10-30 14:35:32 +01:00
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sim_seconds 0.000016 # Number of seconds simulated
|
2012-11-02 17:50:06 +01:00
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|
sim_ticks 15802500 # Number of ticks simulated
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|
final_tick 15802500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
2011-06-21 00:57:14 +02:00
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|
sim_freq 1000000000000 # Frequency of simulated ticks
|
2012-11-02 17:50:06 +01:00
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host_inst_rate 38730 # Simulator instruction rate (inst/s)
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host_op_rate 38726 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 96032767 # Simulator tick rate (ticks/s)
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host_mem_usage 214332 # Number of bytes of host memory used
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host_seconds 0.16 # Real time elapsed on the host
|
2012-08-15 16:38:05 +02:00
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sim_insts 6372 # Number of instructions simulated
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sim_ops 6372 # Number of ops (including micro ops) simulated
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2012-10-25 19:14:42 +02:00
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system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory
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2012-10-30 14:35:32 +01:00
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system.physmem.bytes_read::cpu.data 11136 # Number of bytes read from this memory
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system.physmem.bytes_read::total 31168 # Number of bytes read from this memory
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2012-10-25 19:14:42 +02:00
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system.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory
|
2012-10-30 14:35:32 +01:00
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system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 487 # Number of read requests responded to by this memory
|
2012-11-02 17:50:06 +01:00
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system.physmem.bw_read::cpu.inst 1267647524 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 704698624 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 1972346148 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1267647524 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1267647524 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1267647524 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 704698624 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 1972346148 # Total bandwidth to/from this memory (bytes/s)
|
2012-10-30 14:35:32 +01:00
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|
system.physmem.readReqs 487 # Total number of read requests seen
|
2012-10-25 19:14:42 +02:00
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system.physmem.writeReqs 0 # Total number of write requests seen
|
2012-10-30 14:35:32 +01:00
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|
system.physmem.cpureqs 487 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 31168 # Total number of bytes read from memory
|
2012-10-25 19:14:42 +02:00
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|
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system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
2012-10-30 14:35:32 +01:00
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|
|
system.physmem.bytesConsumedRd 31168 # bytesRead derated as per pkt->getSize()
|
2012-10-25 19:14:42 +02:00
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system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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|
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|
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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|
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 51 # Track reads on a per bank basis
|
2012-10-30 14:35:32 +01:00
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|
|
system.physmem.perBankRdReqs::1 18 # Track reads on a per bank basis
|
2012-10-25 19:14:42 +02:00
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|
|
system.physmem.perBankRdReqs::2 4 # Track reads on a per bank basis
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|
system.physmem.perBankRdReqs::3 30 # Track reads on a per bank basis
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|
system.physmem.perBankRdReqs::4 31 # Track reads on a per bank basis
|
2012-11-02 17:50:06 +01:00
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|
|
system.physmem.perBankRdReqs::5 24 # Track reads on a per bank basis
|
2012-10-25 19:14:42 +02:00
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|
|
system.physmem.perBankRdReqs::6 4 # Track reads on a per bank basis
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|
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|
system.physmem.perBankRdReqs::7 67 # Track reads on a per bank basis
|
2012-10-30 14:35:32 +01:00
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|
|
system.physmem.perBankRdReqs::8 23 # Track reads on a per bank basis
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|
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|
system.physmem.perBankRdReqs::9 34 # Track reads on a per bank basis
|
2012-11-02 17:50:06 +01:00
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|
|
system.physmem.perBankRdReqs::10 73 # Track reads on a per bank basis
|
2012-10-25 19:14:42 +02:00
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|
|
system.physmem.perBankRdReqs::11 67 # Track reads on a per bank basis
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|
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|
|
system.physmem.perBankRdReqs::12 44 # Track reads on a per bank basis
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|
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|
|
system.physmem.perBankRdReqs::13 2 # Track reads on a per bank basis
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|
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|
|
system.physmem.perBankRdReqs::14 7 # Track reads on a per bank basis
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|
|
|
|
system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis
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|
|
|
|
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
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|
|
|
|
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
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|
|
|
|
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
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|
|
|
|
system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
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|
|
|
|
system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
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|
|
|
|
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
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|
|
|
|
system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
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|
|
|
|
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
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|
|
|
|
system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
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|
|
|
|
system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
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|
|
|
|
system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
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|
|
|
|
system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
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|
|
|
|
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
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|
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|
|
system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
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|
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|
|
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
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|
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|
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
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|
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|
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
|
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|
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
2012-11-02 17:50:06 +01:00
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|
|
system.physmem.totGap 15655000 # Total gap between requests
|
2012-10-25 19:14:42 +02:00
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|
|
system.physmem.readPktSize::0 0 # Categorize read packet sizes
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|
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|
|
system.physmem.readPktSize::1 0 # Categorize read packet sizes
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|
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|
|
system.physmem.readPktSize::2 0 # Categorize read packet sizes
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|
|
|
|
system.physmem.readPktSize::3 0 # Categorize read packet sizes
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|
|
|
|
system.physmem.readPktSize::4 0 # Categorize read packet sizes
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|
|
|
|
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
2012-10-30 14:35:32 +01:00
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|
|
system.physmem.readPktSize::6 487 # Categorize read packet sizes
|
2012-10-25 19:14:42 +02:00
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|
|
system.physmem.readPktSize::7 0 # Categorize read packet sizes
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|
|
|
|
system.physmem.readPktSize::8 0 # Categorize read packet sizes
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|
|
|
|
system.physmem.writePktSize::0 0 # categorize write packet sizes
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|
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system.physmem.writePktSize::1 0 # categorize write packet sizes
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|
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system.physmem.writePktSize::2 0 # categorize write packet sizes
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|
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|
system.physmem.writePktSize::3 0 # categorize write packet sizes
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|
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system.physmem.writePktSize::4 0 # categorize write packet sizes
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system.physmem.writePktSize::5 0 # categorize write packet sizes
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system.physmem.writePktSize::6 0 # categorize write packet sizes
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system.physmem.writePktSize::7 0 # categorize write packet sizes
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system.physmem.writePktSize::8 0 # categorize write packet sizes
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system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
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|
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system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
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|
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system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
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|
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system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
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|
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system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
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|
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system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
2012-10-30 14:35:32 +01:00
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|
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system.physmem.rdQLenPdf::0 258 # What read queue length does an incoming req see
|
2012-11-02 17:50:06 +01:00
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system.physmem.rdQLenPdf::1 151 # What read queue length does an incoming req see
|
2012-10-30 14:35:32 +01:00
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system.physmem.rdQLenPdf::2 55 # What read queue length does an incoming req see
|
2012-11-02 17:50:06 +01:00
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system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see
|
2012-10-25 19:14:42 +02:00
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|
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system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
|
2012-10-30 14:35:32 +01:00
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|
|
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
2012-10-25 19:14:42 +02:00
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|
|
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
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|
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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|
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
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|
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
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|
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
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|
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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|
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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|
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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|
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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|
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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|
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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|
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
|
|
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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|
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|
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
|
|
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|
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
|
|
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|
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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|
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|
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
|
|
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|
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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|
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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|
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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|
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
|
|
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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|
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|
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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|
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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|
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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|
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|
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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|
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
|
|
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|
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
|
|
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|
|
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
|
|
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|
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
|
|
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|
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
2012-11-02 17:50:06 +01:00
|
|
|
system.physmem.totQLat 3073487 # Total cycles spent in queuing delays
|
|
|
|
|
system.physmem.totMemAccLat 12819487 # Sum of mem lat for all requests
|
2012-10-30 14:35:32 +01:00
|
|
|
system.physmem.totBusLat 1948000 # Total cycles spent in databus access
|
|
|
|
|
system.physmem.totBankLat 7798000 # Total cycles spent in bank access
|
2012-11-02 17:50:06 +01:00
|
|
|
system.physmem.avgQLat 6311.06 # Average queueing delay per request
|
2012-10-30 14:35:32 +01:00
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|
|
system.physmem.avgBankLat 16012.32 # Average bank access latency per request
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.avgBusLat 4000.00 # Average bus latency per request
|
2012-11-02 17:50:06 +01:00
|
|
|
system.physmem.avgMemAccLat 26323.38 # Average memory access latency
|
|
|
|
|
system.physmem.avgRdBW 1972.35 # Average achieved read bandwidth in MB/s
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
2012-11-02 17:50:06 +01:00
|
|
|
system.physmem.avgConsumedRdBW 1972.35 # Average consumed read bandwidth in MB/s
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
|
|
|
|
|
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
|
2012-11-02 17:50:06 +01:00
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|
|
system.physmem.busUtil 12.33 # Data bus utilization in percentage
|
|
|
|
|
system.physmem.avgRdQLen 0.81 # Average read queue length over time
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.avgWrQLen 0.00 # Average write queue length over time
|
2012-11-02 17:50:06 +01:00
|
|
|
system.physmem.readRowHits 416 # Number of row buffer hits during reads
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
2012-11-02 17:50:06 +01:00
|
|
|
system.physmem.readRowHitRate 85.42 # Row buffer hit rate for reads
|
2012-10-25 19:14:42 +02:00
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|
|
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
2012-11-02 17:50:06 +01:00
|
|
|
system.physmem.avgGap 32145.79 # Average gap between requests
|
2009-04-09 07:21:30 +02:00
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|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
|
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
|
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dtb.read_hits 2068 # DTB read hits
|
|
|
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|
system.cpu.dtb.read_misses 50 # DTB read misses
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dtb.read_accesses 2118 # DTB read accesses
|
|
|
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|
system.cpu.dtb.write_hits 1071 # DTB write hits
|
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|
|
system.cpu.dtb.write_misses 29 # DTB write misses
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dtb.write_accesses 1100 # DTB write accesses
|
|
|
|
|
system.cpu.dtb.data_hits 3139 # DTB hits
|
|
|
|
|
system.cpu.dtb.data_misses 79 # DTB misses
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dtb.data_accesses 3218 # DTB accesses
|
|
|
|
|
system.cpu.itb.fetch_hits 2370 # ITB hits
|
|
|
|
|
system.cpu.itb.fetch_misses 39 # ITB misses
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.itb.fetch_accesses 2409 # ITB accesses
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
|
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
|
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
|
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
|
|
|
system.cpu.workload.num_syscalls 17 # Number of system calls
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.numCycles 31606 # number of cpu cycles simulated
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.BPredUnit.lookups 2927 # Number of BP lookups
|
|
|
|
|
system.cpu.BPredUnit.condPredicted 1718 # Number of conditional branches predicted
|
|
|
|
|
system.cpu.BPredUnit.condIncorrect 517 # Number of conditional branches incorrect
|
|
|
|
|
system.cpu.BPredUnit.BTBLookups 2238 # Number of BTB lookups
|
|
|
|
|
system.cpu.BPredUnit.BTBHits 757 # Number of BTB hits
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.BPredUnit.usedRAS 420 # Number of times the RAS was used to get a target.
|
|
|
|
|
system.cpu.BPredUnit.RASInCorrect 77 # Number of incorrect RAS predictions.
|
|
|
|
|
system.cpu.fetch.icacheStallCycles 8266 # Number of cycles fetch is stalled on an Icache miss
|
|
|
|
|
system.cpu.fetch.Insts 16744 # Number of instructions fetch has processed
|
|
|
|
|
system.cpu.fetch.Branches 2927 # Number of branches that fetch encountered
|
|
|
|
|
system.cpu.fetch.predictedBranches 1177 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu.fetch.Cycles 2985 # Number of cycles fetch has run and was not squashing or blocked
|
|
|
|
|
system.cpu.fetch.SquashCycles 1897 # Number of cycles fetch has spent squashing
|
|
|
|
|
system.cpu.fetch.BlockedCycles 1074 # Number of cycles fetch has spent blocked
|
|
|
|
|
system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
|
|
|
system.cpu.fetch.PendingTrapStallCycles 762 # Number of stall cycles due to pending traps
|
|
|
|
|
system.cpu.fetch.CacheLines 2370 # Number of cache lines fetched
|
|
|
|
|
system.cpu.fetch.IcacheSquashes 362 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu.fetch.rateDist::samples 14416 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::mean 1.161487 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::stdev 2.555904 # Number of instructions fetched each cycle (Total)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.fetch.rateDist::0 11431 79.29% 79.29% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::1 317 2.20% 81.49% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::2 233 1.62% 83.11% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::3 212 1.47% 84.58% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::4 264 1.83% 86.41% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::5 229 1.59% 88.00% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::6 265 1.84% 89.84% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::7 186 1.29% 91.13% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::8 1279 8.87% 100.00% # Number of instructions fetched each cycle (Total)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.fetch.rateDist::total 14416 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.branchRate 0.092609 # Number of branch fetches per cycle
|
|
|
|
|
system.cpu.fetch.rate 0.529773 # Number of inst fetches per cycle
|
|
|
|
|
system.cpu.decode.IdleCycles 9179 # Number of cycles decode is idle
|
|
|
|
|
system.cpu.decode.BlockedCycles 1146 # Number of cycles decode is blocked
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.decode.RunCycles 2779 # Number of cycles decode is running
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.decode.UnblockCycles 90 # Number of cycles decode is unblocking
|
|
|
|
|
system.cpu.decode.SquashCycles 1222 # Number of cycles decode is squashing
|
|
|
|
|
system.cpu.decode.BranchResolved 249 # Number of times decode resolved a branch
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.decode.BranchMispred 87 # Number of times decode detected a branch misprediction
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.decode.DecodedInsts 15526 # Number of instructions handled by decode
|
|
|
|
|
system.cpu.decode.SquashedInsts 231 # Number of squashed instructions handled by decode
|
|
|
|
|
system.cpu.rename.SquashCycles 1222 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.IdleCycles 9389 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.BlockCycles 326 # Number of cycles rename is blocking
|
|
|
|
|
system.cpu.rename.serializeStallCycles 477 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.RunCycles 2653 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.UnblockCycles 349 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RenamedInsts 14793 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu.rename.LSQFullEvents 317 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu.rename.RenamedOperands 11113 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RenameLookups 18446 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.int_rename_lookups 18429 # Number of integer rename lookups
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups
|
2012-08-15 16:38:05 +02:00
|
|
|
system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.rename.UndoneMaps 6543 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.serializingInsts 32 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.tempSerializingInsts 26 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu.rename.skidInsts 811 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.memDep0.insertedLoads 2756 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.insertedStores 1363 # Number of stores inserted to the mem dependence unit.
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iq.iqInstsAdded 13069 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ
|
|
|
|
|
system.cpu.iq.iqInstsIssued 10819 # Number of instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedInstsExamined 6341 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 3614 # Number of squashed operands that are examined and possibly removed from graph
|
|
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed
|
|
|
|
|
system.cpu.iq.issued_per_cycle::samples 14416 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::mean 0.750486 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::stdev 1.391653 # Number of insts issued each cycle
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iq.issued_per_cycle::0 9926 68.85% 68.85% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::1 1619 11.23% 80.08% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::2 1135 7.87% 87.96% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::3 768 5.33% 93.29% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::4 481 3.34% 96.62% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::5 285 1.98% 98.60% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::6 151 1.05% 99.65% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::7 37 0.26% 99.90% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iq.issued_per_cycle::total 14416 # Number of insts issued each cycle
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iq.fu_full::IntAlu 14 11.97% 11.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 11.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 11.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 11.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 11.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 11.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.97% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemRead 64 54.70% 66.67% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemWrite 39 33.33% 100.00% # attempts to use FU when none available
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iq.FU_type_0::IntAlu 7317 67.63% 67.65% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.66% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.66% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.68% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemRead 2355 21.77% 89.44% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 1142 10.56% 100.00% # Type of FU issued
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iq.FU_type_0::total 10819 # Type of FU issued
|
|
|
|
|
system.cpu.iq.rate 0.342308 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 117 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.010814 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 36206 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 19446 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 9723 # Number of integer instruction queue wakeup accesses
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iq.int_alu_accesses 10923 # Number of integer alu accesses
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 67 # Number of loads that had data forwarded from stores
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 1573 # Number of loads squashed
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 18 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 498 # Number of stores squashed
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 90 # Number of times an access to memory failed due to the cache being blocked
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iew.iewSquashCycles 1222 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 52 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 13186 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 157 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 2756 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 1363 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iew.memOrderViolationEvents 18 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 129 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 393 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 522 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 10167 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 2129 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 652 # Number of squashed instructions skipped in execute
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iew.exec_nop 87 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_refs 3231 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 1614 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 1102 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 0.321679 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 9882 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 9733 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 5145 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 6933 # num instructions consuming a value
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iew.wb_rate 0.307948 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.742103 # average fanout of values written-back
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.commit.commitSquashedInsts 6795 # The number of squashed insts skipped by commit
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.commit.branchMispredicts 435 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 13194 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 0.484235 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 1.303292 # Number of insts commited each cycle
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.commit.committed_per_cycle::0 10420 78.98% 78.98% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 1475 11.18% 90.15% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 517 3.92% 94.07% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 247 1.87% 95.95% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 154 1.17% 97.11% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 92 0.70% 97.81% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 106 0.80% 98.61% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 37 0.28% 98.89% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 146 1.11% 100.00% # Number of insts commited each cycle
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.commit.committed_per_cycle::total 13194 # Number of insts commited each cycle
|
2012-08-15 16:38:05 +02:00
|
|
|
system.cpu.commit.committedInsts 6389 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
2012-08-15 16:38:05 +02:00
|
|
|
system.cpu.commit.refs 2048 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 1183 # Number of loads committed
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
2012-08-15 16:38:05 +02:00
|
|
|
system.cpu.commit.branches 1050 # Number of branches committed
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.commit.fp_insts 10 # Number of committed floating point instructions.
|
2012-08-15 16:38:05 +02:00
|
|
|
system.cpu.commit.int_insts 6307 # Number of committed integer instructions.
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.commit.function_calls 127 # Number of function calls committed.
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.commit.bw_lim_events 146 # number cycles where commit BW limit reached
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.rob.rob_reads 25881 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 27599 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 17190 # Total number of cycles that the CPU has spent unscheduled due to idling
|
2012-08-15 16:38:05 +02:00
|
|
|
system.cpu.committedInsts 6372 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated
|
|
|
|
|
system.cpu.committedInsts_total 6372 # Number of Instructions Simulated
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.cpi 4.960138 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 4.960138 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 0.201607 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 0.201607 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 12907 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 7365 # number of integer regfile writes
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.fp_regfile_reads 8 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
|
|
|
|
|
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
|
|
|
|
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
|
|
|
|
system.cpu.icache.replacements 0 # number of replacements
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.icache.tagsinuse 160.479269 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 1894 # Total number of references to valid blocks.
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks.
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.icache.avg_refs 6.031847 # Average number of references to valid blocks.
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.icache.occ_blocks::cpu.inst 160.479269 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.icache.occ_percent::cpu.inst 0.078359 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.occ_percent::total 0.078359 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 1894 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_hits::total 1894 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits::cpu.inst 1894 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_hits::total 1894 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits::cpu.inst 1894 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_hits::total 1894 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 476 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_misses::total 476 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses::cpu.inst 476 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_misses::total 476 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses::cpu.inst 476 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_misses::total 476 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 21386500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::total 21386500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 21386500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::total 21386500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 21386500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::total 21386500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 2370 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::total 2370 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses::cpu.inst 2370 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_accesses::total 2370 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::cpu.inst 2370 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::total 2370 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.200844 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.200844 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.200844 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::total 0.200844 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.200844 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::total 0.200844 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44929.621849 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 44929.621849 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 44929.621849 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::total 44929.621849 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 44929.621849 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::total 44929.621849 # average overall miss latency
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 162 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits::total 162 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 162 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits::total 162 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 162 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits::total 162 # number of overall MSHR hits
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::total 314 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::total 314 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::total 314 # number of overall MSHR misses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15404000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 15404000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15404000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::total 15404000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15404000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::total 15404000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.132489 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.132489 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.132489 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.132489 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.132489 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.132489 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49057.324841 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49057.324841 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49057.324841 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 49057.324841 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49057.324841 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 49057.324841 # average overall mshr miss latency
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.tagsinuse 220.902491 # Cycle average of tags in use
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.sampled_refs 414 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 0.002415 # Average number of references to valid blocks.
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 160.626019 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_blocks::cpu.data 60.276472 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.004902 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.001839 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::total 0.006741 # Average percentage of cache occupancy
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::total 1 # number of overall hits
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 313 # number of ReadReq misses
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 101 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::total 414 # number of ReadReq misses
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu.l2cache.demand_misses::cpu.inst 313 # number of demand (read+write) misses
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.demand_misses::cpu.data 174 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::total 487 # number of demand (read+write) misses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu.l2cache.overall_misses::cpu.inst 313 # number of overall misses
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::total 487 # number of overall misses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15078000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6210500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 21288500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3737500 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 3737500 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 15078000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 9948000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::total 25026000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 15078000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 9948000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::total 25026000 # number of overall miss cycles
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 314 # number of ReadReq accesses(hits+misses)
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses)
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 314 # number of demand (read+write) accesses
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.demand_accesses::cpu.data 174 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::total 488 # number of demand (read+write) accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 314 # number of overall (read+write) accesses
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.overall_accesses::cpu.data 174 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::total 488 # number of overall (read+write) accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996815 # miss rate for ReadReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.997590 # miss rate for ReadReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996815 # miss rate for demand accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.demand_miss_rate::total 0.997951 # miss rate for demand accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996815 # miss rate for overall accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.overall_miss_rate::total 0.997951 # miss rate for overall accesses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48172.523962 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 61490.099010 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 51421.497585 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51198.630137 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51198.630137 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48172.523962 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 57172.413793 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 51388.090349 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48172.523962 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 57172.413793 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 51388.090349 # average overall miss latency
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 414 # number of ReadReq MSHR misses
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::total 487 # number of demand (read+write) MSHR misses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::total 487 # number of overall MSHR misses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11136994 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4966088 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16103082 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2842064 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2842064 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11136994 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7808152 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 18945146 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11136994 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7808152 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 18945146 # number of overall MSHR miss cycles
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for ReadReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997590 # mshr miss rate for ReadReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for demand accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.997951 # mshr miss rate for demand accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for overall accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997951 # mshr miss rate for overall accesses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35581.450479 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 49169.188119 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38896.333333 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38932.383562 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38932.383562 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35581.450479 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44874.436782 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38901.737166 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35581.450479 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44874.436782 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38901.737166 # average overall mshr miss latency
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dcache.replacements 0 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 107.834334 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 2264 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 13.011494 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.occ_blocks::cpu.data 107.834334 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.dcache.occ_percent::cpu.data 0.026327 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.occ_percent::total 0.026327 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 1758 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::total 1758 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits::cpu.data 2264 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_hits::total 2264 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits::cpu.data 2264 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_hits::total 2264 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 169 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::total 169 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses::cpu.data 528 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_misses::total 528 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses::cpu.data 528 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_misses::total 528 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 9065500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::total 9065500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 15837484 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::total 15837484 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 24902984 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::total 24902984 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 24902984 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::total 24902984 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 1927 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::total 1927 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses::cpu.data 2792 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_accesses::total 2792 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::cpu.data 2792 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::total 2792 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087701 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.087701 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.189112 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::total 0.189112 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.189112 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::total 0.189112 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53642.011834 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 53642.011834 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44115.554318 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 44115.554318 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 47164.742424 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::total 47164.742424 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 47164.742424 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::total 47164.742424 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 801 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_mshrs 26 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.807692 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 68 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 286 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 286 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 354 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::total 354 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 354 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::total 354 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6319000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6319000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3813500 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3813500 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10132500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 10132500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10132500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 10132500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052413 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052413 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062321 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.062321 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062321 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.062321 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62564.356436 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62564.356436 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52239.726027 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52239.726027 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58232.758621 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 58232.758621 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58232.758621 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 58232.758621 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2006-09-01 23:59:36 +02:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
