2013-01-07 19:05:52 +01:00
---------- Begin Simulation Statistics ----------
2015-12-05 01:11:25 +01:00
sim_seconds 2.909671 # Number of seconds simulated
sim_ticks 2909670971500 # Number of ticks simulated
final_tick 2909670971500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2013-01-07 19:05:52 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2015-12-12 23:27:38 +01:00
host_inst_rate 363443 # Simulator instruction rate (inst/s)
host_op_rate 438198 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 9403770867 # Simulator tick rate (ticks/s)
host_mem_usage 560672 # Number of bytes of host memory used
host_seconds 309.42 # Real time elapsed on the host
2015-12-05 01:11:25 +01:00
sim_insts 112454909 # Number of instructions simulated
sim_ops 135585028 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2015-07-03 16:15:03 +02:00
system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory
2015-12-05 01:11:25 +01:00
system.physmem.bytes_read::cpu0.inst 523360 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 4648320 # Number of bytes read from this memory
2015-09-25 13:27:03 +02:00
system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
2015-12-05 01:11:25 +01:00
system.physmem.bytes_read::cpu1.inst 663236 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 4253220 # Number of bytes read from this memory
2014-11-12 15:05:25 +01:00
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
2015-12-05 01:11:25 +01:00
system.physmem.bytes_read::total 10089608 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 523360 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 663236 # Number of instructions bytes read from this memory
2015-11-06 09:26:50 +01:00
system.physmem.bytes_inst_read::total 1186596 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7511936 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 8852 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 8672 # Number of bytes written to this memory
system.physmem.bytes_written::total 7529460 # Number of bytes written to this memory
2015-07-03 16:15:03 +02:00
system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory
2015-12-05 01:11:25 +01:00
system.physmem.num_reads::cpu0.inst 13465 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 73133 # Number of read requests responded to by this memory
2015-09-25 13:27:03 +02:00
system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
2015-12-05 01:11:25 +01:00
system.physmem.num_reads::cpu1.inst 13529 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 66473 # Number of read requests responded to by this memory
2014-11-12 15:05:25 +01:00
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
2015-12-05 01:11:25 +01:00
system.physmem.num_reads::total 166623 # Number of read requests responded to by this memory
2015-11-06 09:26:50 +01:00
system.physmem.num_writes::writebacks 117374 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 2213 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 2168 # Number of write requests responded to by this memory
system.physmem.num_writes::total 121755 # Number of write requests responded to by this memory
2015-07-03 16:15:03 +02:00
system.physmem.bw_read::cpu0.dtb.walker 88 # Total read bandwidth from this memory (bytes/s)
2015-12-05 01:11:25 +01:00
system.physmem.bw_read::cpu0.inst 179869 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 1597541 # Total read bandwidth from this memory (bytes/s)
2015-09-25 13:27:03 +02:00
system.physmem.bw_read::cpu1.dtb.walker 66 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s)
2015-12-05 01:11:25 +01:00
system.physmem.bw_read::cpu1.inst 227942 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 1461753 # Total read bandwidth from this memory (bytes/s)
2015-09-25 13:27:03 +02:00
system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s)
2015-12-05 01:11:25 +01:00
system.physmem.bw_read::total 3467611 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 179869 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 227942 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 407811 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2581713 # Write bandwidth from this memory (bytes/s)
2015-11-06 09:26:50 +01:00
system.physmem.bw_write::cpu0.data 3042 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 2980 # Write bandwidth from this memory (bytes/s)
2015-12-05 01:11:25 +01:00
system.physmem.bw_write::total 2587736 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2581713 # Total bandwidth to/from this memory (bytes/s)
2015-07-03 16:15:03 +02:00
system.physmem.bw_total::cpu0.dtb.walker 88 # Total bandwidth to/from this memory (bytes/s)
2015-12-05 01:11:25 +01:00
system.physmem.bw_total::cpu0.inst 179869 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 1600584 # Total bandwidth to/from this memory (bytes/s)
2015-09-25 13:27:03 +02:00
system.physmem.bw_total::cpu1.dtb.walker 66 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s)
2015-12-05 01:11:25 +01:00
system.physmem.bw_total::cpu1.inst 227942 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 1464733 # Total bandwidth to/from this memory (bytes/s)
2015-09-25 13:27:03 +02:00
system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s)
2015-12-05 01:11:25 +01:00
system.physmem.bw_total::total 6055347 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 166623 # Number of read requests accepted
2015-11-06 09:26:50 +01:00
system.physmem.writeReqs 121755 # Number of write requests accepted
2015-12-05 01:11:25 +01:00
system.physmem.readBursts 166623 # Number of DRAM read bursts, including those serviced by the write queue
2015-11-06 09:26:50 +01:00
system.physmem.writeBursts 121755 # Number of DRAM write bursts, including those merged in the write queue
2015-12-05 01:11:25 +01:00
system.physmem.bytesReadDRAM 10657728 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 6144 # Total number of bytes read from write queue
2015-11-06 09:26:50 +01:00
system.physmem.bytesWritten 7541440 # Total number of bytes written to DRAM
2015-12-05 01:11:25 +01:00
system.physmem.bytesReadSys 10089608 # Total read bytes from the system interface side
2015-11-06 09:26:50 +01:00
system.physmem.bytesWrittenSys 7529460 # Total written bytes from the system interface side
2015-12-05 01:11:25 +01:00
system.physmem.servicedByWrQ 96 # Number of DRAM read bursts serviced by the write queue
2015-07-03 16:15:03 +02:00
system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one
2015-12-05 01:11:25 +01:00
system.physmem.neitherReadNorWriteReqs 47111 # Number of requests that are neither read nor write
2015-11-06 09:26:50 +01:00
system.physmem.perBankRdBursts::0 10080 # Per bank write bursts
system.physmem.perBankRdBursts::1 9979 # Per bank write bursts
system.physmem.perBankRdBursts::2 10697 # Per bank write bursts
2015-12-05 01:11:25 +01:00
system.physmem.perBankRdBursts::3 10654 # Per bank write bursts
2015-11-06 09:26:50 +01:00
system.physmem.perBankRdBursts::4 18793 # Per bank write bursts
2015-12-05 01:11:25 +01:00
system.physmem.perBankRdBursts::5 9662 # Per bank write bursts
system.physmem.perBankRdBursts::6 9670 # Per bank write bursts
system.physmem.perBankRdBursts::7 10489 # Per bank write bursts
2015-11-06 09:26:50 +01:00
system.physmem.perBankRdBursts::8 9276 # Per bank write bursts
system.physmem.perBankRdBursts::9 9982 # Per bank write bursts
system.physmem.perBankRdBursts::10 9231 # Per bank write bursts
2015-12-05 01:11:25 +01:00
system.physmem.perBankRdBursts::11 8676 # Per bank write bursts
2015-11-06 09:26:50 +01:00
system.physmem.perBankRdBursts::12 9823 # Per bank write bursts
system.physmem.perBankRdBursts::13 10380 # Per bank write bursts
2015-12-05 01:11:25 +01:00
system.physmem.perBankRdBursts::14 9722 # Per bank write bursts
2015-11-06 09:26:50 +01:00
system.physmem.perBankRdBursts::15 9413 # Per bank write bursts
system.physmem.perBankWrBursts::0 7393 # Per bank write bursts
system.physmem.perBankWrBursts::1 7263 # Per bank write bursts
system.physmem.perBankWrBursts::2 8284 # Per bank write bursts
2015-12-05 01:11:25 +01:00
system.physmem.perBankWrBursts::3 8167 # Per bank write bursts
2015-11-06 09:26:50 +01:00
system.physmem.perBankWrBursts::4 7485 # Per bank write bursts
system.physmem.perBankWrBursts::5 7265 # Per bank write bursts
system.physmem.perBankWrBursts::6 7108 # Per bank write bursts
system.physmem.perBankWrBursts::7 7667 # Per bank write bursts
system.physmem.perBankWrBursts::8 7080 # Per bank write bursts
system.physmem.perBankWrBursts::9 7523 # Per bank write bursts
system.physmem.perBankWrBursts::10 6694 # Per bank write bursts
2015-12-05 01:11:25 +01:00
system.physmem.perBankWrBursts::11 6468 # Per bank write bursts
2015-11-06 09:26:50 +01:00
system.physmem.perBankWrBursts::12 7527 # Per bank write bursts
system.physmem.perBankWrBursts::13 7859 # Per bank write bursts
2015-12-05 01:11:25 +01:00
system.physmem.perBankWrBursts::14 7264 # Per bank write bursts
2015-11-06 09:26:50 +01:00
system.physmem.perBankWrBursts::15 6788 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
2015-12-05 01:11:25 +01:00
system.physmem.numWrRetry 4 # Number of times write queue was full causing retry
system.physmem.totGap 2909670614500 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
2014-10-30 05:18:29 +01:00
system.physmem.readPktSize::2 9558 # Read request sizes (log2)
system.physmem.readPktSize::3 14 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2015-12-05 01:11:25 +01:00
system.physmem.readPktSize::6 157051 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
2014-10-30 05:18:29 +01:00
system.physmem.writePktSize::2 4381 # Write request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
2015-11-06 09:26:50 +01:00
system.physmem.writePktSize::6 117374 # Write request sizes (log2)
2015-12-05 01:11:25 +01:00
system.physmem.rdQLenPdf::0 165647 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 611 # What read queue length does an incoming req see
2015-09-25 13:27:03 +02:00
system.physmem.rdQLenPdf::2 257 # What read queue length does an incoming req see
2014-10-30 05:18:29 +01:00
system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
2013-01-07 19:05:52 +01:00
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
2015-12-05 01:11:25 +01:00
system.physmem.wrQLenPdf::0 202 # What write queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.wrQLenPdf::1 199 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 188 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 185 # What write queue length does an incoming req see
2015-12-05 01:11:25 +01:00
system.physmem.wrQLenPdf::4 184 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 181 # What write queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.wrQLenPdf::6 180 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 176 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 174 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 172 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 170 # What write queue length does an incoming req see
2015-12-05 01:11:25 +01:00
system.physmem.wrQLenPdf::11 169 # What write queue length does an incoming req see
2015-09-25 13:27:03 +02:00
system.physmem.wrQLenPdf::12 166 # What write queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.wrQLenPdf::13 165 # What write queue length does an incoming req see
2015-09-25 13:27:03 +02:00
system.physmem.wrQLenPdf::14 163 # What write queue length does an incoming req see
2015-12-05 01:11:25 +01:00
system.physmem.wrQLenPdf::15 2202 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 2477 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5854 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5793 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 6266 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6267 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 7166 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 6776 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 7632 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 7829 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 7695 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 9135 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 7022 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 6466 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 6502 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 6063 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 5806 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 5737 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 248 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 190 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 150 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 165 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 144 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 113 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 72 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 99 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 60 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 91 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 81 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 68 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 102 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 109 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 89 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 143 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 83 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 68 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 60 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 63 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 52 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 33 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 20 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 20 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 10 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 18 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 15 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 10 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 12 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 58603 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 310.549016 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 183.176876 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 330.004841 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 21372 36.47% 36.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 14638 24.98% 61.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 6011 10.26% 71.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3214 5.48% 77.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2514 4.29% 81.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1548 2.64% 84.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1052 1.80% 85.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1122 1.91% 87.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 7132 12.17% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 58603 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 5730 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 29.058290 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 544.635756 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 5727 99.95% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095 2 0.03% 99.98% # Reads before turning the bus around for writes
2014-10-30 05:18:29 +01:00
system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes
2015-12-05 01:11:25 +01:00
system.physmem.rdPerTurnAround::total 5730 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 5730 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 20.564572 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.725438 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 12.838937 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3 17 0.30% 0.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7 9 0.16% 0.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11 8 0.14% 0.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15 11 0.19% 0.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 4763 83.12% 83.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 132 2.30% 86.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 73 1.27% 87.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 203 3.54% 91.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 27 0.47% 91.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 153 2.67% 94.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 54 0.94% 95.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 2 0.03% 95.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 13 0.23% 95.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 23 0.40% 95.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 5 0.09% 95.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 7 0.12% 95.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 171 2.98% 98.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 5 0.09% 99.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 6 0.10% 99.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 24 0.42% 99.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 3 0.05% 99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 1 0.02% 99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 1 0.02% 99.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 11 0.19% 99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 1 0.02% 99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 1 0.02% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155 3 0.05% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 2 0.03% 99.98% # Writes before turning the bus around for reads
2015-11-06 09:26:50 +01:00
system.physmem.wrPerTurnAround::164-167 1 0.02% 100.00% # Writes before turning the bus around for reads
2015-12-05 01:11:25 +01:00
system.physmem.wrPerTurnAround::total 5730 # Writes before turning the bus around for reads
system.physmem.totQLat 1612014000 # Total ticks spent queuing
system.physmem.totMemAccLat 4734395250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 832635000 # Total ticks spent in databus transfers
system.physmem.avgQLat 9680.20 # Average queueing delay per DRAM burst
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2015-12-05 01:11:25 +01:00
system.physmem.avgMemAccLat 28430.20 # Average memory access latency per DRAM burst
2015-09-25 13:27:03 +02:00
system.physmem.avgRdBW 3.66 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.59 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 3.47 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 2.59 # Average system write bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2015-03-02 11:04:20 +01:00
system.physmem.busUtil 0.05 # Data bus utilization in percentage
2014-10-30 05:18:29 +01:00
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
2015-03-02 11:04:20 +01:00
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
2014-10-30 05:18:29 +01:00
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
2015-12-05 01:11:25 +01:00
system.physmem.avgWrQLen 12.26 # Average write queue length when enqueuing
system.physmem.readRowHits 136241 # Number of row buffer hits during reads
system.physmem.writeRowHits 89517 # Number of row buffer hits during writes
system.physmem.readRowHitRate 81.81 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 75.95 # Row buffer hit rate for writes
system.physmem.avgGap 10089780.13 # Average gap between requests
system.physmem.pageHitRate 79.38 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 230746320 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 125903250 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 702187200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 392895360 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 190045312080 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 90312406830 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1666579011000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 1948388462040 # Total energy per rank (pJ)
system.physmem_0.averagePower 669.625842 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 2772320056250 # Time in different power states
system.physmem_0.memoryStateTime::REF 97160180000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-12-05 01:11:25 +01:00
system.physmem_0.memoryStateTime::ACT 40187145000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-12-05 01:11:25 +01:00
system.physmem_1.actEnergy 212292360 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 115834125 # Energy for precharge commands per rank (pJ)
2015-11-06 09:26:50 +01:00
system.physmem_1.readEnergy 596715600 # Energy for read commands per rank (pJ)
2015-12-05 01:11:25 +01:00
system.physmem_1.writeEnergy 370675440 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 190045312080 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 88507788255 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1668162009750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1948010627610 # Total energy per rank (pJ)
system.physmem_1.averagePower 669.495988 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 2774979616000 # Time in different power states
system.physmem_1.memoryStateTime::REF 97160180000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-12-05 01:11:25 +01:00
system.physmem_1.memoryStateTime::ACT 37531027500 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2014-11-12 15:05:25 +01:00
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2014-12-23 15:31:20 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2015-12-05 01:11:25 +01:00
system.cpu0.dtb.walker.walks 6370 # Table walker walks requested
system.cpu0.dtb.walker.walksShort 6370 # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1827 # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 4542 # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore 1 # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples 6369 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0 6369 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 6369 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples 5319 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 13473.303252 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 11679.114902 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 7408.984019 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-16383 3974 74.71% 74.71% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1341 25.21% 99.92% # Table walker service (enqueue to completion) latency
2015-11-06 09:26:50 +01:00
system.cpu0.dtb.walker.walkCompletionTime::131072-147455 4 0.08% 100.00% # Table walker service (enqueue to completion) latency
2015-12-05 01:11:25 +01:00
system.cpu0.dtb.walker.walkCompletionTime::total 5319 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 2989035968 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean 0.330748 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev 0.470482 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 2000419000 66.93% 66.93% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1 988616968 33.07% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 2989035968 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 3517 66.13% 66.13% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M 1801 33.87% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 5318 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 6370 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2015-12-05 01:11:25 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 6370 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5318 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2015-12-05 01:11:25 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5318 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 11688 # Table walker requests started/completed, data/inst
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
2015-12-05 01:11:25 +01:00
system.cpu0.dtb.read_hits 12041748 # DTB read hits
system.cpu0.dtb.read_misses 5569 # DTB read misses
system.cpu0.dtb.write_hits 9609883 # DTB write hits
system.cpu0.dtb.write_misses 801 # DTB write misses
system.cpu0.dtb.flush_tlb 2941 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 437 # Number of times TLB was flushed by MVA
2014-10-30 05:18:29 +01:00
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2015-12-05 01:11:25 +01:00
system.cpu0.dtb.flush_entries 3992 # Number of entries that have been flushed from TLB
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
2015-12-05 01:11:25 +01:00
system.cpu0.dtb.prefetch_faults 859 # Number of TLB faults due to prefetch
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2015-12-05 01:11:25 +01:00
system.cpu0.dtb.perms_faults 214 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 12047317 # DTB read accesses
system.cpu0.dtb.write_accesses 9610684 # DTB write accesses
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
2015-12-05 01:11:25 +01:00
system.cpu0.dtb.hits 21651631 # DTB hits
system.cpu0.dtb.misses 6370 # DTB misses
system.cpu0.dtb.accesses 21658001 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2015-12-05 01:11:25 +01:00
system.cpu0.itb.walker.walks 3218 # Table walker walks requested
system.cpu0.itb.walker.walksShort 3218 # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1 687 # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2531 # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples 3218 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0 3218 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 3218 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples 2361 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 13277.424820 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 11544.822386 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 6544.721859 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::4096-6143 607 25.71% 25.71% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::10240-12287 660 27.95% 53.66% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::12288-14335 188 7.96% 61.63% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::14336-16383 387 16.39% 78.02% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-18431 3 0.13% 78.14% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::22528-24575 510 21.60% 99.75% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::24576-26623 6 0.25% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total 2361 # Table walker service (enqueue to completion) latency
2015-09-25 13:27:03 +02:00
system.cpu0.itb.walker.walksPending::samples 2000380500 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 2000380500 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 2000380500 # Table walker pending requests distribution
2015-12-05 01:11:25 +01:00
system.cpu0.itb.walker.walkPageSizes::4K 1674 70.90% 70.90% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M 687 29.10% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 2361 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2015-12-05 01:11:25 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3218 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3218 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2015-12-05 01:11:25 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2361 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2361 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 5579 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 56731893 # ITB inst hits
system.cpu0.itb.inst_misses 3218 # ITB inst misses
2013-01-07 19:05:52 +01:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
2015-12-05 01:11:25 +01:00
system.cpu0.itb.flush_tlb 2941 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 437 # Number of times TLB was flushed by MVA
2014-10-30 05:18:29 +01:00
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2015-12-05 01:11:25 +01:00
system.cpu0.itb.flush_entries 2380 # Number of entries that have been flushed from TLB
2013-01-07 19:05:52 +01:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
2015-12-05 01:11:25 +01:00
system.cpu0.itb.inst_accesses 56735111 # ITB inst accesses
system.cpu0.itb.hits 56731893 # DTB hits
system.cpu0.itb.misses 3218 # DTB misses
system.cpu0.itb.accesses 56735111 # DTB accesses
system.cpu0.numCycles 2910044257 # number of cpu cycles simulated
2013-01-07 19:05:52 +01:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
2015-12-05 01:11:25 +01:00
system.cpu0.kern.inst.quiesce 3034 # number of quiesce instructions executed
system.cpu0.committedInsts 55192175 # Number of instructions committed
system.cpu0.committedOps 66601030 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 58838667 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 5226 # Number of float alu accesses
system.cpu0.num_func_calls 4816070 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 7555391 # number of instructions that are conditional controls
system.cpu0.num_int_insts 58838667 # number of integer instructions
system.cpu0.num_fp_insts 5226 # number of float instructions
system.cpu0.num_int_register_reads 106920418 # number of times the integer registers were read
system.cpu0.num_int_register_writes 40489001 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 3747 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 1482 # number of times the floating registers were written
system.cpu0.num_cc_register_reads 240444662 # number of times the CC registers were read
system.cpu0.num_cc_register_writes 25665883 # number of times the CC registers were written
system.cpu0.num_mem_refs 22275144 # number of memory refs
system.cpu0.num_load_insts 12196401 # Number of load instructions
system.cpu0.num_store_insts 10078743 # Number of store instructions
system.cpu0.num_idle_cycles 2694612539.353109 # Number of idle cycles
system.cpu0.num_busy_cycles 215431717.646891 # Number of busy cycles
system.cpu0.not_idle_fraction 0.074030 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.925970 # Percentage of idle cycles
system.cpu0.Branches 12738975 # Number of branches fetched
system.cpu0.op_class::No_OpClass 134 0.00% 0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu 45781986 67.21% 67.21% # Class of executed instruction
system.cpu0.op_class::IntMult 56167 0.08% 67.29% # Class of executed instruction
system.cpu0.op_class::IntDiv 0 0.00% 67.29% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 67.29% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 67.29% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 67.29% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 67.29% # Class of executed instruction
system.cpu0.op_class::FloatDiv 0 0.00% 67.29% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 67.29% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 67.29% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 67.29% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 67.29% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 67.29% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 67.29% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 67.29% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 67.29% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 67.29% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 67.29% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.29% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 67.29% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.29% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.29% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.29% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.29% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.29% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 3968 0.01% 67.30% # Class of executed instruction
2015-11-06 09:26:50 +01:00
system.cpu0.op_class::SimdFloatMult 0 0.00% 67.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.30% # Class of executed instruction
2015-12-05 01:11:25 +01:00
system.cpu0.op_class::MemRead 12196401 17.90% 85.20% # Class of executed instruction
system.cpu0.op_class::MemWrite 10078743 14.80% 100.00% # Class of executed instruction
2015-11-06 09:26:50 +01:00
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
2015-12-05 01:11:25 +01:00
system.cpu0.op_class::total 68117399 # Class of executed instruction
system.cpu0.dcache.tags.replacements 819062 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.702235 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 43234880 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 819574 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 52.752869 # Average number of references to valid blocks.
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.tags.warmup_cycle 1736913500 # Cycle when the warmup percentage was hit.
2015-12-05 01:11:25 +01:00
system.cpu0.dcache.tags.occ_blocks::cpu0.data 43.309006 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 468.393230 # Average occupied blocks per requestor
2015-11-06 09:26:50 +01:00
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.084588 # Average percentage of cache occupancy
2015-12-05 01:11:25 +01:00
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.914831 # Average percentage of cache occupancy
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.tags.occ_percent::total 0.999418 # Average percentage of cache occupancy
2014-01-24 22:29:33 +01:00
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
2014-01-24 22:29:33 +01:00
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2015-12-05 01:11:25 +01:00
system.cpu0.dcache.tags.tag_accesses 177106290 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 177106290 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 11353905 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 11758208 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 23112113 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 9226963 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 9596855 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 18823818 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 190234 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 202489 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 392723 # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 213697 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 229550 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 443247 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 221754 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 238460 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 460214 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 20580868 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 21355063 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 41935931 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 20771102 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 21557552 # number of overall hits
system.cpu0.dcache.overall_hits::total 42328654 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 199783 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 200066 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 399849 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 149794 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 148846 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 298640 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 58818 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 59499 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 118317 # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10855 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 11895 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 22750 # number of LoadLockedReq misses
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.StoreCondReq_misses::cpu1.data 2 # number of StoreCondReq misses
2014-10-30 05:18:29 +01:00
system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
2015-12-05 01:11:25 +01:00
system.cpu0.dcache.demand_misses::cpu0.data 349577 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 348912 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 698489 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 408395 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 408411 # number of overall misses
system.cpu0.dcache.overall_misses::total 816806 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3309369500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3172445000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 6481814500 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9848447000 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 9257158000 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 19105605000 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 137223000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 156952000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 294175000 # number of LoadLockedReq miss cycles
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 164000 # number of StoreCondReq miss cycles
2015-03-02 11:04:20 +01:00
system.cpu0.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles
2015-12-05 01:11:25 +01:00
system.cpu0.dcache.demand_miss_latency::cpu0.data 13157816500 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 12429603000 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 25587419500 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 13157816500 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 12429603000 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 25587419500 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 11553688 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 11958274 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 23511962 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 9376757 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 9745701 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 19122458 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 249052 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 261988 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 511040 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 224552 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 241445 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 465997 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 221754 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 238462 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 460216 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 20930445 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 21703975 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 42634420 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 21179497 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 21965963 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 43145460 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.017292 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.016730 # miss rate for ReadReq accesses
2015-11-06 09:26:50 +01:00
system.cpu0.dcache.ReadReq_miss_rate::total 0.017006 # miss rate for ReadReq accesses
2015-12-05 01:11:25 +01:00
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.015975 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015273 # miss rate for WriteReq accesses
2015-11-06 09:26:50 +01:00
system.cpu0.dcache.WriteReq_miss_rate::total 0.015617 # miss rate for WriteReq accesses
2015-12-05 01:11:25 +01:00
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.236168 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.227106 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.231522 # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048341 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.049266 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048820 # miss rate for LoadLockedReq accesses
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000008 # miss rate for StoreCondReq accesses
2014-10-30 05:18:29 +01:00
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
2015-12-05 01:11:25 +01:00
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016702 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.016076 # miss rate for demand accesses
2015-11-06 09:26:50 +01:00
system.cpu0.dcache.demand_miss_rate::total 0.016383 # miss rate for demand accesses
2015-12-05 01:11:25 +01:00
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019283 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.018593 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.018931 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16564.820330 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15856.992193 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 16210.655773 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65746.605338 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 62192.857047 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 63975.371685 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12641.455550 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13194.787726 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12930.769231 # average LoadLockedReq miss latency
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 82000 # average StoreCondReq miss latency
2015-03-02 11:04:20 +01:00
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency
2015-12-05 01:11:25 +01:00
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37639.251152 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35623.890838 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 36632.530362 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32218.358452 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 30434.055400 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 31326.189450 # average overall miss latency
2015-07-03 16:15:03 +02:00
system.cpu0.dcache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2014-10-30 05:18:29 +01:00
system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
2015-07-03 16:15:03 +02:00
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
2015-12-05 01:11:25 +01:00
system.cpu0.dcache.writebacks::writebacks 683867 # number of writebacks
system.cpu0.dcache.writebacks::total 683867 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 471 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 454 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 925 # number of ReadReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 7013 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 7211 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14224 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 471 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data 454 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 925 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 471 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data 454 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 925 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 199312 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 199612 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 398924 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 149794 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 148846 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 298640 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 57717 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 58554 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 116271 # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 3842 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 4684 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8526 # number of LoadLockedReq MSHR misses
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 2 # number of StoreCondReq MSHR misses
2014-10-30 05:18:29 +01:00
system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
2015-12-05 01:11:25 +01:00
system.cpu0.dcache.demand_mshr_misses::cpu0.data 349106 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 348458 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 697564 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 406823 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 407012 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 813835 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 14993 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 16145 # number of ReadReq MSHR uncacheable
2015-07-03 16:15:03 +02:00
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31138 # number of ReadReq MSHR uncacheable
2015-12-05 01:11:25 +01:00
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 13371 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 14218 # number of WriteReq MSHR uncacheable
2015-07-03 16:15:03 +02:00
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable
2015-12-05 01:11:25 +01:00
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 28364 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 30363 # number of overall MSHR uncacheable misses
2015-07-03 16:15:03 +02:00
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 58727 # number of overall MSHR uncacheable misses
2015-12-05 01:11:25 +01:00
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3093759000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2959743000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6053502000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9698653000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 9108312000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 18806965000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 795616000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 818334500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1613950500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 52173500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63283500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 115457000 # number of LoadLockedReq MSHR miss cycles
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 162000 # number of StoreCondReq MSHR miss cycles
2015-07-03 16:15:03 +02:00
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 162000 # number of StoreCondReq MSHR miss cycles
2015-12-05 01:11:25 +01:00
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12792412000 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 12068055000 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 24860467000 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13588028000 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 12886389500 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 26474417500 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3047137000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3231000000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6278137000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2491876500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2598064000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5089940500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5539013500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5829064000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11368077500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017251 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016692 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016967 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015975 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015273 # mshr miss rate for WriteReq accesses
2015-11-06 09:26:50 +01:00
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015617 # mshr miss rate for WriteReq accesses
2015-12-05 01:11:25 +01:00
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.231747 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.223499 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.227518 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017110 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019400 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018296 # mshr miss rate for LoadLockedReq accesses
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000008 # mshr miss rate for StoreCondReq accesses
2014-10-30 05:18:29 +01:00
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses
2015-12-05 01:11:25 +01:00
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016679 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016055 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.016362 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019208 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.018529 # mshr miss rate for overall accesses
2015-11-06 09:26:50 +01:00
system.cpu0.dcache.overall_mshr_miss_rate::total 0.018863 # mshr miss rate for overall accesses
2015-12-05 01:11:25 +01:00
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15522.191338 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14827.480312 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15174.574606 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 64746.605338 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 61192.857047 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 62975.371685 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13784.777449 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13975.723264 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13880.937637 # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13579.776158 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13510.567891 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13541.754633 # average LoadLockedReq mshr miss latency
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 81000 # average StoreCondReq mshr miss latency
2015-07-03 16:15:03 +02:00
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency
2015-12-05 01:11:25 +01:00
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 36643.346147 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 34632.739096 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35638.976495 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33400.343638 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 31660.957171 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32530.448432 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 203237.310745 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 200123.877361 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201623.000835 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 186364.258470 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 182730.623154 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184491.663344 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 195283.228741 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 191979.185193 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193574.974032 # average overall mshr uncacheable latency
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-12-05 01:11:25 +01:00
system.cpu0.icache.tags.replacements 1695832 # number of replacements
system.cpu0.icache.tags.tagsinuse 510.436658 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 113855734 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 1696344 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 67.118305 # Average number of references to valid blocks.
2015-11-06 09:26:50 +01:00
system.cpu0.icache.tags.warmup_cycle 29075840500 # Cycle when the warmup percentage was hit.
2015-12-05 01:11:25 +01:00
system.cpu0.icache.tags.occ_blocks::cpu0.inst 60.007721 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 450.428938 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.117203 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.879744 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.996947 # Average percentage of cache occupancy
2014-11-12 15:05:25 +01:00
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2015-07-03 16:15:03 +02:00
system.cpu0.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id
2015-09-25 13:27:03 +02:00
system.cpu0.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id
2014-11-12 15:05:25 +01:00
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2015-12-05 01:11:25 +01:00
system.cpu0.icache.tags.tag_accesses 117248434 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 117248434 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 55890585 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 57965149 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 113855734 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 55890585 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 57965149 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 113855734 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 55890585 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 57965149 # number of overall hits
system.cpu0.icache.overall_hits::total 113855734 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 841308 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 855042 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 1696350 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 841308 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 855042 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 1696350 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 841308 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 855042 # number of overall misses
system.cpu0.icache.overall_misses::total 1696350 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11907607000 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 12366012000 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 24273619000 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 11907607000 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 12366012000 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 24273619000 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 11907607000 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 12366012000 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 24273619000 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 56731893 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 58820191 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 115552084 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 56731893 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 58820191 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 115552084 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 56731893 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 58820191 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 115552084 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014830 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014537 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.014680 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014830 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014537 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.014680 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014830 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014537 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.014680 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14153.683312 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14462.461493 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14309.322369 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14153.683312 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14462.461493 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14309.322369 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14153.683312 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14462.461493 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14309.322369 # average overall miss latency
2014-11-12 15:05:25 +01:00
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
2015-12-05 01:11:25 +01:00
system.cpu0.icache.writebacks::writebacks 1695832 # number of writebacks
system.cpu0.icache.writebacks::total 1695832 # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 841308 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 855042 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 1696350 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 841308 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 855042 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 1696350 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 841308 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 855042 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 1696350 # number of overall MSHR misses
2015-09-25 13:27:03 +02:00
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 5645 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst 3377 # number of ReadReq MSHR uncacheable
2015-05-05 09:22:39 +02:00
system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable
2015-09-25 13:27:03 +02:00
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 5645 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst 3377 # number of overall MSHR uncacheable misses
2015-05-05 09:22:39 +02:00
system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses
2015-12-05 01:11:25 +01:00
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11066299000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 11510970000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 22577269000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11066299000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 11510970000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 22577269000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11066299000 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 11510970000 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 22577269000 # number of overall MSHR miss cycles
2015-09-25 13:27:03 +02:00
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 713903000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 428990000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1142893000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 713903000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 428990000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 1142893000 # number of overall MSHR uncacheable cycles
2015-12-05 01:11:25 +01:00
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014830 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014537 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014680 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014830 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014537 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.014680 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014830 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014537 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.014680 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13153.683312 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13462.461493 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13309.322369 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13153.683312 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13462.461493 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 13309.322369 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13153.683312 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13462.461493 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13309.322369 # average overall mshr miss latency
2015-09-25 13:27:03 +02:00
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 126466.430469 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127032.869411 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 126678.452671 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 126466.430469 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127032.869411 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 126678.452671 # average overall mshr uncacheable latency
2014-11-12 15:05:25 +01:00
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2014-12-23 15:31:20 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2015-12-05 01:11:25 +01:00
system.cpu1.dtb.walker.walks 6967 # Table walker walks requested
system.cpu1.dtb.walker.walksShort 6967 # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 2209 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4758 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples 6967 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0 6967 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 6967 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 5854 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 13310.386061 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 11595.564813 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 7355.876792 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-32767 5853 99.98% 99.98% # Table walker service (enqueue to completion) latency
2015-09-25 13:27:03 +02:00
system.cpu1.dtb.walker.walkCompletionTime::262144-294911 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
2015-12-05 01:11:25 +01:00
system.cpu1.dtb.walker.walkCompletionTime::total 5854 # Table walker service (enqueue to completion) latency
2015-09-25 13:27:03 +02:00
system.cpu1.dtb.walker.walksPending::samples 1639416500 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 1639416500 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 1639416500 # Table walker pending requests distribution
2015-12-05 01:11:25 +01:00
system.cpu1.dtb.walker.walkPageSizes::4K 3666 62.62% 62.62% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M 2188 37.38% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 5854 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6967 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2015-12-05 01:11:25 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6967 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5854 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2015-12-05 01:11:25 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5854 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 12821 # Table walker requests started/completed, data/inst
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
2015-12-05 01:11:25 +01:00
system.cpu1.dtb.read_hits 12477838 # DTB read hits
system.cpu1.dtb.read_misses 5947 # DTB read misses
system.cpu1.dtb.write_hits 9996447 # DTB write hits
system.cpu1.dtb.write_misses 1020 # DTB write misses
system.cpu1.dtb.flush_tlb 2941 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 480 # Number of times TLB was flushed by MVA
2014-10-30 05:18:29 +01:00
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2015-12-05 01:11:25 +01:00
system.cpu1.dtb.flush_entries 4688 # Number of entries that have been flushed from TLB
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
2015-12-05 01:11:25 +01:00
system.cpu1.dtb.prefetch_faults 911 # Number of TLB faults due to prefetch
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2015-12-05 01:11:25 +01:00
system.cpu1.dtb.perms_faults 231 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 12483785 # DTB read accesses
system.cpu1.dtb.write_accesses 9997467 # DTB write accesses
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
2015-12-05 01:11:25 +01:00
system.cpu1.dtb.hits 22474285 # DTB hits
system.cpu1.dtb.misses 6967 # DTB misses
system.cpu1.dtb.accesses 22481252 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2015-12-05 01:11:25 +01:00
system.cpu1.itb.walker.walks 3507 # Table walker walks requested
system.cpu1.itb.walker.walksShort 3507 # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1 840 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2667 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples 3507 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0 3507 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 3507 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 2709 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 13994.462901 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 12131.377414 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 7198.145608 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-16383 1959 72.31% 72.31% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-32767 749 27.65% 99.96% # Table walker service (enqueue to completion) latency
2015-09-25 13:27:03 +02:00
system.cpu1.itb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
2015-12-05 01:11:25 +01:00
system.cpu1.itb.walker.walkCompletionTime::total 2709 # Table walker service (enqueue to completion) latency
2015-09-25 13:27:03 +02:00
system.cpu1.itb.walker.walksPending::samples 1638889000 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 1638889000 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 1638889000 # Table walker pending requests distribution
2015-12-05 01:11:25 +01:00
system.cpu1.itb.walker.walkPageSizes::4K 1869 68.99% 68.99% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M 840 31.01% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 2709 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2015-12-05 01:11:25 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3507 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3507 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2015-12-05 01:11:25 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2709 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2709 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 6216 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 58820191 # ITB inst hits
system.cpu1.itb.inst_misses 3507 # ITB inst misses
2013-01-07 19:05:52 +01:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
2015-12-05 01:11:25 +01:00
system.cpu1.itb.flush_tlb 2941 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 480 # Number of times TLB was flushed by MVA
2014-10-30 05:18:29 +01:00
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2015-12-05 01:11:25 +01:00
system.cpu1.itb.flush_entries 2713 # Number of entries that have been flushed from TLB
2013-01-07 19:05:52 +01:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
2015-12-05 01:11:25 +01:00
system.cpu1.itb.inst_accesses 58823698 # ITB inst accesses
system.cpu1.itb.hits 58820191 # DTB hits
system.cpu1.itb.misses 3507 # DTB misses
system.cpu1.itb.accesses 58823698 # DTB accesses
system.cpu1.numCycles 2909297686 # number of cpu cycles simulated
2013-01-07 19:05:52 +01:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
2015-12-05 01:11:25 +01:00
system.cpu1.committedInsts 57262734 # Number of instructions committed
system.cpu1.committedOps 68983998 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 61052130 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 5870 # Number of float alu accesses
system.cpu1.num_func_calls 5075478 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 7674901 # number of instructions that are conditional controls
system.cpu1.num_int_insts 61052130 # number of integer instructions
system.cpu1.num_fp_insts 5870 # number of float instructions
system.cpu1.num_int_register_reads 111137302 # number of times the integer registers were read
system.cpu1.num_int_register_writes 42154976 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 4637 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 1234 # number of times the floating registers were written
system.cpu1.num_cc_register_reads 249286409 # number of times the CC registers were read
system.cpu1.num_cc_register_writes 26228170 # number of times the CC registers were written
system.cpu1.num_mem_refs 23131429 # number of memory refs
system.cpu1.num_load_insts 12645834 # Number of load instructions
system.cpu1.num_store_insts 10485595 # Number of store instructions
system.cpu1.num_idle_cycles 2689887383.006891 # Number of idle cycles
system.cpu1.num_busy_cycles 219410302.993109 # Number of busy cycles
system.cpu1.not_idle_fraction 0.075417 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.924583 # Percentage of idle cycles
system.cpu1.Branches 13176890 # Number of branches fetched
system.cpu1.op_class::No_OpClass 2203 0.00% 0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu 47391308 67.14% 67.14% # Class of executed instruction
system.cpu1.op_class::IntMult 58256 0.08% 67.22% # Class of executed instruction
2015-11-06 09:26:50 +01:00
system.cpu1.op_class::IntDiv 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::FloatDiv 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.22% # Class of executed instruction
2015-12-05 01:11:25 +01:00
system.cpu1.op_class::SimdFloatMisc 4483 0.01% 67.23% # Class of executed instruction
2015-11-06 09:26:50 +01:00
system.cpu1.op_class::SimdFloatMult 0 0.00% 67.23% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.23% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.23% # Class of executed instruction
2015-12-05 01:11:25 +01:00
system.cpu1.op_class::MemRead 12645834 17.92% 85.15% # Class of executed instruction
system.cpu1.op_class::MemWrite 10485595 14.85% 100.00% # Class of executed instruction
2015-11-06 09:26:50 +01:00
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
2015-12-05 01:11:25 +01:00
system.cpu1.op_class::total 70587679 # Class of executed instruction
2015-09-25 13:27:03 +02:00
system.iobus.trans_dist::ReadReq 30177 # Transaction distribution
system.iobus.trans_dist::ReadResp 30177 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.iobus.trans_dist::WriteResp 59014 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72904 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72904 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 178382 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321056 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321056 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2480181 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer0.occupancy 46334000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer1.occupancy 98000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer2.occupancy 336000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer3.occupancy 30000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 95000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer8.occupancy 644000 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer16.occupancy 52000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer18.occupancy 12000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer23.occupancy 6288000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer24.occupancy 36457000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer25.occupancy 186225545 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2015-03-02 11:04:20 +01:00
system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.iobus.respLayer3.occupancy 36728000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.iocache.tags.replacements 36418 # number of replacements
2015-12-05 01:11:25 +01:00
system.iocache.tags.tagsinuse 1.084397 # Cycle average of tags in use
2013-08-19 09:52:36 +02:00
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
2015-09-25 13:27:03 +02:00
system.iocache.tags.sampled_refs 36434 # Sample count of references to valid blocks.
2014-10-30 05:18:29 +01:00
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
2015-11-06 09:26:50 +01:00
system.iocache.tags.warmup_cycle 313834390000 # Cycle when the warmup percentage was hit.
2015-12-05 01:11:25 +01:00
system.iocache.tags.occ_blocks::realview.ide 1.084397 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.067775 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.067775 # Average percentage of cache occupancy
2014-10-30 05:18:29 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2015-09-25 13:27:03 +02:00
system.iocache.tags.tag_accesses 328068 # Number of tag accesses
system.iocache.tags.data_accesses 328068 # Number of data accesses
system.iocache.ReadReq_misses::realview.ide 228 # number of ReadReq misses
system.iocache.ReadReq_misses::total 228 # number of ReadReq misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
2015-09-25 13:27:03 +02:00
system.iocache.demand_misses::realview.ide 228 # number of demand (read+write) misses
system.iocache.demand_misses::total 228 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 228 # number of overall misses
system.iocache.overall_misses::total 228 # number of overall misses
2015-12-05 01:11:25 +01:00
system.iocache.ReadReq_miss_latency::realview.ide 28184876 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 28184876 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 4715128669 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 4715128669 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide 28184876 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 28184876 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 28184876 # number of overall miss cycles
system.iocache.overall_miss_latency::total 28184876 # number of overall miss cycles
2015-09-25 13:27:03 +02:00
system.iocache.ReadReq_accesses::realview.ide 228 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 228 # number of ReadReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
2015-09-25 13:27:03 +02:00
system.iocache.demand_accesses::realview.ide 228 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 228 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 228 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 228 # number of overall (read+write) accesses
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2014-10-30 05:18:29 +01:00
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2015-12-05 01:11:25 +01:00
system.iocache.ReadReq_avg_miss_latency::realview.ide 123617.877193 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 123617.877193 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130165.875359 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 130165.875359 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 123617.877193 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 123617.877193 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 123617.877193 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 123617.877193 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 572 # number of cycles access was blocked
2013-01-07 19:05:52 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.iocache.blocked::no_mshrs 60 # number of cycles access was blocked
2013-01-07 19:05:52 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2015-12-05 01:11:25 +01:00
system.iocache.avg_blocked_cycles::no_mshrs 9.533333 # average number of cycles each access was blocked
2013-01-07 19:05:52 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2014-12-02 12:08:25 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
2013-01-07 19:05:52 +01:00
system.iocache.cache_copies 0 # number of cache copies performed
2014-12-02 12:08:25 +01:00
system.iocache.writebacks::writebacks 36190 # number of writebacks
system.iocache.writebacks::total 36190 # number of writebacks
2015-09-25 13:27:03 +02:00
system.iocache.ReadReq_mshr_misses::realview.ide 228 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
2015-09-25 13:27:03 +02:00
system.iocache.demand_mshr_misses::realview.ide 228 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 228 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 228 # number of overall MSHR misses
2015-12-05 01:11:25 +01:00
system.iocache.ReadReq_mshr_miss_latency::realview.ide 16784876 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 16784876 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2903928669 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 2903928669 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 16784876 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 16784876 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 16784876 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 16784876 # number of overall MSHR miss cycles
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2014-10-30 05:18:29 +01:00
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2015-12-05 01:11:25 +01:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73617.877193 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 73617.877193 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80165.875359 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80165.875359 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 73617.877193 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 73617.877193 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 73617.877193 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 73617.877193 # average overall mshr miss latency
2013-01-07 19:05:52 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-12-05 01:11:25 +01:00
system.l2c.tags.replacements 87560 # number of replacements
system.l2c.tags.tagsinuse 64865.201521 # Cycle average of tags in use
system.l2c.tags.total_refs 4551354 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 152795 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 29.787323 # Average number of references to valid blocks.
2014-11-12 15:05:25 +01:00
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-12-05 01:11:25 +01:00
system.l2c.tags.occ_blocks::writebacks 50199.128097 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.905025 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 4090.007642 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 2504.647366 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.838092 # Average occupied blocks per requestor
2015-11-06 09:26:50 +01:00
system.l2c.tags.occ_blocks::cpu1.itb.walker 0.000605 # Average occupied blocks per requestor
2015-12-05 01:11:25 +01:00
system.l2c.tags.occ_blocks::cpu1.inst 5610.818089 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 2455.856604 # Average occupied blocks per requestor
2015-11-06 09:26:50 +01:00
system.l2c.tags.occ_percent::writebacks 0.765978 # Average percentage of cache occupancy
2015-09-25 13:27:03 +02:00
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000029 # Average percentage of cache occupancy
2015-12-05 01:11:25 +01:00
system.l2c.tags.occ_percent::cpu0.inst 0.062409 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.038218 # Average percentage of cache occupancy
2015-09-25 13:27:03 +02:00
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000043 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy
2015-12-05 01:11:25 +01:00
system.l2c.tags.occ_percent::cpu1.inst 0.085614 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.037473 # Average percentage of cache occupancy
2015-11-06 09:26:50 +01:00
system.l2c.tags.occ_percent::total 0.989764 # Average percentage of cache occupancy
2015-09-25 13:27:03 +02:00
system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.l2c.tags.occ_task_id_blocks::1024 65231 # Occupied blocks per task id
2015-09-25 13:27:03 +02:00
system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.l2c.tags.age_task_id_blocks_1024::0 13 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 2129 # Occupied blocks per task id
2015-12-05 01:11:25 +01:00
system.l2c.tags.age_task_id_blocks_1024::3 6852 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 56199 # Occupied blocks per task id
2015-09-25 13:27:03 +02:00
system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id
2015-11-06 09:26:50 +01:00
system.l2c.tags.occ_task_id_percent::1024 0.995346 # Percentage of cache occupancy per task id
2015-12-05 01:11:25 +01:00
system.l2c.tags.tag_accesses 40566832 # Number of tag accesses
system.l2c.tags.data_accesses 40566832 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 5848 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 3044 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 6379 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 3501 # number of ReadReq hits
system.l2c.ReadReq_hits::total 18772 # number of ReadReq hits
system.l2c.WritebackDirty_hits::writebacks 683867 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 683867 # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks 1665046 # number of WritebackClean hits
system.l2c.WritebackClean_hits::total 1665046 # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 10 # number of UpgradeReq hits
2015-11-06 09:26:50 +01:00
system.l2c.UpgradeReq_hits::total 23 # number of UpgradeReq hits
2015-12-05 01:11:25 +01:00
system.l2c.ReadExReq_hits::cpu0.data 81302 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 85662 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 166964 # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst 833466 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst 844870 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total 1678336 # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 254311 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 257239 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 511550 # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker 5848 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 3044 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 833466 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 335613 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 6379 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 3501 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 844870 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 342901 # number of demand (read+write) hits
system.l2c.demand_hits::total 2375622 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 5848 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 3044 # number of overall hits
system.l2c.overall_hits::cpu0.inst 833466 # number of overall hits
system.l2c.overall_hits::cpu0.data 335613 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 6379 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 3501 # number of overall hits
system.l2c.overall_hits::cpu1.inst 844870 # number of overall hits
system.l2c.overall_hits::cpu1.data 342901 # number of overall hits
system.l2c.overall_hits::total 2375622 # number of overall hits
2015-07-03 16:15:03 +02:00
system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses
2015-09-25 13:27:03 +02:00
system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses
system.l2c.ReadReq_misses::total 8 # number of ReadReq misses
2015-12-05 01:11:25 +01:00
system.l2c.UpgradeReq_misses::cpu0.data 1368 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 1372 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 2740 # number of UpgradeReq misses
2015-09-25 13:27:03 +02:00
system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses
2014-11-12 15:05:25 +01:00
system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
2015-12-05 01:11:25 +01:00
system.l2c.ReadExReq_misses::cpu0.data 67111 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 61802 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 128913 # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst 7825 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst 10154 # number of ReadCleanReq misses
2015-11-06 09:26:50 +01:00
system.l2c.ReadCleanReq_misses::total 17979 # number of ReadCleanReq misses
2015-12-05 01:11:25 +01:00
system.l2c.ReadSharedReq_misses::cpu0.data 6560 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 5611 # number of ReadSharedReq misses
2015-11-06 09:26:50 +01:00
system.l2c.ReadSharedReq_misses::total 12171 # number of ReadSharedReq misses
2015-07-03 16:15:03 +02:00
system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses
2015-12-05 01:11:25 +01:00
system.l2c.demand_misses::cpu0.inst 7825 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 73671 # number of demand (read+write) misses
2015-09-25 13:27:03 +02:00
system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
2015-12-05 01:11:25 +01:00
system.l2c.demand_misses::cpu1.inst 10154 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 67413 # number of demand (read+write) misses
system.l2c.demand_misses::total 159071 # number of demand (read+write) misses
2015-07-03 16:15:03 +02:00
system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses
2015-12-05 01:11:25 +01:00
system.l2c.overall_misses::cpu0.inst 7825 # number of overall misses
system.l2c.overall_misses::cpu0.data 73671 # number of overall misses
2015-09-25 13:27:03 +02:00
system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
2015-12-05 01:11:25 +01:00
system.l2c.overall_misses::cpu1.inst 10154 # number of overall misses
system.l2c.overall_misses::cpu1.data 67413 # number of overall misses
system.l2c.overall_misses::total 159071 # number of overall misses
2015-11-06 09:26:50 +01:00
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 530500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 398500 # number of ReadReq miss cycles
2015-09-25 13:27:03 +02:00
system.l2c.ReadReq_miss_latency::cpu1.itb.walker 133000 # number of ReadReq miss cycles
2015-11-06 09:26:50 +01:00
system.l2c.ReadReq_miss_latency::total 1062000 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 1048500 # number of UpgradeReq miss cycles
2015-12-05 01:11:25 +01:00
system.l2c.UpgradeReq_miss_latency::cpu1.data 808500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 1857000 # number of UpgradeReq miss cycles
2015-09-25 13:27:03 +02:00
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 159000 # number of SCUpgradeReq miss cycles
2015-03-02 11:04:20 +01:00
system.l2c.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles
2015-12-05 01:11:25 +01:00
system.l2c.ReadExReq_miss_latency::cpu0.data 8507840500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 7872807000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 16380647500 # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1024152500 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst 1327263000 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total 2351415500 # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data 871431000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data 737412500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 1608843500 # number of ReadSharedReq miss cycles
2015-11-06 09:26:50 +01:00
system.l2c.demand_miss_latency::cpu0.dtb.walker 530500 # number of demand (read+write) miss cycles
2015-12-05 01:11:25 +01:00
system.l2c.demand_miss_latency::cpu0.inst 1024152500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 9379271500 # number of demand (read+write) miss cycles
2015-11-06 09:26:50 +01:00
system.l2c.demand_miss_latency::cpu1.dtb.walker 398500 # number of demand (read+write) miss cycles
2015-09-25 13:27:03 +02:00
system.l2c.demand_miss_latency::cpu1.itb.walker 133000 # number of demand (read+write) miss cycles
2015-12-05 01:11:25 +01:00
system.l2c.demand_miss_latency::cpu1.inst 1327263000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 8610219500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 20341968500 # number of demand (read+write) miss cycles
2015-11-06 09:26:50 +01:00
system.l2c.overall_miss_latency::cpu0.dtb.walker 530500 # number of overall miss cycles
2015-12-05 01:11:25 +01:00
system.l2c.overall_miss_latency::cpu0.inst 1024152500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 9379271500 # number of overall miss cycles
2015-11-06 09:26:50 +01:00
system.l2c.overall_miss_latency::cpu1.dtb.walker 398500 # number of overall miss cycles
2015-09-25 13:27:03 +02:00
system.l2c.overall_miss_latency::cpu1.itb.walker 133000 # number of overall miss cycles
2015-12-05 01:11:25 +01:00
system.l2c.overall_miss_latency::cpu1.inst 1327263000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 8610219500 # number of overall miss cycles
system.l2c.overall_miss_latency::total 20341968500 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 5852 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 3044 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 6382 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 3502 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 18780 # number of ReadReq accesses(hits+misses)
system.l2c.WritebackDirty_accesses::writebacks 683867 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total 683867 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks 1665046 # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total 1665046 # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 1381 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 1382 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 2763 # number of UpgradeReq accesses(hits+misses)
2015-09-25 13:27:03 +02:00
system.l2c.SCUpgradeReq_accesses::cpu1.data 2 # number of SCUpgradeReq accesses(hits+misses)
2014-11-12 15:05:25 +01:00
system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
2015-12-05 01:11:25 +01:00
system.l2c.ReadExReq_accesses::cpu0.data 148413 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 147464 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 295877 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst 841291 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst 855024 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total 1696315 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data 260871 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data 262850 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 523721 # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 5852 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 3044 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 841291 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 409284 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 6382 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 3502 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 855024 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 410314 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2534693 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 5852 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 3044 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 841291 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 409284 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 6382 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 3502 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 855024 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 410314 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2534693 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000684 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000470 # miss rate for ReadReq accesses
2015-11-06 09:26:50 +01:00
system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000286 # miss rate for ReadReq accesses
2015-12-05 01:11:25 +01:00
system.l2c.ReadReq_miss_rate::total 0.000426 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990587 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.992764 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.991676 # miss rate for UpgradeReq accesses
2015-09-25 13:27:03 +02:00
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
2014-11-12 15:05:25 +01:00
system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
2015-12-05 01:11:25 +01:00
system.l2c.ReadExReq_miss_rate::cpu0.data 0.452191 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.419099 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.435698 # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.009301 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.011876 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total 0.010599 # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.025147 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.021347 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.023239 # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000684 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.009301 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.180000 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000470 # miss rate for demand accesses
2015-11-06 09:26:50 +01:00
system.l2c.demand_miss_rate::cpu1.itb.walker 0.000286 # miss rate for demand accesses
2015-12-05 01:11:25 +01:00
system.l2c.demand_miss_rate::cpu1.inst 0.011876 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.164296 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.062758 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000684 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.009301 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.180000 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000470 # miss rate for overall accesses
2015-11-06 09:26:50 +01:00
system.l2c.overall_miss_rate::cpu1.itb.walker 0.000286 # miss rate for overall accesses
2015-12-05 01:11:25 +01:00
system.l2c.overall_miss_rate::cpu1.inst 0.011876 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.164296 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.062758 # miss rate for overall accesses
2015-11-06 09:26:50 +01:00
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 132625 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 132833.333333 # average ReadReq miss latency
2015-09-25 13:27:03 +02:00
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 133000 # average ReadReq miss latency
2015-11-06 09:26:50 +01:00
system.l2c.ReadReq_avg_miss_latency::total 132750 # average ReadReq miss latency
2015-12-05 01:11:25 +01:00
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 766.447368 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 589.285714 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 677.737226 # average UpgradeReq miss latency
2015-09-25 13:27:03 +02:00
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 79500 # average SCUpgradeReq miss latency
2015-03-02 11:04:20 +01:00
system.l2c.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency
2015-12-05 01:11:25 +01:00
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 126772.667670 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 127387.576454 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 127067.460225 # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 130882.108626 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 130713.314950 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 130786.779020 # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 132840.091463 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 131422.651934 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 132186.632158 # average ReadSharedReq miss latency
2015-11-06 09:26:50 +01:00
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 132625 # average overall miss latency
2015-12-05 01:11:25 +01:00
system.l2c.demand_avg_miss_latency::cpu0.inst 130882.108626 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 127312.938605 # average overall miss latency
2015-11-06 09:26:50 +01:00
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 132833.333333 # average overall miss latency
2015-09-25 13:27:03 +02:00
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 133000 # average overall miss latency
2015-12-05 01:11:25 +01:00
system.l2c.demand_avg_miss_latency::cpu1.inst 130713.314950 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 127723.428716 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 127879.805244 # average overall miss latency
2015-11-06 09:26:50 +01:00
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 132625 # average overall miss latency
2015-12-05 01:11:25 +01:00
system.l2c.overall_avg_miss_latency::cpu0.inst 130882.108626 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 127312.938605 # average overall miss latency
2015-11-06 09:26:50 +01:00
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 132833.333333 # average overall miss latency
2015-09-25 13:27:03 +02:00
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 133000 # average overall miss latency
2015-12-05 01:11:25 +01:00
system.l2c.overall_avg_miss_latency::cpu1.inst 130713.314950 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 127723.428716 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 127879.805244 # average overall miss latency
2014-11-12 15:05:25 +01:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
2015-11-06 09:26:50 +01:00
system.l2c.writebacks::writebacks 81184 # number of writebacks
system.l2c.writebacks::total 81184 # number of writebacks
2015-07-03 16:15:03 +02:00
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 4 # number of ReadReq MSHR misses
2015-09-25 13:27:03 +02:00
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 3 # number of ReadReq MSHR misses
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system.l2c.ReadReq_mshr_misses::total 8 # number of ReadReq MSHR misses
2015-12-05 01:11:25 +01:00
system.l2c.UpgradeReq_mshr_misses::cpu0.data 1368 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 1372 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 2740 # number of UpgradeReq MSHR misses
2015-09-25 13:27:03 +02:00
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 2 # number of SCUpgradeReq MSHR misses
2014-11-12 15:05:25 +01:00
system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
2015-12-05 01:11:25 +01:00
system.l2c.ReadExReq_mshr_misses::cpu0.data 67111 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 61802 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 128913 # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 7825 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 10154 # number of ReadCleanReq MSHR misses
2015-11-06 09:26:50 +01:00
system.l2c.ReadCleanReq_mshr_misses::total 17979 # number of ReadCleanReq MSHR misses
2015-12-05 01:11:25 +01:00
system.l2c.ReadSharedReq_mshr_misses::cpu0.data 6560 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 5611 # number of ReadSharedReq MSHR misses
2015-11-06 09:26:50 +01:00
system.l2c.ReadSharedReq_mshr_misses::total 12171 # number of ReadSharedReq MSHR misses
2015-07-03 16:15:03 +02:00
system.l2c.demand_mshr_misses::cpu0.dtb.walker 4 # number of demand (read+write) MSHR misses
2015-12-05 01:11:25 +01:00
system.l2c.demand_mshr_misses::cpu0.inst 7825 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 73671 # number of demand (read+write) MSHR misses
2015-09-25 13:27:03 +02:00
system.l2c.demand_mshr_misses::cpu1.dtb.walker 3 # number of demand (read+write) MSHR misses
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2015-12-05 01:11:25 +01:00
system.l2c.demand_mshr_misses::cpu1.inst 10154 # number of demand (read+write) MSHR misses
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2015-07-03 16:15:03 +02:00
system.l2c.overall_mshr_misses::cpu0.dtb.walker 4 # number of overall MSHR misses
2015-12-05 01:11:25 +01:00
system.l2c.overall_mshr_misses::cpu0.inst 7825 # number of overall MSHR misses
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2015-09-25 13:27:03 +02:00
system.l2c.overall_mshr_misses::cpu1.dtb.walker 3 # number of overall MSHR misses
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2015-12-05 01:11:25 +01:00
system.l2c.overall_mshr_misses::cpu1.inst 10154 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 67413 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 159071 # number of overall MSHR misses
2015-09-25 13:27:03 +02:00
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 5645 # number of ReadReq MSHR uncacheable
2015-12-05 01:11:25 +01:00
system.l2c.ReadReq_mshr_uncacheable::cpu0.data 14993 # number of ReadReq MSHR uncacheable
2015-09-25 13:27:03 +02:00
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 3377 # number of ReadReq MSHR uncacheable
2015-12-05 01:11:25 +01:00
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 16145 # number of ReadReq MSHR uncacheable
2015-07-03 16:15:03 +02:00
system.l2c.ReadReq_mshr_uncacheable::total 40160 # number of ReadReq MSHR uncacheable
2015-12-05 01:11:25 +01:00
system.l2c.WriteReq_mshr_uncacheable::cpu0.data 13371 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 14218 # number of WriteReq MSHR uncacheable
2015-07-03 16:15:03 +02:00
system.l2c.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable
2015-09-25 13:27:03 +02:00
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 5645 # number of overall MSHR uncacheable misses
2015-12-05 01:11:25 +01:00
system.l2c.overall_mshr_uncacheable_misses::cpu0.data 28364 # number of overall MSHR uncacheable misses
2015-09-25 13:27:03 +02:00
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 3377 # number of overall MSHR uncacheable misses
2015-12-05 01:11:25 +01:00
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 30363 # number of overall MSHR uncacheable misses
2015-07-03 16:15:03 +02:00
system.l2c.overall_mshr_uncacheable_misses::total 67749 # number of overall MSHR uncacheable misses
2015-11-06 09:26:50 +01:00
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 490500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 368500 # number of ReadReq MSHR miss cycles
2015-09-25 13:27:03 +02:00
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 123000 # number of ReadReq MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.l2c.ReadReq_mshr_miss_latency::total 982000 # number of ReadReq MSHR miss cycles
2015-12-05 01:11:25 +01:00
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 96874500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 97146000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 194020500 # number of UpgradeReq MSHR miss cycles
2015-09-25 13:27:03 +02:00
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 139000 # number of SCUpgradeReq MSHR miss cycles
2015-07-03 16:15:03 +02:00
system.l2c.SCUpgradeReq_mshr_miss_latency::total 139000 # number of SCUpgradeReq MSHR miss cycles
2015-12-05 01:11:25 +01:00
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7836730500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 7254787000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 15091517500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 945902500 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 1225723000 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total 2171625500 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 805831000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 681302500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 1487133500 # number of ReadSharedReq MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 490500 # number of demand (read+write) MSHR miss cycles
2015-12-05 01:11:25 +01:00
system.l2c.demand_mshr_miss_latency::cpu0.inst 945902500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 8642561500 # number of demand (read+write) MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 368500 # number of demand (read+write) MSHR miss cycles
2015-09-25 13:27:03 +02:00
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 123000 # number of demand (read+write) MSHR miss cycles
2015-12-05 01:11:25 +01:00
system.l2c.demand_mshr_miss_latency::cpu1.inst 1225723000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 7936089500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 18751258500 # number of demand (read+write) MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 490500 # number of overall MSHR miss cycles
2015-12-05 01:11:25 +01:00
system.l2c.overall_mshr_miss_latency::cpu0.inst 945902500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 8642561500 # number of overall MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 368500 # number of overall MSHR miss cycles
2015-09-25 13:27:03 +02:00
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 123000 # number of overall MSHR miss cycles
2015-12-05 01:11:25 +01:00
system.l2c.overall_mshr_miss_latency::cpu1.inst 1225723000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 7936089500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 18751258500 # number of overall MSHR miss cycles
2015-09-25 13:27:03 +02:00
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 643340500 # number of ReadReq MSHR uncacheable cycles
2015-12-05 01:11:25 +01:00
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2859676500 # number of ReadReq MSHR uncacheable cycles
2015-09-25 13:27:03 +02:00
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 386777500 # number of ReadReq MSHR uncacheable cycles
2015-12-05 01:11:25 +01:00
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3029132000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 6918926500 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2338041000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2434495500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 4772536500 # number of WriteReq MSHR uncacheable cycles
2015-09-25 13:27:03 +02:00
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 643340500 # number of overall MSHR uncacheable cycles
2015-12-05 01:11:25 +01:00
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5197717500 # number of overall MSHR uncacheable cycles
2015-09-25 13:27:03 +02:00
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 386777500 # number of overall MSHR uncacheable cycles
2015-12-05 01:11:25 +01:00
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5463627500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 11691463000 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000684 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000470 # mshr miss rate for ReadReq accesses
2015-11-06 09:26:50 +01:00
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000286 # mshr miss rate for ReadReq accesses
2015-12-05 01:11:25 +01:00
system.l2c.ReadReq_mshr_miss_rate::total 0.000426 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.990587 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.992764 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.991676 # mshr miss rate for UpgradeReq accesses
2015-09-25 13:27:03 +02:00
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
2014-11-12 15:05:25 +01:00
system.l2c.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2015-12-05 01:11:25 +01:00
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.452191 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.419099 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.435698 # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.009301 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.011876 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010599 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.025147 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.021347 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.023239 # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000684 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009301 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.180000 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000470 # mshr miss rate for demand accesses
2015-11-06 09:26:50 +01:00
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000286 # mshr miss rate for demand accesses
2015-12-05 01:11:25 +01:00
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011876 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.164296 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.062758 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000684 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009301 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.180000 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000470 # mshr miss rate for overall accesses
2015-11-06 09:26:50 +01:00
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000286 # mshr miss rate for overall accesses
2015-12-05 01:11:25 +01:00
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011876 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.164296 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.062758 # mshr miss rate for overall accesses
2015-11-06 09:26:50 +01:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 122625 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 122833.333333 # average ReadReq mshr miss latency
2015-09-25 13:27:03 +02:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average ReadReq mshr miss latency
2015-11-06 09:26:50 +01:00
system.l2c.ReadReq_avg_mshr_miss_latency::total 122750 # average ReadReq mshr miss latency
2015-12-05 01:11:25 +01:00
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70814.692982 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70806.122449 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70810.401460 # average UpgradeReq mshr miss latency
2015-09-25 13:27:03 +02:00
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 69500 # average SCUpgradeReq mshr miss latency
2015-07-03 16:15:03 +02:00
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency
2015-12-05 01:11:25 +01:00
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 116772.667670 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117387.576454 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 117067.460225 # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 120882.108626 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120713.314950 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 120786.779020 # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 122840.091463 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121422.651934 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 122186.632158 # average ReadSharedReq mshr miss latency
2015-11-06 09:26:50 +01:00
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 122625 # average overall mshr miss latency
2015-12-05 01:11:25 +01:00
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120882.108626 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 117312.938605 # average overall mshr miss latency
2015-11-06 09:26:50 +01:00
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 122833.333333 # average overall mshr miss latency
2015-09-25 13:27:03 +02:00
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average overall mshr miss latency
2015-12-05 01:11:25 +01:00
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120713.314950 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117723.428716 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 117879.805244 # average overall mshr miss latency
2015-11-06 09:26:50 +01:00
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 122625 # average overall mshr miss latency
2015-12-05 01:11:25 +01:00
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120882.108626 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 117312.938605 # average overall mshr miss latency
2015-11-06 09:26:50 +01:00
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 122833.333333 # average overall mshr miss latency
2015-09-25 13:27:03 +02:00
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average overall mshr miss latency
2015-12-05 01:11:25 +01:00
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120713.314950 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117723.428716 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 117879.805244 # average overall mshr miss latency
2015-09-25 13:27:03 +02:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113966.430469 # average ReadReq mshr uncacheable latency
2015-12-05 01:11:25 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190734.109251 # average ReadReq mshr uncacheable latency
2015-09-25 13:27:03 +02:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411 # average ReadReq mshr uncacheable latency
2015-12-05 01:11:25 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187620.439765 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 172284.026394 # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 174859.098048 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171226.297651 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172986.933198 # average WriteReq mshr uncacheable latency
2015-09-25 13:27:03 +02:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113966.430469 # average overall mshr uncacheable latency
2015-12-05 01:11:25 +01:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 183250.511211 # average overall mshr uncacheable latency
2015-09-25 13:27:03 +02:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411 # average overall mshr uncacheable latency
2015-12-05 01:11:25 +01:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 179943.599117 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 172570.266720 # average overall mshr uncacheable latency
2014-11-12 15:05:25 +01:00
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::ReadReq 40160 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.membus.trans_dist::ReadResp 70546 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::WriteReq 27589 # Transaction distribution
system.membus.trans_dist::WriteResp 27589 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.membus.trans_dist::WritebackDirty 117374 # Transaction distribution
2015-12-05 01:11:25 +01:00
system.membus.trans_dist::CleanEvict 6389 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4498 # Transaction distribution
2014-11-12 15:05:25 +01:00
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
2015-12-05 01:11:25 +01:00
system.membus.trans_dist::UpgradeResp 4500 # Transaction distribution
system.membus.trans_dist::ReadExReq 127155 # Transaction distribution
system.membus.trans_dist::ReadExResp 127155 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.membus.trans_dist::ReadSharedReq 30386 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 438813 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 546405 # Packet count per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108894 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 108894 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.membus.pkt_count::total 655299 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15301948 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 15465301 # Cumulative packet size per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.membus.pkt_size::total 17782421 # Cumulative packet size per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.membus.snoops 492 # Total snoops (count)
2015-12-05 01:11:25 +01:00
system.membus.snoop_fanout::samples 389996 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2015-12-05 01:11:25 +01:00
system.membus.snoop_fanout::1 389996 100.00% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2015-12-05 01:11:25 +01:00
system.membus.snoop_fanout::total 389996 # Request fanout histogram
system.membus.reqLayer0.occupancy 90452500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2015-03-02 11:04:20 +01:00
system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.membus.reqLayer2.occupancy 1723000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.membus.reqLayer5.occupancy 823109916 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.membus.respLayer2.occupancy 952195249 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.membus.respLayer3.occupancy 64063181 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-12-04 01:19:05 +01:00
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
2014-11-12 15:05:25 +01:00
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
2015-12-04 01:19:05 +01:00
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
2015-12-05 01:11:25 +01:00
system.toL2Bus.snoop_filter.tot_requests 5053996 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 2538070 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 38133 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2015-11-06 09:26:50 +01:00
system.toL2Bus.snoop_filter.tot_snoops 581 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 581 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2015-12-05 01:11:25 +01:00
system.toL2Bus.trans_dist::ReadReq 74719 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2295003 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution
2015-12-05 01:11:25 +01:00
system.toL2Bus.trans_dist::WritebackDirty 801245 # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean 1665046 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 134452 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 2763 # Transaction distribution
2014-11-12 15:05:25 +01:00
system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
2015-12-05 01:11:25 +01:00
system.toL2Bus.trans_dist::UpgradeResp 2765 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 295877 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 295877 # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq 1696350 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 523949 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
2015-12-05 01:11:25 +01:00
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5075755 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2574108 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18469 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 34870 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 7703202 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 215163192 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96418525 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26184 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 48936 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 311656837 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 176461 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 2781455 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.021257 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.144239 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2015-12-05 01:11:25 +01:00
system.toL2Bus.snoop_fanout::0 2722330 97.87% 97.87% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 59125 2.13% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
2015-12-05 01:11:25 +01:00
system.toL2Bus.snoop_fanout::total 2781455 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 4961451000 # Layer occupancy (ticks)
2015-11-06 09:26:50 +01:00
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.toL2Bus.snoopLayer0.occupancy 380876 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.toL2Bus.respLayer0.occupancy 2553547000 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.toL2Bus.respLayer1.occupancy 1275712000 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.toL2Bus.respLayer2.occupancy 11923000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.toL2Bus.respLayer3.occupancy 22636000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2013-01-07 19:05:52 +01:00
---------- End Simulation Statistics ----------