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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt

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tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
---------- Begin Simulation Statistics ----------
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
sim_seconds 2.904683 # Number of seconds simulated
sim_ticks 2904682547500 # Number of ticks simulated
final_tick 2904682547500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
host_inst_rate 744036 # Simulator instruction rate (inst/s)
host_op_rate 897074 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 19213049576 # Simulator tick rate (ticks/s)
host_mem_usage 562336 # Number of bytes of host memory used
host_seconds 151.18 # Real time elapsed on the host
sim_insts 112485415 # Number of instructions simulated
sim_ops 135622211 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 557732 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 4265248 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 631552 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 4773892 # Number of bytes read from this memory
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.bytes_read::total 10229960 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 557732 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 631552 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1189284 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 5300352 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.bytes_written::total 7636212 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 17168 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 67163 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 7 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 9868 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 74593 # Number of read requests responded to by this memory
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.num_reads::total 168816 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 82818 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.num_writes::total 123423 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 22 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 192011 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 1468404 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 154 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 217425 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 1643516 # Total read bandwidth from this memory (bytes/s)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.bw_read::total 3521886 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 192011 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 217425 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 409437 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1824761 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 6030 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.physmem.bw_write::realview.ide 798137 # Write bandwidth from this memory (bytes/s)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.bw_write::total 2628932 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1824761 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 192011 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 1474434 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 217425 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 1643519 # Total bandwidth to/from this memory (bytes/s)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.physmem.bw_total::realview.ide 798468 # Total bandwidth to/from this memory (bytes/s)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.bw_total::total 6150817 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 168816 # Number of read requests accepted
system.physmem.writeReqs 123423 # Number of write requests accepted
system.physmem.readBursts 168816 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 123423 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 10794880 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 9344 # Total number of bytes read from write queue
system.physmem.bytesWritten 7651200 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 10229960 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 7636212 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 3868 # Number of DRAM write bursts merged with an existing one
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.physmem.neitherReadNorWriteReqs 4511 # Number of requests that are neither read nor write
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.perBankRdBursts::0 9768 # Per bank write bursts
system.physmem.perBankRdBursts::1 9653 # Per bank write bursts
system.physmem.perBankRdBursts::2 10324 # Per bank write bursts
system.physmem.perBankRdBursts::3 9994 # Per bank write bursts
system.physmem.perBankRdBursts::4 18675 # Per bank write bursts
system.physmem.perBankRdBursts::5 10148 # Per bank write bursts
system.physmem.perBankRdBursts::6 10372 # Per bank write bursts
system.physmem.perBankRdBursts::7 10429 # Per bank write bursts
system.physmem.perBankRdBursts::8 9938 # Per bank write bursts
system.physmem.perBankRdBursts::9 10451 # Per bank write bursts
system.physmem.perBankRdBursts::10 9811 # Per bank write bursts
system.physmem.perBankRdBursts::11 9561 # Per bank write bursts
system.physmem.perBankRdBursts::12 9986 # Per bank write bursts
system.physmem.perBankRdBursts::13 9803 # Per bank write bursts
system.physmem.perBankRdBursts::14 9966 # Per bank write bursts
system.physmem.perBankRdBursts::15 9791 # Per bank write bursts
system.physmem.perBankWrBursts::0 7253 # Per bank write bursts
system.physmem.perBankWrBursts::1 7191 # Per bank write bursts
system.physmem.perBankWrBursts::2 8157 # Per bank write bursts
system.physmem.perBankWrBursts::3 7614 # Per bank write bursts
system.physmem.perBankWrBursts::4 7092 # Per bank write bursts
system.physmem.perBankWrBursts::5 7380 # Per bank write bursts
system.physmem.perBankWrBursts::6 7560 # Per bank write bursts
system.physmem.perBankWrBursts::7 7725 # Per bank write bursts
system.physmem.perBankWrBursts::8 7575 # Per bank write bursts
system.physmem.perBankWrBursts::9 8007 # Per bank write bursts
system.physmem.perBankWrBursts::10 7415 # Per bank write bursts
system.physmem.perBankWrBursts::11 7436 # Per bank write bursts
system.physmem.perBankWrBursts::12 7462 # Per bank write bursts
system.physmem.perBankWrBursts::13 7248 # Per bank write bursts
system.physmem.perBankWrBursts::14 7309 # Per bank write bursts
system.physmem.perBankWrBursts::15 7126 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.numWrRetry 3 # Number of times write queue was full causing retry
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.physmem.totGap 2904682181000 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.readPktSize::2 9558 # Read request sizes (log2)
system.physmem.readPktSize::3 14 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.readPktSize::6 159244 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.writePktSize::2 4381 # Write request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.writePktSize::6 119042 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 167845 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 557 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 256 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.wrQLenPdf::0 202 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 194 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 191 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 187 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 185 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 183 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 181 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 176 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 171 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 168 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 164 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 163 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 162 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 160 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 157 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 2142 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 2709 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5948 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 6092 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 6127 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6689 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 6919 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 7493 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 7962 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 8752 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 8130 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 7631 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 7029 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 6807 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 6096 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 5937 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 5907 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 5856 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 187 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 183 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 163 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 149 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 137 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 142 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 148 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 120 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 114 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 104 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 120 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 124 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 112 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 121 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 109 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 86 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 76 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 59 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 40 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 37 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 38 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 34 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 29 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 25 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 27 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 18 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 12 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.physmem.bytesPerActivate::samples 58500 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 315.315419 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 184.678002 # Bytes accessed per row activation
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.physmem.bytesPerActivate::stdev 335.865134 # Bytes accessed per row activation
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.physmem.bytesPerActivate::0-127 21233 36.30% 36.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 14762 25.23% 61.53% # Bytes accessed per row activation
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.physmem.bytesPerActivate::256-383 5741 9.81% 71.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3177 5.43% 76.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2294 3.92% 80.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1562 2.67% 83.37% # Bytes accessed per row activation
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.physmem.bytesPerActivate::768-895 1019 1.74% 85.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1097 1.88% 86.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 7615 13.02% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 58500 # Bytes accessed per row activation
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.rdPerTurnAround::samples 5866 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 28.752472 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 562.127013 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 5865 99.98% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 5866 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 5866 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 20.380157 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.599784 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 12.515949 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3 16 0.27% 0.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7 10 0.17% 0.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11 13 0.22% 0.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15 18 0.31% 0.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 4930 84.04% 85.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 59 1.01% 86.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 57 0.97% 86.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 249 4.24% 91.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 210 3.58% 94.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 20 0.34% 95.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 11 0.19% 95.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 8 0.14% 95.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 30 0.51% 95.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 5 0.09% 96.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 4 0.07% 96.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 3 0.05% 96.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 157 2.68% 98.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 5 0.09% 98.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 4 0.07% 99.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 3 0.05% 99.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 19 0.32% 99.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 1 0.02% 99.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 6 0.10% 99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 2 0.03% 99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111 6 0.10% 99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 6 0.10% 99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119 3 0.05% 99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 2 0.03% 99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 7 0.12% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 5866 # Writes before turning the bus around for reads
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.physmem.totQLat 1486855250 # Total ticks spent queuing
system.physmem.totMemAccLat 4649417750 # Total ticks spent from burst creation until serviced by the DRAM
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.totBusLat 843350000 # Total ticks spent in databus transfers
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.physmem.avgQLat 8815.17 # Average queueing delay per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.physmem.avgMemAccLat 27565.17 # Average memory access latency per DRAM burst
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.avgRdBW 3.72 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.63 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 2.63 # Average system write bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.busUtil 0.05 # Data bus utilization in percentage
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 11.56 # Average write queue length when enqueuing
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.physmem.readRowHits 139006 # Number of row buffer hits during reads
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.writeRowHits 90713 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.41 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 75.88 # Row buffer hit rate for writes
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.physmem.avgGap 9939406.38 # Average gap between requests
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.pageHitRate 79.70 # Row buffer hit rate, read and write combined
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.physmem.memoryStateTime::IDLE 2756105768250 # Time in different power states
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.memoryStateTime::REF 96993520000 # Time in different power states
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.physmem.memoryStateTime::ACT 51577106750 # Time in different power states
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.physmem.actEnergy::0 224736120 # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1 217523880 # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0 122623875 # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1 118688625 # Energy for precharge commands per rank (pJ)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.readEnergy::0 697031400 # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1 618579000 # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0 388618560 # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1 386065440 # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0 189719325120 # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1 189719325120 # Energy for refresh commands per rank (pJ)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.physmem.actBackEnergy::0 86946648885 # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1 86006740545 # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0 1666536838500 # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1 1667361319500 # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0 1944635822460 # Total energy per rank (pJ)
system.physmem.totalEnergy::1 1944428242110 # Total energy per rank (pJ)
system.physmem.averagePower::0 669.484503 # Core power per rank (mW)
system.physmem.averagePower::1 669.413038 # Core power per rank (mW)
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.dtb.read_hits 12289553 # DTB read hits
system.cpu0.dtb.read_misses 5977 # DTB read misses
system.cpu0.dtb.write_hits 9834643 # DTB write hits
system.cpu0.dtb.write_misses 1047 # DTB write misses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.dtb.flush_tlb 2938 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 467 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 4657 # Number of entries that have been flushed from TLB
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.dtb.prefetch_faults 865 # Number of TLB faults due to prefetch
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.dtb.perms_faults 233 # Number of TLB faults due to permissions restrictions
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.dtb.read_accesses 12295530 # DTB read accesses
system.cpu0.dtb.write_accesses 9835690 # DTB write accesses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.dtb.hits 22124196 # DTB hits
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.dtb.misses 7024 # DTB misses
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.dtb.accesses 22131220 # DTB accesses
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.itb.inst_hits 58032770 # ITB inst hits
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.itb.inst_misses 3465 # ITB inst misses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.itb.flush_tlb 2938 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 467 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 2699 # Number of entries that have been flushed from TLB
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.itb.inst_accesses 58036235 # ITB inst accesses
system.cpu0.itb.hits 58032770 # DTB hits
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.itb.misses 3465 # DTB misses
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.itb.accesses 58036235 # DTB accesses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.numCycles 2905319694 # number of cpu cycles simulated
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.committedInsts 56513131 # Number of instructions committed
system.cpu0.committedOps 68067849 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 60172046 # Number of integer alu accesses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.num_fp_alu_accesses 6287 # Number of float alu accesses
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.num_func_calls 4924583 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 7649378 # number of instructions that are conditional controls
system.cpu0.num_int_insts 60172046 # number of integer instructions
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.num_fp_insts 6287 # number of float instructions
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.num_int_register_reads 109432768 # number of times the integer registers were read
system.cpu0.num_int_register_writes 41532346 # number of times the integer registers were written
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.num_fp_register_reads 4990 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 1298 # number of times the floating registers were written
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.num_cc_register_reads 245794871 # number of times the CC registers were read
system.cpu0.num_cc_register_writes 26123486 # number of times the CC registers were written
system.cpu0.num_mem_refs 22763364 # number of memory refs
system.cpu0.num_load_insts 12450622 # Number of load instructions
system.cpu0.num_store_insts 10312742 # Number of store instructions
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.num_idle_cycles 2685746001.120693 # Number of idle cycles
system.cpu0.num_busy_cycles 219573692.879307 # Number of busy cycles
system.cpu0.not_idle_fraction 0.075576 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.924424 # Percentage of idle cycles
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.Branches 12983457 # Number of branches fetched
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.op_class::No_OpClass 2204 0.00% 0.00% # Class of executed instruction
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.op_class::IntAlu 46789630 67.21% 67.21% # Class of executed instruction
system.cpu0.op_class::IntMult 58620 0.08% 67.30% # Class of executed instruction
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.op_class::IntDiv 0 0.00% 67.30% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 67.30% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 67.30% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 67.30% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 67.30% # Class of executed instruction
system.cpu0.op_class::FloatDiv 0 0.00% 67.30% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 67.30% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 67.30% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 67.30% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 67.30% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 67.30% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 67.30% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 67.30% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 67.30% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 67.30% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 67.30% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.30% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 67.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 4273 0.01% 67.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 67.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.30% # Class of executed instruction
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.op_class::MemRead 12450622 17.88% 85.19% # Class of executed instruction
system.cpu0.op_class::MemWrite 10312742 14.81% 100.00% # Class of executed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.op_class::total 69618091 # Class of executed instruction
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.kern.inst.quiesce 3031 # number of quiesce instructions executed
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.tags.replacements 822992 # number of replacements
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.dcache.tags.tagsinuse 511.850755 # Cycle average of tags in use
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.tags.total_refs 43241503 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 823504 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 52.509160 # Average number of references to valid blocks.
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.dcache.tags.warmup_cycle 876905250 # Cycle when the warmup percentage was hit.
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.tags.occ_blocks::cpu0.data 320.068917 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 191.781838 # Average occupied blocks per requestor
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.625135 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.374574 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999709 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.tags.tag_accesses 177151535 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 177151535 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 11581583 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 11533865 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 23115448 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 9437909 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 9389790 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 18827699 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 199753 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 192262 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 392015 # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 227025 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 216269 # number of LoadLockedReq hits
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.dcache.LoadLockedReq_hits::total 443294 # number of LoadLockedReq hits
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 235239 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 225055 # number of StoreCondReq hits
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.dcache.StoreCondReq_hits::total 460294 # number of StoreCondReq hits
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.demand_hits::cpu0.data 21019492 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 20923655 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 41943147 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 21219245 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 21115917 # number of overall hits
system.cpu0.dcache.overall_hits::total 42335162 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 197297 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 205526 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 402823 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 150193 # number of WriteReq misses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.dcache.WriteReq_misses::cpu1.data 148466 # number of WriteReq misses
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.WriteReq_misses::total 298659 # number of WriteReq misses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 58530 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 60464 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 118994 # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 11127 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 11645 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 22772 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.demand_misses::cpu0.data 347490 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 353992 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 701482 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 406020 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 414456 # number of overall misses
system.cpu0.dcache.overall_misses::total 820476 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2868020500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3066163250 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 5934183750 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5744459123 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 6031837843 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 11776296966 # number of WriteReq miss cycles
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 135157750 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 145057500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 280215250 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 52002 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 52002 # number of StoreCondReq miss cycles
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.demand_miss_latency::cpu0.data 8612479623 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 9098001093 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 17710480716 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 8612479623 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 9098001093 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 17710480716 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 11778880 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 11739391 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 23518271 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 9588102 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 9538256 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 19126358 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 258283 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 252726 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 511009 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 238152 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 227914 # number of LoadLockedReq accesses(hits+misses)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.dcache.LoadLockedReq_accesses::total 466066 # number of LoadLockedReq accesses(hits+misses)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 235241 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 225055 # number of StoreCondReq accesses(hits+misses)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.dcache.StoreCondReq_accesses::total 460296 # number of StoreCondReq accesses(hits+misses)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.demand_accesses::cpu0.data 21366982 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 21277647 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 42644629 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 21625265 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 21530373 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 43155638 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016750 # miss rate for ReadReq accesses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.017507 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.017128 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.015665 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015565 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.015615 # miss rate for WriteReq accesses
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.226612 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.239247 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.232861 # miss rate for SoftPFReq accesses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046722 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.051094 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048860 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000009 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016263 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.016637 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.016449 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018775 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.019250 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.019012 # miss rate for overall accesses
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14536.564165 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14918.614920 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14731.491871 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38247.182778 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40627.738627 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 39430.577903 # average WriteReq miss latency
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12146.827537 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12456.633748 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12305.254260 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26001 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26001 # average StoreCondReq miss latency
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24784.827255 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25701.148876 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 25247.234734 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21211.959073 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 21951.669400 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 21585.617027 # average overall miss latency
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.dcache.blocked_cycles::no_mshrs 38 # number of cycles access was blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 2 # average number of cycles each access was blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.writebacks::writebacks 686960 # number of writebacks
system.cpu0.dcache.writebacks::total 686960 # number of writebacks
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 287 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 328 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 615 # number of ReadReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 7032 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 7182 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14214 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 287 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data 328 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 615 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 287 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data 328 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 615 # number of overall MSHR hits
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 197010 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 205198 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 402208 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 150193 # number of WriteReq MSHR misses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 148466 # number of WriteReq MSHR misses
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.WriteReq_mshr_misses::total 298659 # number of WriteReq MSHR misses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 57639 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 59222 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 116861 # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 4095 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 4463 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8558 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.demand_mshr_misses::cpu0.data 347203 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 353664 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 700867 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 404842 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 412886 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 817728 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2467868750 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2647702500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5115571250 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5416592829 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5704580119 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11121172948 # number of WriteReq MSHR miss cycles
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 696038250 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 742244000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1438282250 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 48274750 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 52699750 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 100974500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 47998 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 47998 # number of StoreCondReq MSHR miss cycles
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7884461579 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 8352282619 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 16236744198 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8580499829 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 9094526619 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 17675026448 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2688395000 # number of ReadReq MSHR uncacheable cycles
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3103027500 # number of ReadReq MSHR uncacheable cycles
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5791422500 # number of ReadReq MSHR uncacheable cycles
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2165315000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2264487500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4429802500 # number of WriteReq MSHR uncacheable cycles
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4853710000 # number of overall MSHR uncacheable cycles
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5367515000 # number of overall MSHR uncacheable cycles
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10221225000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016726 # mshr miss rate for ReadReq accesses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.017479 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017102 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015665 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015565 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015615 # mshr miss rate for WriteReq accesses
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.223162 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.234333 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.228687 # mshr miss rate for SoftPFReq accesses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017195 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019582 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018362 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000009 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016250 # mshr miss rate for demand accesses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016621 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.016435 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018721 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.019177 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.018948 # mshr miss rate for overall accesses
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12526.616669 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12903.159388 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12718.720786 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36064.216235 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38423.478231 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37237.026000 # average WriteReq mshr miss latency
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12075.821059 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12533.247780 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12307.632572 # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11788.705739 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11808.144746 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11798.843188 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23999 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23999 # average StoreCondReq mshr miss latency
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22708.506490 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23616.434296 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23166.655297 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21194.687876 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22026.725583 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21614.799112 # average overall mshr miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu0.icache.tags.replacements 1698167 # number of replacements
system.cpu0.icache.tags.tagsinuse 510.774848 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 113885267 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 1698679 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 67.043430 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 25359588250 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 419.089773 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 91.685075 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.818535 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.179072 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.997607 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 117282637 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 117282637 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 57188138 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 56697129 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 113885267 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 57188138 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 56697129 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 113885267 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 57188138 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 56697129 # number of overall hits
system.cpu0.icache.overall_hits::total 113885267 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 844632 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 854053 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 1698685 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 844632 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 854053 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 1698685 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 844632 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 854053 # number of overall misses
system.cpu0.icache.overall_misses::total 1698685 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11522232749 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 11755811000 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 23278043749 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 11522232749 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 11755811000 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 23278043749 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 11522232749 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 11755811000 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 23278043749 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 58032770 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 57551182 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 115583952 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 58032770 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 57551182 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 115583952 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 58032770 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 57551182 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 115583952 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014554 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014840 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.014697 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014554 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014840 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.014697 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014554 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014840 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.014697 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13641.719410 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13764.732400 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13703.567023 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13641.719410 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13764.732400 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13703.567023 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13641.719410 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13764.732400 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13703.567023 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 844632 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 854053 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 1698685 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 844632 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 854053 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 1698685 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 844632 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 854053 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 1698685 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9830027251 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 10044094000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 19874121251 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9830027251 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 10044094000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 19874121251 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9830027251 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 10044094000 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 19874121251 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 597905000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 597905000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 597905000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 597905000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014554 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014840 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014697 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014554 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014840 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.014697 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014554 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014840 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.014697 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11638.236831 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11760.504325 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11699.709629 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11638.236831 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11760.504325 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11699.709629 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11638.236831 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11760.504325 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11699.709629 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu1.dtb.read_hits 12236392 # DTB read hits
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu1.dtb.read_misses 5657 # DTB read misses
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu1.dtb.write_hits 9775692 # DTB write hits
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu1.dtb.write_misses 790 # DTB write misses
system.cpu1.dtb.flush_tlb 2934 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 450 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 4044 # Number of entries that have been flushed from TLB
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu1.dtb.prefetch_faults 918 # Number of TLB faults due to prefetch
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu1.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu1.dtb.read_accesses 12242049 # DTB read accesses
system.cpu1.dtb.write_accesses 9776482 # DTB write accesses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu1.dtb.hits 22012084 # DTB hits
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu1.dtb.misses 6447 # DTB misses
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu1.dtb.accesses 22018531 # DTB accesses
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu1.itb.inst_hits 57551182 # ITB inst hits
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu1.itb.inst_misses 3277 # ITB inst misses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu1.itb.flush_tlb 2934 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 450 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 2396 # Number of entries that have been flushed from TLB
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu1.itb.inst_accesses 57554459 # ITB inst accesses
system.cpu1.itb.hits 57551182 # DTB hits
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu1.itb.misses 3277 # DTB misses
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu1.itb.accesses 57554459 # DTB accesses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu1.numCycles 2904045401 # number of cpu cycles simulated
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu1.committedInsts 55972284 # Number of instructions committed
system.cpu1.committedOps 67554362 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 59752131 # Number of integer alu accesses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu1.num_fp_alu_accesses 5003 # Number of float alu accesses
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu1.num_func_calls 4972365 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 7584533 # number of instructions that are conditional controls
system.cpu1.num_int_insts 59752131 # number of integer instructions
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu1.num_fp_insts 5003 # number of float instructions
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu1.num_int_register_reads 108688988 # number of times the integer registers were read
system.cpu1.num_int_register_writes 41135378 # number of times the integer registers were written
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu1.num_fp_register_reads 3588 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 1418 # number of times the floating registers were written
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu1.num_cc_register_reads 244071190 # number of times the CC registers were read
system.cpu1.num_cc_register_writes 25783552 # number of times the CC registers were written
system.cpu1.num_mem_refs 22653716 # number of memory refs
system.cpu1.num_load_insts 12397911 # Number of load instructions
system.cpu1.num_store_insts 10255805 # Number of store instructions
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu1.num_idle_cycles 2693922745.089012 # Number of idle cycles
system.cpu1.num_busy_cycles 210122655.910988 # Number of busy cycles
system.cpu1.not_idle_fraction 0.072355 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.927645 # Percentage of idle cycles
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu1.Branches 12941389 # Number of branches fetched
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu1.op_class::No_OpClass 133 0.00% 0.00% # Class of executed instruction
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu1.op_class::IntAlu 46411475 67.14% 67.14% # Class of executed instruction
system.cpu1.op_class::IntMult 56055 0.08% 67.22% # Class of executed instruction
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu1.op_class::IntDiv 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::FloatDiv 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc 4164 0.01% 67.23% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 67.23% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.23% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.23% # Class of executed instruction
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu1.op_class::MemRead 12397911 17.94% 85.16% # Class of executed instruction
system.cpu1.op_class::MemWrite 10255805 14.84% 100.00% # Class of executed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu1.op_class::total 69125543 # Class of executed instruction
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.iobus.trans_dist::ReadReq 30195 # Transaction distribution
system.iobus.trans_dist::ReadResp 30195 # Transaction distribution
system.iobus.trans_dist::WriteReq 59038 # Transaction distribution
system.iobus.trans_dist::WriteResp 59038 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 326584349 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 36804759 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iocache.tags.replacements 36424 # number of replacements
system.iocache.tags.tagsinuse 1.083103 # Cycle average of tags in use
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 309429741000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide 1.083103 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.067694 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.067694 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 328122 # Number of tag accesses
system.iocache.tags.data_accesses 328122 # Number of data accesses
system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits
system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses
system.iocache.ReadReq_misses::total 234 # number of ReadReq misses
system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses
system.iocache.demand_misses::total 234 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 234 # number of overall misses
system.iocache.overall_misses::total 234 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide 28034377 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 28034377 # number of ReadReq miss cycles
system.iocache.demand_miss_latency::realview.ide 28034377 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 28034377 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 28034377 # number of overall miss cycles
system.iocache.overall_miss_latency::total 28034377 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 119805.029915 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 119805.029915 # average ReadReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 119805.029915 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 119805.029915 # average overall miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iocache.fast_writes 36224 # number of fast writes performed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.iocache.cache_copies 0 # number of cache copies performed
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide 15865377 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 15865377 # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2203719731 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2203719731 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 15865377 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 15865377 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 15865377 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 15865377 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67800.756410 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 67800.756410 # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.l2c.tags.replacements 89435 # number of replacements
system.l2c.tags.tagsinuse 64928.071220 # Cycle average of tags in use
system.l2c.tags.total_refs 2766032 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 154676 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 17.882748 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 50556.019197 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.943993 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000464 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 3889.866505 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 2064.899938 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 4.768384 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 5760.330465 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 2651.242275 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.771424 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000014 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.059355 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.031508 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000073 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.087896 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.040455 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.990724 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 65236 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 2127 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 6815 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 56246 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.995422 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 26292076 # Number of tag accesses
system.l2c.tags.data_accesses 26292076 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 6208 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 3383 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 836467 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 253621 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 5323 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 2799 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 844177 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 261864 # number of ReadReq hits
system.l2c.ReadReq_hits::total 2213842 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 686960 # number of Writeback hits
system.l2c.Writeback_hits::total 686960 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 11 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 12 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 23 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 86549 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 78519 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 165068 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 6208 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 3383 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 836467 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 340170 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 5323 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 2799 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 844177 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 340383 # number of demand (read+write) hits
system.l2c.demand_hits::total 2378910 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 6208 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 3383 # number of overall hits
system.l2c.overall_hits::cpu0.inst 836467 # number of overall hits
system.l2c.overall_hits::cpu0.data 340170 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 5323 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 2799 # number of overall hits
system.l2c.overall_hits::cpu1.inst 844177 # number of overall hits
system.l2c.overall_hits::cpu1.data 340383 # number of overall hits
system.l2c.overall_hits::total 2378910 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst 8151 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 5123 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 7 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 9868 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 7019 # number of ReadReq misses
system.l2c.ReadReq_misses::total 30170 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 1297 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 1431 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 2728 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 2 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 62336 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 68504 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 130840 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 8151 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 67459 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 7 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 9868 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 75523 # number of demand (read+write) misses
system.l2c.demand_misses::total 161010 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses
system.l2c.overall_misses::cpu0.inst 8151 # number of overall misses
system.l2c.overall_misses::cpu0.data 67459 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 7 # number of overall misses
system.l2c.overall_misses::cpu1.inst 9868 # number of overall misses
system.l2c.overall_misses::cpu1.data 75523 # number of overall misses
system.l2c.overall_misses::total 161010 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 74500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 75000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst 591607750 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 390910500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 566500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 717676500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 528864500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 2229775250 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 232490 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 231490 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 463980 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 45998 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 45998 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 4342118150 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 4712358069 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 9054476219 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 74500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 75000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 591607750 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 4733028650 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 566500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 717676500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 5241222569 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 11284251469 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 74500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 75000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 591607750 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 4733028650 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 566500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 717676500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 5241222569 # number of overall miss cycles
system.l2c.overall_miss_latency::total 11284251469 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 6209 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 3384 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 844618 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 258744 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 5330 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 2799 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 854045 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 268883 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2244012 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 686960 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 686960 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 1308 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 1443 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 2751 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 2 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 148885 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 147023 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 295908 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 6209 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 3384 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 844618 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 407629 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 5330 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 2799 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 854045 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 415906 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2539920 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 6209 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 3384 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 844618 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 407629 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 5330 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 2799 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 854045 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 415906 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2539920 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000161 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000296 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.009651 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.019799 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.001313 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.011554 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.026104 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.013445 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.991590 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.991684 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.991639 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.418686 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.465941 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.442164 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000161 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000296 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.009651 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.165491 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.001313 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.011554 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.181587 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.063392 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000161 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000296 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.009651 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.165491 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.001313 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.011554 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.181587 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.063392 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 74500 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 72581.002331 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 76304.997072 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 80928.571429 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72727.655047 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 75347.556632 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 73907.035134 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 179.252120 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 161.767994 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 170.080645 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 22999 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 22999 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 69656.669501 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68789.531546 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 69202.661411 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 74500 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 72581.002331 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 70161.559614 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 80928.571429 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 72727.655047 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 69399.025052 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 70084.165387 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 74500 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 72581.002331 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 70161.559614 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 80928.571429 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 72727.655047 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 69399.025052 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 70084.165387 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 82818 # number of writebacks
system.l2c.writebacks::total 82818 # number of writebacks
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst 8151 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data 5123 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 7 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst 9868 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 7019 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 30170 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 1297 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 1431 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 2728 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 2 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 62336 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 68504 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 130840 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker 1 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst 8151 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 67459 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 7 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 9868 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 75523 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 161010 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 8151 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 67459 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 7 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 9868 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 75523 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 161010 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 62500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 62500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 488588750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 327005500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 479000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 592914000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 441224000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 1850336250 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 12974797 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 14335431 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 27310228 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 20002 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3544228350 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3834786931 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 7379015281 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 62500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 488588750 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 3871233850 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 479000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 592914000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 4276010931 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 9229351531 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 62500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 488588750 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 3871233850 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 479000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 592914000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 4276010931 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 9229351531 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 474215000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2495734500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2890261000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 5860210500 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1979887500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2118425500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 4098313000 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 474215000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4475622000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5008686500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 9958523500 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000161 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000296 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.009651 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.019799 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.001313 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011554 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.026104 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.013445 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.991590 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991684 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.991639 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.418686 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.465941 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.442164 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000161 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000296 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009651 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.165491 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.001313 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011554 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.181587 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.063392 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000161 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000296 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009651 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.165491 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001313 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011554 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.181587 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.063392 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 62500 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59942.185008 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63830.860824 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68428.571429 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60084.515606 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62861.376264 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 61330.336427 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10003.698535 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10017.771488 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10011.080645 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56856.845964 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55979.022115 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 56397.243053 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 62500 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59942.185008 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57386.469559 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68428.571429 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60084.515606 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56618.658303 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 57321.604441 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62500 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59942.185008 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57386.469559 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68428.571429 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60084.515606 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56618.658303 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 57321.604441 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 70576 # Transaction distribution
system.membus.trans_dist::ReadResp 70576 # Transaction distribution
system.membus.trans_dist::WriteReq 27613 # Transaction distribution
system.membus.trans_dist::WriteResp 27613 # Transaction distribution
system.membus.trans_dist::Writeback 82818 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4509 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
system.membus.trans_dist::UpgradeResp 4511 # Transaction distribution
system.membus.trans_dist::ReadExReq 129059 # Transaction distribution
system.membus.trans_dist::ReadExResp 129059 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 438204 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 545868 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 618565 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15546876 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 15710301 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 18029597 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 219 # Total snoops (count)
system.membus.snoop_fanout::samples 283019 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 283019 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 283019 # Request fanout histogram
system.membus.reqLayer0.occupancy 87171000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 1736000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 1336695000 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 1640329489 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
system.membus.respLayer3.occupancy 38340241 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.toL2Bus.trans_dist::ReadReq 2301469 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2301454 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 27613 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 27613 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 686960 # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq 36226 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 2751 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 2753 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 295908 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 295908 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3415392 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2457281 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18122 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 34351 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 5925146 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108750520 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96868901 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 24732 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 46156 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 205690309 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 53730 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 3283144 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 5.011105 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.104794 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::5 3246684 98.89% 98.89% # Request fanout histogram
system.toL2Bus.snoop_fanout::6 36460 1.11% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 3283144 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 4418882248 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 985500 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 7658490749 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 3782924511 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 11939000 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 22834207 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
---------- End Simulation Statistics ----------
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