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gem5/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt

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add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
---------- Begin Simulation Statistics ----------
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
sim_seconds 0.200409 # Number of seconds simulated
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
sim_ticks 200409293000 # Number of ticks simulated
final_tick 4321201686500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
host_inst_rate 19440889 # Simulator instruction rate (inst/s)
host_op_rate 19440880 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 7408936081 # Simulator tick rate (ticks/s)
host_mem_usage 472492 # Number of bytes of host memory used
host_seconds 27.05 # Real time elapsed on the host
sim_insts 525869186 # Number of instructions simulated
sim_ops 525869186 # Number of ops (including micro ops) simulated
testsys.physmem.bytes_read::cpu.inst 81048564 # Number of bytes read from this memory
testsys.physmem.bytes_read::cpu.data 27826180 # Number of bytes read from this memory
testsys.physmem.bytes_read::tsunami.ethernet 51169128 # Number of bytes read from this memory
testsys.physmem.bytes_read::total 160043872 # Number of bytes read from this memory
testsys.physmem.bytes_inst_read::cpu.inst 81048564 # Number of instructions bytes read from this memory
testsys.physmem.bytes_inst_read::total 81048564 # Number of instructions bytes read from this memory
testsys.physmem.bytes_written::cpu.data 16606324 # Number of bytes written to this memory
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
testsys.physmem.bytes_written::tsunami.ethernet 902 # Number of bytes written to this memory
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.physmem.bytes_written::total 16607226 # Number of bytes written to this memory
testsys.physmem.num_reads::cpu.inst 20262141 # Number of read requests responded to by this memory
testsys.physmem.num_reads::cpu.data 3842564 # Number of read requests responded to by this memory
testsys.physmem.num_reads::tsunami.ethernet 2132029 # Number of read requests responded to by this memory
testsys.physmem.num_reads::total 26236734 # Number of read requests responded to by this memory
testsys.physmem.num_writes::cpu.data 2258349 # Number of write requests responded to by this memory
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
testsys.physmem.num_writes::tsunami.ethernet 31 # Number of write requests responded to by this memory
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.physmem.num_writes::total 2258380 # Number of write requests responded to by this memory
testsys.physmem.bw_read::cpu.inst 404415198 # Total read bandwidth from this memory (bytes/s)
testsys.physmem.bw_read::cpu.data 138846755 # Total read bandwidth from this memory (bytes/s)
testsys.physmem.bw_read::tsunami.ethernet 255323130 # Total read bandwidth from this memory (bytes/s)
testsys.physmem.bw_read::total 798585084 # Total read bandwidth from this memory (bytes/s)
testsys.physmem.bw_inst_read::cpu.inst 404415198 # Instruction read bandwidth from this memory (bytes/s)
testsys.physmem.bw_inst_read::total 404415198 # Instruction read bandwidth from this memory (bytes/s)
testsys.physmem.bw_write::cpu.data 82862046 # Write bandwidth from this memory (bytes/s)
Stats: Update stats for twosys-tsunami after setting CPU clock This patch updates the stats to reflect the addition of a clock period other than the default 1 Tick.
2012-09-25 00:03:43 +02:00
testsys.physmem.bw_write::tsunami.ethernet 4501 # Write bandwidth from this memory (bytes/s)
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.physmem.bw_write::total 82866547 # Write bandwidth from this memory (bytes/s)
testsys.physmem.bw_total::cpu.inst 404415198 # Total bandwidth to/from this memory (bytes/s)
testsys.physmem.bw_total::cpu.data 221708801 # Total bandwidth to/from this memory (bytes/s)
testsys.physmem.bw_total::tsunami.ethernet 255327631 # Total bandwidth to/from this memory (bytes/s)
testsys.physmem.bw_total::total 881451630 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
testsys.physmem.readReqs 0 # Total number of read requests seen
testsys.physmem.writeReqs 0 # Total number of write requests seen
testsys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
testsys.physmem.bytesRead 0 # Total number of bytes read from memory
testsys.physmem.bytesWritten 0 # Total number of bytes written to memory
testsys.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
testsys.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
testsys.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
testsys.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
testsys.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis
testsys.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
testsys.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
testsys.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
testsys.physmem.totGap 0 # Total gap between requests
testsys.physmem.readPktSize::0 0 # Categorize read packet sizes
testsys.physmem.readPktSize::1 0 # Categorize read packet sizes
testsys.physmem.readPktSize::2 0 # Categorize read packet sizes
testsys.physmem.readPktSize::3 0 # Categorize read packet sizes
testsys.physmem.readPktSize::4 0 # Categorize read packet sizes
testsys.physmem.readPktSize::5 0 # Categorize read packet sizes
testsys.physmem.readPktSize::6 0 # Categorize read packet sizes
testsys.physmem.readPktSize::7 0 # Categorize read packet sizes
testsys.physmem.readPktSize::8 0 # Categorize read packet sizes
testsys.physmem.writePktSize::0 0 # categorize write packet sizes
testsys.physmem.writePktSize::1 0 # categorize write packet sizes
testsys.physmem.writePktSize::2 0 # categorize write packet sizes
testsys.physmem.writePktSize::3 0 # categorize write packet sizes
testsys.physmem.writePktSize::4 0 # categorize write packet sizes
testsys.physmem.writePktSize::5 0 # categorize write packet sizes
testsys.physmem.writePktSize::6 0 # categorize write packet sizes
testsys.physmem.writePktSize::7 0 # categorize write packet sizes
testsys.physmem.writePktSize::8 0 # categorize write packet sizes
testsys.physmem.neitherpktsize::0 0 # categorize neither packet sizes
testsys.physmem.neitherpktsize::1 0 # categorize neither packet sizes
testsys.physmem.neitherpktsize::2 0 # categorize neither packet sizes
testsys.physmem.neitherpktsize::3 0 # categorize neither packet sizes
testsys.physmem.neitherpktsize::4 0 # categorize neither packet sizes
testsys.physmem.neitherpktsize::5 0 # categorize neither packet sizes
testsys.physmem.neitherpktsize::6 0 # categorize neither packet sizes
testsys.physmem.neitherpktsize::7 0 # categorize neither packet sizes
testsys.physmem.neitherpktsize::8 0 # categorize neither packet sizes
testsys.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
testsys.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
testsys.physmem.totQLat 0 # Total cycles spent in queuing delays
testsys.physmem.totMemAccLat 0 # Sum of mem lat for all requests
testsys.physmem.totBusLat 0 # Total cycles spent in databus access
testsys.physmem.totBankLat 0 # Total cycles spent in bank access
testsys.physmem.avgQLat nan # Average queueing delay per request
testsys.physmem.avgBankLat nan # Average bank access latency per request
testsys.physmem.avgBusLat nan # Average bus latency per request
testsys.physmem.avgMemAccLat nan # Average memory access latency
testsys.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s
testsys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
testsys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
testsys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
testsys.physmem.busUtil 0.00 # Data bus utilization in percentage
testsys.physmem.avgRdQLen 0.00 # Average read queue length over time
testsys.physmem.avgWrQLen 0.00 # Average write queue length over time
testsys.physmem.readRowHits 0 # Number of row buffer hits during reads
testsys.physmem.writeRowHits 0 # Number of row buffer hits during writes
testsys.physmem.readRowHitRate nan # Row buffer hit rate for reads
testsys.physmem.writeRowHitRate nan # Row buffer hit rate for writes
testsys.physmem.avgGap nan # Average gap between requests
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
testsys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes.
testsys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
testsys.disk0.dma_write_txs 0 # Number of DMA write transactions.
testsys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
testsys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
testsys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
testsys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes.
testsys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
testsys.disk2.dma_write_txs 0 # Number of DMA write transactions.
tests: update tests for TLB unification
2009-04-09 07:21:30 +02:00
testsys.cpu.dtb.fetch_hits 0 # ITB hits
testsys.cpu.dtb.fetch_misses 0 # ITB misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.dtb.fetch_acv 0 # ITB acv
testsys.cpu.dtb.fetch_accesses 0 # ITB accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.cpu.dtb.read_hits 3916928 # DTB read hits
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
testsys.cpu.dtb.read_misses 3287 # DTB read misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.dtb.read_acv 80 # DTB read access violations
testsys.cpu.dtb.read_accesses 225414 # DTB read accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.cpu.dtb.write_hits 2316846 # DTB write hits
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
testsys.cpu.dtb.write_misses 528 # DTB write misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.dtb.write_acv 81 # DTB write access violations
testsys.cpu.dtb.write_accesses 109988 # DTB write accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.cpu.dtb.data_hits 6233774 # DTB hits
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.dtb.data_misses 3815 # DTB misses
testsys.cpu.dtb.data_acv 161 # DTB access violations
testsys.cpu.dtb.data_accesses 335402 # DTB accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.cpu.itb.fetch_hits 4052272 # ITB hits
tests: update tests for TLB unification
2009-04-09 07:21:30 +02:00
testsys.cpu.itb.fetch_misses 1497 # ITB misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.itb.fetch_acv 69 # ITB acv
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.cpu.itb.fetch_accesses 4053769 # ITB accesses
tests: update tests for TLB unification
2009-04-09 07:21:30 +02:00
testsys.cpu.itb.read_hits 0 # DTB read hits
testsys.cpu.itb.read_misses 0 # DTB read misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.itb.read_acv 0 # DTB read access violations
testsys.cpu.itb.read_accesses 0 # DTB read accesses
tests: update tests for TLB unification
2009-04-09 07:21:30 +02:00
testsys.cpu.itb.write_hits 0 # DTB write hits
testsys.cpu.itb.write_misses 0 # DTB write misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.itb.write_acv 0 # DTB write access violations
testsys.cpu.itb.write_accesses 0 # DTB write accesses
testsys.cpu.itb.data_hits 0 # DTB hits
testsys.cpu.itb.data_misses 0 # DTB misses
testsys.cpu.itb.data_acv 0 # DTB access violations
testsys.cpu.itb.data_accesses 0 # DTB accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.cpu.numCycles 400815936 # number of cpu cycles simulated
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.cpu.committedInsts 20258165 # Number of instructions committed
testsys.cpu.committedOps 20258165 # Number of ops (including micro ops) committed
testsys.cpu.num_int_alu_accesses 18837392 # Number of integer alu accesses
testsys.cpu.num_fp_alu_accesses 17313 # Number of float alu accesses
testsys.cpu.num_func_calls 1221260 # number of times a function call or return occured
testsys.cpu.num_conditional_control_insts 1442190 # number of instructions that are conditional controls
testsys.cpu.num_int_insts 18837392 # number of integer instructions
testsys.cpu.num_fp_insts 17313 # number of float instructions
testsys.cpu.num_int_register_reads 24787608 # number of times the integer registers were read
testsys.cpu.num_int_register_writes 14694255 # number of times the integer registers were written
testsys.cpu.num_fp_register_reads 11133 # number of times the floating registers were read
testsys.cpu.num_fp_register_writes 10789 # number of times the floating registers were written
testsys.cpu.num_mem_refs 6263009 # number of memory refs
testsys.cpu.num_load_insts 3944038 # Number of load instructions
testsys.cpu.num_store_insts 2318971 # Number of store instructions
testsys.cpu.num_idle_cycles 380552362.972989 # Number of idle cycles
testsys.cpu.num_busy_cycles 20263573.027011 # Number of busy cycles
testsys.cpu.not_idle_fraction 0.050556 # Percentage of non-idle cycles
testsys.cpu.idle_fraction 0.949444 # Percentage of idle cycles
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
testsys.cpu.kern.inst.arm 0 # number of arm instructions executed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.cpu.kern.inst.quiesce 19598 # number of quiesce instructions executed
testsys.cpu.kern.inst.hwrei 153677 # number of hwrei instructions executed
testsys.cpu.kern.ipl_count::0 62790 42.68% 42.68% # number of times we switched to this ipl
testsys.cpu.kern.ipl_count::21 19620 13.34% 56.01% # number of times we switched to this ipl
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
testsys.cpu.kern.ipl_count::22 205 0.14% 56.15% # number of times we switched to this ipl
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.cpu.kern.ipl_count::31 64514 43.85% 100.00% # number of times we switched to this ipl
testsys.cpu.kern.ipl_count::total 147129 # number of times we switched to this ipl
testsys.cpu.kern.ipl_good::0 62784 43.18% 43.18% # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_good::21 19620 13.49% 56.67% # number of times we switched to this ipl from a different ipl
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
testsys.cpu.kern.ipl_good::22 205 0.14% 56.81% # number of times we switched to this ipl from a different ipl
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.cpu.kern.ipl_good::31 62791 43.19% 100.00% # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_good::total 145400 # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_ticks::0 194352160500 96.98% 96.98% # number of cycles we spent at this ipl
testsys.cpu.kern.ipl_ticks::21 1588908500 0.79% 97.77% # number of cycles we spent at this ipl
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
testsys.cpu.kern.ipl_ticks::22 8815000 0.00% 97.78% # number of cycles we spent at this ipl
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.cpu.kern.ipl_ticks::31 4458302500 2.22% 100.00% # number of cycles we spent at this ipl
testsys.cpu.kern.ipl_ticks::total 200408186500 # number of cycles we spent at this ipl
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
testsys.cpu.kern.ipl_used::0 0.999904 # fraction of swpipl calls that actually changed the ipl
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
testsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.cpu.kern.ipl_used::31 0.973293 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.ipl_used::total 0.988248 # fraction of swpipl calls that actually changed the ipl
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
testsys.cpu.kern.syscall::2 3 3.61% 3.61% # number of syscalls executed
testsys.cpu.kern.syscall::3 7 8.43% 12.05% # number of syscalls executed
testsys.cpu.kern.syscall::4 1 1.20% 13.25% # number of syscalls executed
testsys.cpu.kern.syscall::6 7 8.43% 21.69% # number of syscalls executed
testsys.cpu.kern.syscall::17 7 8.43% 30.12% # number of syscalls executed
testsys.cpu.kern.syscall::19 2 2.41% 32.53% # number of syscalls executed
testsys.cpu.kern.syscall::20 1 1.20% 33.73% # number of syscalls executed
testsys.cpu.kern.syscall::33 3 3.61% 37.35% # number of syscalls executed
testsys.cpu.kern.syscall::45 10 12.05% 49.40% # number of syscalls executed
testsys.cpu.kern.syscall::48 5 6.02% 55.42% # number of syscalls executed
testsys.cpu.kern.syscall::54 1 1.20% 56.63% # number of syscalls executed
testsys.cpu.kern.syscall::59 3 3.61% 60.24% # number of syscalls executed
testsys.cpu.kern.syscall::71 15 18.07% 78.31% # number of syscalls executed
testsys.cpu.kern.syscall::74 4 4.82% 83.13% # number of syscalls executed
testsys.cpu.kern.syscall::97 2 2.41% 85.54% # number of syscalls executed
testsys.cpu.kern.syscall::98 2 2.41% 87.95% # number of syscalls executed
testsys.cpu.kern.syscall::101 2 2.41% 90.36% # number of syscalls executed
testsys.cpu.kern.syscall::102 2 2.41% 92.77% # number of syscalls executed
testsys.cpu.kern.syscall::104 1 1.20% 93.98% # number of syscalls executed
testsys.cpu.kern.syscall::105 3 3.61% 97.59% # number of syscalls executed
testsys.cpu.kern.syscall::118 2 2.41% 100.00% # number of syscalls executed
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
testsys.cpu.kern.syscall::total 83 # number of syscalls executed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.cpu.kern.callpal::swpctx 437 0.34% 0.34% # number of callpals executed
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
testsys.cpu.kern.callpal::tbi 20 0.02% 0.36% # number of callpals executed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.cpu.kern.callpal::swpipl 106841 83.26% 83.62% # number of callpals executed
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
testsys.cpu.kern.callpal::rdps 359 0.28% 83.90% # number of callpals executed
testsys.cpu.kern.callpal::wrusp 3 0.00% 83.90% # number of callpals executed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.cpu.kern.callpal::rdusp 3 0.00% 83.90% # number of callpals executed
testsys.cpu.kern.callpal::rti 20470 15.95% 99.86% # number of callpals executed
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
testsys.cpu.kern.callpal::callsys 140 0.11% 99.97% # number of callpals executed
testsys.cpu.kern.callpal::imb 44 0.03% 100.00% # number of callpals executed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.cpu.kern.callpal::total 128317 # number of callpals executed
testsys.cpu.kern.mode_switch::kernel 1281 # number of protection mode switches
testsys.cpu.kern.mode_switch::user 703 # number of protection mode switches
testsys.cpu.kern.mode_switch::idle 19627 # number of protection mode switches
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
testsys.cpu.kern.mode_good::kernel 707
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.cpu.kern.mode_good::user 703
testsys.cpu.kern.mode_good::idle 4
testsys.cpu.kern.mode_switch_good::kernel 0.551913 # fraction of useful protection mode switches
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.cpu.kern.mode_switch_good::idle 0.000204 # fraction of useful protection mode switches
testsys.cpu.kern.mode_switch_good::total 0.065430 # fraction of useful protection mode switches
testsys.cpu.kern.mode_ticks::kernel 1002766500 60.53% 60.53% # number of ticks spent at the given mode
testsys.cpu.kern.mode_ticks::user 533073000 32.18% 92.70% # number of ticks spent at the given mode
testsys.cpu.kern.mode_ticks::idle 120928500 7.30% 100.00% # number of ticks spent at the given mode
testsys.cpu.kern.swap_context 437 # number of times the context was actually changed
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
testsys.tsunami.ethernet.rxBytes 798 # Bytes Received
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.tsunami.ethernet.txPackets 8 # Number of Packets Transmitted
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
testsys.tsunami.ethernet.rxPackets 5 # Number of Packets Received
testsys.tsunami.ethernet.txIpChecksums 2 # Number of tx IP Checksums done by device
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.tsunami.ethernet.rxIpChecksums 5 # Number of rx IP Checksums done by device
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
testsys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.tsunami.ethernet.rxTcpChecksums 5 # Number of rx TCP Checksums done by device
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
testsys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.tsunami.ethernet.descDMAReads 2131994 # Number of descriptors the device read w/ DMA
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.tsunami.ethernet.descDmaReadBytes 51167856 # number of descriptor bytes read w/ DMA
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
testsys.tsunami.ethernet.totBandwidth 70176 # Total Bandwidth (bits/s)
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.tsunami.ethernet.totPackets 13 # Total Packets
testsys.tsunami.ethernet.totBytes 1758 # Total Bytes
testsys.tsunami.ethernet.totPPS 65 # Total Tranmission Rate (packets/s)
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
testsys.tsunami.ethernet.txBandwidth 38322 # Transmit Bandwidth (bits/s)
testsys.tsunami.ethernet.rxBandwidth 31855 # Receive Bandwidth (bits/s)
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.tsunami.ethernet.txPPS 40 # Packet Tranmission Rate (packets/s)
testsys.tsunami.ethernet.rxPPS 25 # Packet Reception Rate (packets/s)
testsys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
testsys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
testsys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
testsys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
testsys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
testsys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
testsys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
testsys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
testsys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
Stats: Update stats for twosys-tsunami after setting CPU clock This patch updates the stats to reflect the addition of a clock period other than the default 1 Tick.
2012-09-25 00:03:43 +02:00
testsys.tsunami.ethernet.postedRxDesc 5 # number of RxDesc interrupts posted to CPU
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
testsys.tsunami.ethernet.totalRxDesc 5 # total number of RxDesc written to ISR
testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
testsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.tsunami.ethernet.postedTxIdle 19571 # number of TxIdle interrupts posted to CPU
Stats: Update stats for twosys-tsunami after setting CPU clock This patch updates the stats to reflect the addition of a clock period other than the default 1 Tick.
2012-09-25 00:03:43 +02:00
testsys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.tsunami.ethernet.totalTxIdle 2131994 # total number of TxIdle written to ISR
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
testsys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
testsys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.tsunami.ethernet.postedInterrupts 2132012 # number of posts to CPU
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.physmem.bytes_read::cpu.inst 76288612 # Number of bytes read from this memory
drivesys.physmem.bytes_read::cpu.data 26312880 # Number of bytes read from this memory
drivesys.physmem.bytes_read::tsunami.ethernet 51169134 # Number of bytes read from this memory
drivesys.physmem.bytes_read::total 153770626 # Number of bytes read from this memory
drivesys.physmem.bytes_inst_read::cpu.inst 76288612 # Number of instructions bytes read from this memory
drivesys.physmem.bytes_inst_read::total 76288612 # Number of instructions bytes read from this memory
drivesys.physmem.bytes_written::cpu.data 14635456 # Number of bytes written to this memory
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
drivesys.physmem.bytes_written::tsunami.ethernet 1064 # Number of bytes written to this memory
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.physmem.bytes_written::total 14636520 # Number of bytes written to this memory
drivesys.physmem.num_reads::cpu.inst 19072153 # Number of read requests responded to by this memory
drivesys.physmem.num_reads::cpu.data 3651006 # Number of read requests responded to by this memory
drivesys.physmem.num_reads::tsunami.ethernet 2132030 # Number of read requests responded to by this memory
drivesys.physmem.num_reads::total 24855189 # Number of read requests responded to by this memory
drivesys.physmem.num_writes::cpu.data 2026958 # Number of write requests responded to by this memory
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
drivesys.physmem.num_writes::tsunami.ethernet 37 # Number of write requests responded to by this memory
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.physmem.num_writes::total 2026995 # Number of write requests responded to by this memory
drivesys.physmem.bw_read::cpu.inst 380664044 # Total read bandwidth from this memory (bytes/s)
drivesys.physmem.bw_read::cpu.data 131295708 # Total read bandwidth from this memory (bytes/s)
drivesys.physmem.bw_read::tsunami.ethernet 255323160 # Total read bandwidth from this memory (bytes/s)
drivesys.physmem.bw_read::total 767282912 # Total read bandwidth from this memory (bytes/s)
drivesys.physmem.bw_inst_read::cpu.inst 380664044 # Instruction read bandwidth from this memory (bytes/s)
drivesys.physmem.bw_inst_read::total 380664044 # Instruction read bandwidth from this memory (bytes/s)
drivesys.physmem.bw_write::cpu.data 73027831 # Write bandwidth from this memory (bytes/s)
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.physmem.bw_write::tsunami.ethernet 5309 # Write bandwidth from this memory (bytes/s)
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.physmem.bw_write::total 73033140 # Write bandwidth from this memory (bytes/s)
drivesys.physmem.bw_total::cpu.inst 380664044 # Total bandwidth to/from this memory (bytes/s)
drivesys.physmem.bw_total::cpu.data 204323539 # Total bandwidth to/from this memory (bytes/s)
drivesys.physmem.bw_total::tsunami.ethernet 255328469 # Total bandwidth to/from this memory (bytes/s)
drivesys.physmem.bw_total::total 840316053 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
drivesys.physmem.readReqs 0 # Total number of read requests seen
drivesys.physmem.writeReqs 0 # Total number of write requests seen
drivesys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
drivesys.physmem.bytesRead 0 # Total number of bytes read from memory
drivesys.physmem.bytesWritten 0 # Total number of bytes written to memory
drivesys.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
drivesys.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
drivesys.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
drivesys.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
drivesys.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis
drivesys.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
drivesys.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
drivesys.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
drivesys.physmem.totGap 0 # Total gap between requests
drivesys.physmem.readPktSize::0 0 # Categorize read packet sizes
drivesys.physmem.readPktSize::1 0 # Categorize read packet sizes
drivesys.physmem.readPktSize::2 0 # Categorize read packet sizes
drivesys.physmem.readPktSize::3 0 # Categorize read packet sizes
drivesys.physmem.readPktSize::4 0 # Categorize read packet sizes
drivesys.physmem.readPktSize::5 0 # Categorize read packet sizes
drivesys.physmem.readPktSize::6 0 # Categorize read packet sizes
drivesys.physmem.readPktSize::7 0 # Categorize read packet sizes
drivesys.physmem.readPktSize::8 0 # Categorize read packet sizes
drivesys.physmem.writePktSize::0 0 # categorize write packet sizes
drivesys.physmem.writePktSize::1 0 # categorize write packet sizes
drivesys.physmem.writePktSize::2 0 # categorize write packet sizes
drivesys.physmem.writePktSize::3 0 # categorize write packet sizes
drivesys.physmem.writePktSize::4 0 # categorize write packet sizes
drivesys.physmem.writePktSize::5 0 # categorize write packet sizes
drivesys.physmem.writePktSize::6 0 # categorize write packet sizes
drivesys.physmem.writePktSize::7 0 # categorize write packet sizes
drivesys.physmem.writePktSize::8 0 # categorize write packet sizes
drivesys.physmem.neitherpktsize::0 0 # categorize neither packet sizes
drivesys.physmem.neitherpktsize::1 0 # categorize neither packet sizes
drivesys.physmem.neitherpktsize::2 0 # categorize neither packet sizes
drivesys.physmem.neitherpktsize::3 0 # categorize neither packet sizes
drivesys.physmem.neitherpktsize::4 0 # categorize neither packet sizes
drivesys.physmem.neitherpktsize::5 0 # categorize neither packet sizes
drivesys.physmem.neitherpktsize::6 0 # categorize neither packet sizes
drivesys.physmem.neitherpktsize::7 0 # categorize neither packet sizes
drivesys.physmem.neitherpktsize::8 0 # categorize neither packet sizes
drivesys.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
drivesys.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
drivesys.physmem.totQLat 0 # Total cycles spent in queuing delays
drivesys.physmem.totMemAccLat 0 # Sum of mem lat for all requests
drivesys.physmem.totBusLat 0 # Total cycles spent in databus access
drivesys.physmem.totBankLat 0 # Total cycles spent in bank access
drivesys.physmem.avgQLat nan # Average queueing delay per request
drivesys.physmem.avgBankLat nan # Average bank access latency per request
drivesys.physmem.avgBusLat nan # Average bus latency per request
drivesys.physmem.avgMemAccLat nan # Average memory access latency
drivesys.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s
drivesys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
drivesys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
drivesys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
drivesys.physmem.busUtil 0.00 # Data bus utilization in percentage
drivesys.physmem.avgRdQLen 0.00 # Average read queue length over time
drivesys.physmem.avgWrQLen 0.00 # Average write queue length over time
drivesys.physmem.readRowHits 0 # Number of row buffer hits during reads
drivesys.physmem.writeRowHits 0 # Number of row buffer hits during writes
drivesys.physmem.readRowHitRate nan # Row buffer hit rate for reads
drivesys.physmem.writeRowHitRate nan # Row buffer hit rate for writes
drivesys.physmem.avgGap nan # Average gap between requests
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
drivesys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes.
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
drivesys.disk0.dma_write_txs 0 # Number of DMA write transactions.
drivesys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
drivesys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
drivesys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes.
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
drivesys.disk2.dma_write_txs 0 # Number of DMA write transactions.
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.dtb.fetch_hits 0 # ITB hits
drivesys.cpu.dtb.fetch_misses 0 # ITB misses
drivesys.cpu.dtb.fetch_acv 0 # ITB acv
drivesys.cpu.dtb.fetch_accesses 0 # ITB accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.cpu.dtb.read_hits 3729326 # DTB read hits
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.dtb.read_misses 487 # DTB read misses
drivesys.cpu.dtb.read_acv 30 # DTB read access violations
Stats: Update stats for twosys-tsunami after setting CPU clock This patch updates the stats to reflect the addition of a clock period other than the default 1 Tick.
2012-09-25 00:03:43 +02:00
drivesys.cpu.dtb.read_accesses 267991 # DTB read accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.cpu.dtb.write_hits 2086333 # DTB write hits
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.dtb.write_misses 82 # DTB write misses
drivesys.cpu.dtb.write_acv 10 # DTB write access violations
Stats: Update stats for twosys-tsunami after setting CPU clock This patch updates the stats to reflect the addition of a clock period other than the default 1 Tick.
2012-09-25 00:03:43 +02:00
drivesys.cpu.dtb.write_accesses 133239 # DTB write accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.cpu.dtb.data_hits 5815659 # DTB hits
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.dtb.data_misses 569 # DTB misses
drivesys.cpu.dtb.data_acv 40 # DTB access violations
Stats: Update stats for twosys-tsunami after setting CPU clock This patch updates the stats to reflect the addition of a clock period other than the default 1 Tick.
2012-09-25 00:03:43 +02:00
drivesys.cpu.dtb.data_accesses 401230 # DTB accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.cpu.itb.fetch_hits 4201097 # ITB hits
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.itb.fetch_misses 194 # ITB misses
drivesys.cpu.itb.fetch_acv 22 # ITB acv
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.cpu.itb.fetch_accesses 4201291 # ITB accesses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.itb.read_hits 0 # DTB read hits
drivesys.cpu.itb.read_misses 0 # DTB read misses
drivesys.cpu.itb.read_acv 0 # DTB read access violations
drivesys.cpu.itb.read_accesses 0 # DTB read accesses
drivesys.cpu.itb.write_hits 0 # DTB write hits
drivesys.cpu.itb.write_misses 0 # DTB write misses
drivesys.cpu.itb.write_acv 0 # DTB write access violations
drivesys.cpu.itb.write_accesses 0 # DTB write accesses
drivesys.cpu.itb.data_hits 0 # DTB hits
drivesys.cpu.itb.data_misses 0 # DTB misses
drivesys.cpu.itb.data_acv 0 # DTB access violations
drivesys.cpu.itb.data_accesses 0 # DTB accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.cpu.numCycles 801619128 # number of cpu cycles simulated
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
drivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.cpu.committedInsts 19071544 # Number of instructions committed
drivesys.cpu.committedOps 19071544 # Number of ops (including micro ops) committed
drivesys.cpu.num_int_alu_accesses 17759891 # Number of integer alu accesses
Stats: Update stats for twosys-tsunami after setting CPU clock This patch updates the stats to reflect the addition of a clock period other than the default 1 Tick.
2012-09-25 00:03:43 +02:00
drivesys.cpu.num_fp_alu_accesses 1412 # Number of float alu accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.cpu.num_func_calls 1266408 # number of times a function call or return occured
drivesys.cpu.num_conditional_control_insts 1266328 # number of instructions that are conditional controls
drivesys.cpu.num_int_insts 17759891 # number of integer instructions
Stats: Update stats for twosys-tsunami after setting CPU clock This patch updates the stats to reflect the addition of a clock period other than the default 1 Tick.
2012-09-25 00:03:43 +02:00
drivesys.cpu.num_fp_insts 1412 # number of float instructions
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.cpu.num_int_register_reads 23097438 # number of times the integer registers were read
drivesys.cpu.num_int_register_writes 13996340 # number of times the integer registers were written
Stats: Update stats for twosys-tsunami after setting CPU clock This patch updates the stats to reflect the addition of a clock period other than the default 1 Tick.
2012-09-25 00:03:43 +02:00
drivesys.cpu.num_fp_register_reads 760 # number of times the floating registers were read
drivesys.cpu.num_fp_register_writes 766 # number of times the floating registers were written
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.cpu.num_mem_refs 5837119 # number of memory refs
drivesys.cpu.num_load_insts 3750273 # Number of load instructions
drivesys.cpu.num_store_insts 2086846 # Number of store instructions
drivesys.cpu.num_idle_cycles 782547188.298833 # Number of idle cycles
drivesys.cpu.num_busy_cycles 19071939.701167 # Number of busy cycles
drivesys.cpu.not_idle_fraction 0.023792 # Percentage of non-idle cycles
drivesys.cpu.idle_fraction 0.976208 # Percentage of idle cycles
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.cpu.kern.inst.quiesce 19898 # number of quiesce instructions executed
drivesys.cpu.kern.inst.hwrei 143758 # number of hwrei instructions executed
drivesys.cpu.kern.ipl_count::0 60430 42.42% 42.42% # number of times we switched to this ipl
drivesys.cpu.kern.ipl_count::21 19752 13.86% 56.28% # number of times we switched to this ipl
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.kern.ipl_count::22 205 0.14% 56.42% # number of times we switched to this ipl
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.cpu.kern.ipl_count::31 62082 43.58% 100.00% # number of times we switched to this ipl
drivesys.cpu.kern.ipl_count::total 142469 # number of times we switched to this ipl
drivesys.cpu.kern.ipl_good::0 60430 42.91% 42.91% # number of times we switched to this ipl from a different ipl
drivesys.cpu.kern.ipl_good::21 19752 14.03% 56.94% # number of times we switched to this ipl from a different ipl
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.kern.ipl_good::22 205 0.15% 57.09% # number of times we switched to this ipl from a different ipl
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.cpu.kern.ipl_good::31 60432 42.91% 100.00% # number of times we switched to this ipl from a different ipl
drivesys.cpu.kern.ipl_good::total 140819 # number of times we switched to this ipl from a different ipl
drivesys.cpu.kern.ipl_ticks::0 197392680000 98.50% 98.50% # number of cycles we spent at this ipl
drivesys.cpu.kern.ipl_ticks::21 799890500 0.40% 98.90% # number of cycles we spent at this ipl
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.kern.ipl_ticks::22 4407500 0.00% 98.90% # number of cycles we spent at this ipl
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.cpu.kern.ipl_ticks::31 2207804000 1.10% 100.00% # number of cycles we spent at this ipl
drivesys.cpu.kern.ipl_ticks::total 200404782000 # number of cycles we spent at this ipl
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl
drivesys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
drivesys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.cpu.kern.ipl_used::31 0.973422 # fraction of swpipl calls that actually changed the ipl
drivesys.cpu.kern.ipl_used::total 0.988419 # fraction of swpipl calls that actually changed the ipl
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.kern.syscall::2 1 4.55% 4.55% # number of syscalls executed
drivesys.cpu.kern.syscall::6 3 13.64% 18.18% # number of syscalls executed
drivesys.cpu.kern.syscall::17 2 9.09% 27.27% # number of syscalls executed
drivesys.cpu.kern.syscall::97 1 4.55% 31.82% # number of syscalls executed
drivesys.cpu.kern.syscall::99 2 9.09% 40.91% # number of syscalls executed
drivesys.cpu.kern.syscall::101 2 9.09% 50.00% # number of syscalls executed
drivesys.cpu.kern.syscall::102 3 13.64% 63.64% # number of syscalls executed
drivesys.cpu.kern.syscall::104 1 4.55% 68.18% # number of syscalls executed
drivesys.cpu.kern.syscall::105 3 13.64% 81.82% # number of syscalls executed
drivesys.cpu.kern.syscall::106 1 4.55% 86.36% # number of syscalls executed
drivesys.cpu.kern.syscall::118 2 9.09% 95.45% # number of syscalls executed
drivesys.cpu.kern.syscall::150 1 4.55% 100.00% # number of syscalls executed
drivesys.cpu.kern.syscall::total 22 # number of syscalls executed
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.kern.callpal::swpctx 72 0.06% 0.06% # number of callpals executed
drivesys.cpu.kern.callpal::tbi 5 0.00% 0.06% # number of callpals executed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.cpu.kern.callpal::swpipl 102452 83.31% 83.37% # number of callpals executed
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.kern.callpal::rdps 354 0.29% 83.66% # number of callpals executed
drivesys.cpu.kern.callpal::rdusp 1 0.00% 83.66% # number of callpals executed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.cpu.kern.callpal::rti 20062 16.31% 99.97% # number of callpals executed
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.kern.callpal::callsys 25 0.02% 99.99% # number of callpals executed
drivesys.cpu.kern.callpal::imb 7 0.01% 100.00% # number of callpals executed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.cpu.kern.callpal::total 122978 # number of callpals executed
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.kern.mode_switch::kernel 214 # number of protection mode switches
drivesys.cpu.kern.mode_switch::user 139 # number of protection mode switches
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.cpu.kern.mode_switch::idle 19920 # number of protection mode switches
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.kern.mode_good::kernel 143
drivesys.cpu.kern.mode_good::user 139
Stats: Update stats for twosys-tsunami after setting CPU clock This patch updates the stats to reflect the addition of a clock period other than the default 1 Tick.
2012-09-25 00:03:43 +02:00
drivesys.cpu.kern.mode_good::idle 4
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.kern.mode_switch_good::kernel 0.668224 # fraction of useful protection mode switches
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.kern.mode_switch_good::idle 0.000201 # fraction of useful protection mode switches
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.cpu.kern.mode_switch_good::total 0.014107 # fraction of useful protection mode switches
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.kern.mode_ticks::kernel 78132750 2.64% 2.64% # number of ticks spent at the given mode
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.cpu.kern.mode_ticks::user 319665750 10.79% 13.43% # number of ticks spent at the given mode
drivesys.cpu.kern.mode_ticks::idle 2564974000 86.57% 100.00% # number of ticks spent at the given mode
Stats: Update stats for twosys-tsunami after setting CPU clock This patch updates the stats to reflect the addition of a clock period other than the default 1 Tick.
2012-09-25 00:03:43 +02:00
drivesys.cpu.kern.swap_context 72 # number of times the context was actually changed
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.txBytes 798 # Bytes Transmitted
drivesys.tsunami.ethernet.rxBytes 960 # Bytes Received
drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted
drivesys.tsunami.ethernet.rxPackets 8 # Number of Packets Received
drivesys.tsunami.ethernet.txIpChecksums 2 # Number of tx IP Checksums done by device
drivesys.tsunami.ethernet.rxIpChecksums 8 # Number of rx IP Checksums done by device
drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device
drivesys.tsunami.ethernet.rxTcpChecksums 8 # Number of rx TCP Checksums done by device
drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
drivesys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.tsunami.ethernet.descDMAReads 2132001 # Number of descriptors the device read w/ DMA
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.tsunami.ethernet.descDmaReadBytes 51168024 # number of descriptor bytes read w/ DMA
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.tsunami.ethernet.totBandwidth 70176 # Total Bandwidth (bits/s)
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.totPackets 13 # Total Packets
drivesys.tsunami.ethernet.totBytes 1758 # Total Bytes
drivesys.tsunami.ethernet.totPPS 65 # Total Tranmission Rate (packets/s)
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.tsunami.ethernet.txBandwidth 31855 # Transmit Bandwidth (bits/s)
drivesys.tsunami.ethernet.rxBandwidth 38322 # Receive Bandwidth (bits/s)
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.txPPS 25 # Packet Tranmission Rate (packets/s)
drivesys.tsunami.ethernet.rxPPS 40 # Packet Reception Rate (packets/s)
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
drivesys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
drivesys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
drivesys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
drivesys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
drivesys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
drivesys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
drivesys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.tsunami.ethernet.postedRxDesc 8 # number of RxDesc interrupts posted to CPU
drivesys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.totalRxDesc 8 # total number of RxDesc written to ISR
drivesys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
drivesys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.tsunami.ethernet.postedTxIdle 19750 # number of TxIdle interrupts posted to CPU
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.tsunami.ethernet.totalTxIdle 2132001 # total number of TxIdle written to ISR
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
drivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
drivesys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
drivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.tsunami.ethernet.postedInterrupts 2132022 # number of posts to CPU
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
sim_seconds 0.000407 # Number of seconds simulated
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
sim_ticks 407365500 # Number of ticks simulated
final_tick 4321609052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
host_inst_rate 12024534237 # Simulator instruction rate (inst/s)
host_op_rate 12021051237 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 9308365303 # Simulator tick rate (ticks/s)
host_mem_usage 472492 # Number of bytes of host memory used
host_seconds 0.04 # Real time elapsed on the host
sim_insts 525940622 # Number of instructions simulated
sim_ops 525940622 # Number of ops (including micro ops) simulated
testsys.physmem.bytes_read::cpu.inst 141136 # Number of bytes read from this memory
testsys.physmem.bytes_read::cpu.data 48760 # Number of bytes read from this memory
testsys.physmem.bytes_read::tsunami.ethernet 103992 # Number of bytes read from this memory
testsys.physmem.bytes_read::total 293888 # Number of bytes read from this memory
testsys.physmem.bytes_inst_read::cpu.inst 141136 # Number of instructions bytes read from this memory
testsys.physmem.bytes_inst_read::total 141136 # Number of instructions bytes read from this memory
testsys.physmem.bytes_written::cpu.data 27028 # Number of bytes written to this memory
testsys.physmem.bytes_written::total 27028 # Number of bytes written to this memory
testsys.physmem.num_reads::cpu.inst 35284 # Number of read requests responded to by this memory
testsys.physmem.num_reads::cpu.data 6744 # Number of read requests responded to by this memory
testsys.physmem.num_reads::tsunami.ethernet 4333 # Number of read requests responded to by this memory
testsys.physmem.num_reads::total 46361 # Number of read requests responded to by this memory
testsys.physmem.num_writes::cpu.data 3721 # Number of write requests responded to by this memory
testsys.physmem.num_writes::total 3721 # Number of write requests responded to by this memory
testsys.physmem.bw_read::cpu.inst 346460365 # Total read bandwidth from this memory (bytes/s)
testsys.physmem.bw_read::cpu.data 119695949 # Total read bandwidth from this memory (bytes/s)
testsys.physmem.bw_read::tsunami.ethernet 255279350 # Total read bandwidth from this memory (bytes/s)
testsys.physmem.bw_read::total 721435664 # Total read bandwidth from this memory (bytes/s)
testsys.physmem.bw_inst_read::cpu.inst 346460365 # Instruction read bandwidth from this memory (bytes/s)
testsys.physmem.bw_inst_read::total 346460365 # Instruction read bandwidth from this memory (bytes/s)
testsys.physmem.bw_write::cpu.data 66348279 # Write bandwidth from this memory (bytes/s)
testsys.physmem.bw_write::total 66348279 # Write bandwidth from this memory (bytes/s)
testsys.physmem.bw_total::cpu.inst 346460365 # Total bandwidth to/from this memory (bytes/s)
testsys.physmem.bw_total::cpu.data 186044228 # Total bandwidth to/from this memory (bytes/s)
testsys.physmem.bw_total::tsunami.ethernet 255279350 # Total bandwidth to/from this memory (bytes/s)
testsys.physmem.bw_total::total 787783943 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
testsys.physmem.readReqs 0 # Total number of read requests seen
testsys.physmem.writeReqs 0 # Total number of write requests seen
testsys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
testsys.physmem.bytesRead 0 # Total number of bytes read from memory
testsys.physmem.bytesWritten 0 # Total number of bytes written to memory
testsys.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
testsys.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
testsys.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
testsys.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
testsys.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis
testsys.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
testsys.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
testsys.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
testsys.physmem.totGap 0 # Total gap between requests
testsys.physmem.readPktSize::0 0 # Categorize read packet sizes
testsys.physmem.readPktSize::1 0 # Categorize read packet sizes
testsys.physmem.readPktSize::2 0 # Categorize read packet sizes
testsys.physmem.readPktSize::3 0 # Categorize read packet sizes
testsys.physmem.readPktSize::4 0 # Categorize read packet sizes
testsys.physmem.readPktSize::5 0 # Categorize read packet sizes
testsys.physmem.readPktSize::6 0 # Categorize read packet sizes
testsys.physmem.readPktSize::7 0 # Categorize read packet sizes
testsys.physmem.readPktSize::8 0 # Categorize read packet sizes
testsys.physmem.writePktSize::0 0 # categorize write packet sizes
testsys.physmem.writePktSize::1 0 # categorize write packet sizes
testsys.physmem.writePktSize::2 0 # categorize write packet sizes
testsys.physmem.writePktSize::3 0 # categorize write packet sizes
testsys.physmem.writePktSize::4 0 # categorize write packet sizes
testsys.physmem.writePktSize::5 0 # categorize write packet sizes
testsys.physmem.writePktSize::6 0 # categorize write packet sizes
testsys.physmem.writePktSize::7 0 # categorize write packet sizes
testsys.physmem.writePktSize::8 0 # categorize write packet sizes
testsys.physmem.neitherpktsize::0 0 # categorize neither packet sizes
testsys.physmem.neitherpktsize::1 0 # categorize neither packet sizes
testsys.physmem.neitherpktsize::2 0 # categorize neither packet sizes
testsys.physmem.neitherpktsize::3 0 # categorize neither packet sizes
testsys.physmem.neitherpktsize::4 0 # categorize neither packet sizes
testsys.physmem.neitherpktsize::5 0 # categorize neither packet sizes
testsys.physmem.neitherpktsize::6 0 # categorize neither packet sizes
testsys.physmem.neitherpktsize::7 0 # categorize neither packet sizes
testsys.physmem.neitherpktsize::8 0 # categorize neither packet sizes
testsys.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
testsys.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
testsys.physmem.totQLat 0 # Total cycles spent in queuing delays
testsys.physmem.totMemAccLat 0 # Sum of mem lat for all requests
testsys.physmem.totBusLat 0 # Total cycles spent in databus access
testsys.physmem.totBankLat 0 # Total cycles spent in bank access
testsys.physmem.avgQLat nan # Average queueing delay per request
testsys.physmem.avgBankLat nan # Average bank access latency per request
testsys.physmem.avgBusLat nan # Average bus latency per request
testsys.physmem.avgMemAccLat nan # Average memory access latency
testsys.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s
testsys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
testsys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
testsys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
testsys.physmem.busUtil 0.00 # Data bus utilization in percentage
testsys.physmem.avgRdQLen 0.00 # Average read queue length over time
testsys.physmem.avgWrQLen 0.00 # Average write queue length over time
testsys.physmem.readRowHits 0 # Number of row buffer hits during reads
testsys.physmem.writeRowHits 0 # Number of row buffer hits during writes
testsys.physmem.readRowHitRate nan # Row buffer hit rate for reads
testsys.physmem.writeRowHitRate nan # Row buffer hit rate for writes
testsys.physmem.avgGap nan # Average gap between requests
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
testsys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes.
testsys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
testsys.disk0.dma_write_txs 0 # Number of DMA write transactions.
testsys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
testsys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
testsys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
testsys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes.
testsys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
testsys.disk2.dma_write_txs 0 # Number of DMA write transactions.
tests: update tests for TLB unification
2009-04-09 07:21:30 +02:00
testsys.cpu.dtb.fetch_hits 0 # ITB hits
testsys.cpu.dtb.fetch_misses 0 # ITB misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.dtb.fetch_acv 0 # ITB acv
testsys.cpu.dtb.fetch_accesses 0 # ITB accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.cpu.dtb.read_hits 6900 # DTB read hits
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
testsys.cpu.dtb.read_misses 0 # DTB read misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.dtb.read_acv 0 # DTB read access violations
testsys.cpu.dtb.read_accesses 0 # DTB read accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.cpu.dtb.write_hits 3839 # DTB write hits
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
testsys.cpu.dtb.write_misses 0 # DTB write misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.dtb.write_acv 0 # DTB write access violations
testsys.cpu.dtb.write_accesses 0 # DTB write accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.cpu.dtb.data_hits 10739 # DTB hits
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.dtb.data_misses 0 # DTB misses
testsys.cpu.dtb.data_acv 0 # DTB access violations
testsys.cpu.dtb.data_accesses 0 # DTB accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.cpu.itb.fetch_hits 5847 # ITB hits
tests: update tests for TLB unification
2009-04-09 07:21:30 +02:00
testsys.cpu.itb.fetch_misses 0 # ITB misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.itb.fetch_acv 0 # ITB acv
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.cpu.itb.fetch_accesses 5847 # ITB accesses
tests: update tests for TLB unification
2009-04-09 07:21:30 +02:00
testsys.cpu.itb.read_hits 0 # DTB read hits
testsys.cpu.itb.read_misses 0 # DTB read misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.itb.read_acv 0 # DTB read access violations
testsys.cpu.itb.read_accesses 0 # DTB read accesses
tests: update tests for TLB unification
2009-04-09 07:21:30 +02:00
testsys.cpu.itb.write_hits 0 # DTB write hits
testsys.cpu.itb.write_misses 0 # DTB write misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.itb.write_acv 0 # DTB write access violations
testsys.cpu.itb.write_accesses 0 # DTB write accesses
testsys.cpu.itb.data_hits 0 # DTB hits
testsys.cpu.itb.data_misses 0 # DTB misses
testsys.cpu.itb.data_acv 0 # DTB access violations
testsys.cpu.itb.data_accesses 0 # DTB accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.cpu.numCycles 799188 # number of cpu cycles simulated
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.cpu.committedInsts 35284 # Number of instructions committed
testsys.cpu.committedOps 35284 # Number of ops (including micro ops) committed
testsys.cpu.num_int_alu_accesses 32710 # Number of integer alu accesses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.cpu.num_func_calls 2330 # number of times a function call or return occured
testsys.cpu.num_conditional_control_insts 2292 # number of instructions that are conditional controls
testsys.cpu.num_int_insts 32710 # number of integer instructions
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.num_fp_insts 0 # number of float instructions
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.cpu.num_int_register_reads 42720 # number of times the integer registers were read
testsys.cpu.num_int_register_writes 25860 # number of times the integer registers were written
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.num_fp_register_reads 0 # number of times the floating registers were read
testsys.cpu.num_fp_register_writes 0 # number of times the floating registers were written
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.cpu.num_mem_refs 10779 # number of memory refs
testsys.cpu.num_load_insts 6939 # Number of load instructions
testsys.cpu.num_store_insts 3840 # Number of store instructions
testsys.cpu.num_idle_cycles 764577.129267 # Number of idle cycles
testsys.cpu.num_busy_cycles 34610.870733 # Number of busy cycles
testsys.cpu.not_idle_fraction 0.043308 # Percentage of non-idle cycles
testsys.cpu.idle_fraction 0.956692 # Percentage of idle cycles
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
testsys.cpu.kern.inst.arm 0 # number of arm instructions executed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.cpu.kern.inst.quiesce 40 # number of quiesce instructions executed
testsys.cpu.kern.inst.hwrei 288 # number of hwrei instructions executed
testsys.cpu.kern.ipl_count::0 120 41.81% 41.81% # number of times we switched to this ipl
testsys.cpu.kern.ipl_count::21 39 13.59% 55.40% # number of times we switched to this ipl
testsys.cpu.kern.ipl_count::22 1 0.35% 55.75% # number of times we switched to this ipl
testsys.cpu.kern.ipl_count::31 127 44.25% 100.00% # number of times we switched to this ipl
testsys.cpu.kern.ipl_count::total 287 # number of times we switched to this ipl
testsys.cpu.kern.ipl_good::0 120 42.86% 42.86% # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_good::21 39 13.93% 56.79% # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_good::22 1 0.36% 57.14% # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_good::31 120 42.86% 100.00% # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_good::total 280 # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_ticks::0 387349500 96.94% 96.94% # number of cycles we spent at this ipl
testsys.cpu.kern.ipl_ticks::21 3159000 0.79% 97.73% # number of cycles we spent at this ipl
testsys.cpu.kern.ipl_ticks::22 43000 0.01% 97.74% # number of cycles we spent at this ipl
testsys.cpu.kern.ipl_ticks::31 9042500 2.26% 100.00% # number of cycles we spent at this ipl
testsys.cpu.kern.ipl_ticks::total 399594000 # number of cycles we spent at this ipl
Stats: Update stats for twosys-tsunami after setting CPU clock This patch updates the stats to reflect the addition of a clock period other than the default 1 Tick.
2012-09-25 00:03:43 +02:00
testsys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
testsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
Stats: Update stats for twosys-tsunami after setting CPU clock This patch updates the stats to reflect the addition of a clock period other than the default 1 Tick.
2012-09-25 00:03:43 +02:00
testsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.cpu.kern.ipl_used::31 0.944882 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.ipl_used::total 0.975610 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.callpal::swpipl 207 83.47% 83.47% # number of callpals executed
testsys.cpu.kern.callpal::rdps 1 0.40% 83.87% # number of callpals executed
testsys.cpu.kern.callpal::rti 40 16.13% 100.00% # number of callpals executed
testsys.cpu.kern.callpal::total 248 # number of callpals executed
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
testsys.cpu.kern.mode_switch::kernel 0 # number of protection mode switches
testsys.cpu.kern.mode_switch::user 0 # number of protection mode switches
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.cpu.kern.mode_switch::idle 40 # number of protection mode switches
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.cpu.kern.mode_good::kernel 0
testsys.cpu.kern.mode_good::user 0
testsys.cpu.kern.mode_good::idle 0
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
testsys.cpu.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches
testsys.cpu.kern.mode_switch_good::user nan # fraction of useful protection mode switches
Stats: Update stats for twosys-tsunami after setting CPU clock This patch updates the stats to reflect the addition of a clock period other than the default 1 Tick.
2012-09-25 00:03:43 +02:00
testsys.cpu.kern.mode_switch_good::idle 0 # fraction of useful protection mode switches
testsys.cpu.kern.mode_switch_good::total 0 # fraction of useful protection mode switches
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
testsys.cpu.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode
testsys.cpu.kern.mode_ticks::user 0 # number of ticks spent at the given mode
testsys.cpu.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
testsys.cpu.kern.swap_context 0 # number of times the context was actually changed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.tsunami.ethernet.descDMAReads 4333 # Number of descriptors the device read w/ DMA
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
testsys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.tsunami.ethernet.descDmaReadBytes 103992 # number of descriptor bytes read w/ DMA
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
testsys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
testsys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
testsys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
testsys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
testsys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
testsys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
testsys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
testsys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
testsys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
testsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.tsunami.ethernet.postedTxIdle 39 # number of TxIdle interrupts posted to CPU
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
testsys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.tsunami.ethernet.totalTxIdle 4333 # total number of TxIdle written to ISR
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
testsys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
testsys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
testsys.tsunami.ethernet.postedInterrupts 4333 # number of posts to CPU
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.physmem.bytes_read::cpu.inst 144608 # Number of bytes read from this memory
drivesys.physmem.bytes_read::cpu.data 49952 # Number of bytes read from this memory
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.physmem.bytes_read::tsunami.ethernet 104016 # Number of bytes read from this memory
drivesys.physmem.bytes_read::total 298576 # Number of bytes read from this memory
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.physmem.bytes_inst_read::cpu.inst 144608 # Number of instructions bytes read from this memory
drivesys.physmem.bytes_inst_read::total 144608 # Number of instructions bytes read from this memory
drivesys.physmem.bytes_written::cpu.data 27688 # Number of bytes written to this memory
drivesys.physmem.bytes_written::total 27688 # Number of bytes written to this memory
drivesys.physmem.num_reads::cpu.inst 36152 # Number of read requests responded to by this memory
drivesys.physmem.num_reads::cpu.data 6909 # Number of read requests responded to by this memory
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.physmem.num_reads::tsunami.ethernet 4334 # Number of read requests responded to by this memory
drivesys.physmem.num_reads::total 47395 # Number of read requests responded to by this memory
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.physmem.num_writes::cpu.data 3812 # Number of write requests responded to by this memory
drivesys.physmem.num_writes::total 3812 # Number of write requests responded to by this memory
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.physmem.bw_read::cpu.inst 354983424 # Total read bandwidth from this memory (bytes/s)
drivesys.physmem.bw_read::cpu.data 122622068 # Total read bandwidth from this memory (bytes/s)
drivesys.physmem.bw_read::tsunami.ethernet 255338265 # Total read bandwidth from this memory (bytes/s)
drivesys.physmem.bw_read::total 732943757 # Total read bandwidth from this memory (bytes/s)
drivesys.physmem.bw_inst_read::cpu.inst 354983424 # Instruction read bandwidth from this memory (bytes/s)
drivesys.physmem.bw_inst_read::total 354983424 # Instruction read bandwidth from this memory (bytes/s)
drivesys.physmem.bw_write::cpu.data 67968446 # Write bandwidth from this memory (bytes/s)
drivesys.physmem.bw_write::total 67968446 # Write bandwidth from this memory (bytes/s)
drivesys.physmem.bw_total::cpu.inst 354983424 # Total bandwidth to/from this memory (bytes/s)
drivesys.physmem.bw_total::cpu.data 190590514 # Total bandwidth to/from this memory (bytes/s)
drivesys.physmem.bw_total::tsunami.ethernet 255338265 # Total bandwidth to/from this memory (bytes/s)
drivesys.physmem.bw_total::total 800912203 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
drivesys.physmem.readReqs 0 # Total number of read requests seen
drivesys.physmem.writeReqs 0 # Total number of write requests seen
drivesys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
drivesys.physmem.bytesRead 0 # Total number of bytes read from memory
drivesys.physmem.bytesWritten 0 # Total number of bytes written to memory
drivesys.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
drivesys.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
drivesys.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
drivesys.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
drivesys.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis
drivesys.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
drivesys.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
drivesys.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
drivesys.physmem.totGap 0 # Total gap between requests
drivesys.physmem.readPktSize::0 0 # Categorize read packet sizes
drivesys.physmem.readPktSize::1 0 # Categorize read packet sizes
drivesys.physmem.readPktSize::2 0 # Categorize read packet sizes
drivesys.physmem.readPktSize::3 0 # Categorize read packet sizes
drivesys.physmem.readPktSize::4 0 # Categorize read packet sizes
drivesys.physmem.readPktSize::5 0 # Categorize read packet sizes
drivesys.physmem.readPktSize::6 0 # Categorize read packet sizes
drivesys.physmem.readPktSize::7 0 # Categorize read packet sizes
drivesys.physmem.readPktSize::8 0 # Categorize read packet sizes
drivesys.physmem.writePktSize::0 0 # categorize write packet sizes
drivesys.physmem.writePktSize::1 0 # categorize write packet sizes
drivesys.physmem.writePktSize::2 0 # categorize write packet sizes
drivesys.physmem.writePktSize::3 0 # categorize write packet sizes
drivesys.physmem.writePktSize::4 0 # categorize write packet sizes
drivesys.physmem.writePktSize::5 0 # categorize write packet sizes
drivesys.physmem.writePktSize::6 0 # categorize write packet sizes
drivesys.physmem.writePktSize::7 0 # categorize write packet sizes
drivesys.physmem.writePktSize::8 0 # categorize write packet sizes
drivesys.physmem.neitherpktsize::0 0 # categorize neither packet sizes
drivesys.physmem.neitherpktsize::1 0 # categorize neither packet sizes
drivesys.physmem.neitherpktsize::2 0 # categorize neither packet sizes
drivesys.physmem.neitherpktsize::3 0 # categorize neither packet sizes
drivesys.physmem.neitherpktsize::4 0 # categorize neither packet sizes
drivesys.physmem.neitherpktsize::5 0 # categorize neither packet sizes
drivesys.physmem.neitherpktsize::6 0 # categorize neither packet sizes
drivesys.physmem.neitherpktsize::7 0 # categorize neither packet sizes
drivesys.physmem.neitherpktsize::8 0 # categorize neither packet sizes
drivesys.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
drivesys.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
drivesys.physmem.totQLat 0 # Total cycles spent in queuing delays
drivesys.physmem.totMemAccLat 0 # Sum of mem lat for all requests
drivesys.physmem.totBusLat 0 # Total cycles spent in databus access
drivesys.physmem.totBankLat 0 # Total cycles spent in bank access
drivesys.physmem.avgQLat nan # Average queueing delay per request
drivesys.physmem.avgBankLat nan # Average bank access latency per request
drivesys.physmem.avgBusLat nan # Average bus latency per request
drivesys.physmem.avgMemAccLat nan # Average memory access latency
drivesys.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s
drivesys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
drivesys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
drivesys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
drivesys.physmem.busUtil 0.00 # Data bus utilization in percentage
drivesys.physmem.avgRdQLen 0.00 # Average read queue length over time
drivesys.physmem.avgWrQLen 0.00 # Average write queue length over time
drivesys.physmem.readRowHits 0 # Number of row buffer hits during reads
drivesys.physmem.writeRowHits 0 # Number of row buffer hits during writes
drivesys.physmem.readRowHitRate nan # Row buffer hit rate for reads
drivesys.physmem.writeRowHitRate nan # Row buffer hit rate for writes
drivesys.physmem.avgGap nan # Average gap between requests
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
drivesys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes.
drivesys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
drivesys.disk0.dma_write_txs 0 # Number of DMA write transactions.
drivesys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
drivesys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
drivesys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
drivesys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes.
drivesys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
drivesys.disk2.dma_write_txs 0 # Number of DMA write transactions.
drivesys.cpu.dtb.fetch_hits 0 # ITB hits
drivesys.cpu.dtb.fetch_misses 0 # ITB misses
drivesys.cpu.dtb.fetch_acv 0 # ITB acv
drivesys.cpu.dtb.fetch_accesses 0 # ITB accesses
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.dtb.read_hits 7069 # DTB read hits
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.dtb.read_misses 0 # DTB read misses
drivesys.cpu.dtb.read_acv 0 # DTB read access violations
drivesys.cpu.dtb.read_accesses 0 # DTB read accesses
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.dtb.write_hits 3933 # DTB write hits
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.dtb.write_misses 0 # DTB write misses
drivesys.cpu.dtb.write_acv 0 # DTB write access violations
drivesys.cpu.dtb.write_accesses 0 # DTB write accesses
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.dtb.data_hits 11002 # DTB hits
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.dtb.data_misses 0 # DTB misses
drivesys.cpu.dtb.data_acv 0 # DTB access violations
drivesys.cpu.dtb.data_accesses 0 # DTB accesses
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.itb.fetch_hits 5992 # ITB hits
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.itb.fetch_misses 0 # ITB misses
drivesys.cpu.itb.fetch_acv 0 # ITB acv
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.itb.fetch_accesses 5992 # ITB accesses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.itb.read_hits 0 # DTB read hits
drivesys.cpu.itb.read_misses 0 # DTB read misses
drivesys.cpu.itb.read_acv 0 # DTB read access violations
drivesys.cpu.itb.read_accesses 0 # DTB read accesses
drivesys.cpu.itb.write_hits 0 # DTB write hits
drivesys.cpu.itb.write_misses 0 # DTB write misses
drivesys.cpu.itb.write_acv 0 # DTB write access violations
drivesys.cpu.itb.write_accesses 0 # DTB write accesses
drivesys.cpu.itb.data_hits 0 # DTB hits
drivesys.cpu.itb.data_misses 0 # DTB misses
drivesys.cpu.itb.data_acv 0 # DTB access violations
drivesys.cpu.itb.data_accesses 0 # DTB accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.cpu.numCycles 1624320 # number of cpu cycles simulated
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
drivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.committedInsts 36152 # Number of instructions committed
drivesys.cpu.committedOps 36152 # Number of ops (including micro ops) committed
drivesys.cpu.num_int_alu_accesses 33516 # Number of integer alu accesses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.num_func_calls 2388 # number of times a function call or return occured
drivesys.cpu.num_conditional_control_insts 2347 # number of instructions that are conditional controls
drivesys.cpu.num_int_insts 33516 # number of integer instructions
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.num_fp_insts 0 # number of float instructions
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.num_int_register_reads 43772 # number of times the integer registers were read
drivesys.cpu.num_int_register_writes 26499 # number of times the integer registers were written
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.num_fp_register_reads 0 # number of times the floating registers were read
drivesys.cpu.num_fp_register_writes 0 # number of times the floating registers were written
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.num_mem_refs 11043 # number of memory refs
drivesys.cpu.num_load_insts 7109 # Number of load instructions
drivesys.cpu.num_store_insts 3934 # Number of store instructions
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.cpu.num_idle_cycles 1588282.082886 # Number of idle cycles
drivesys.cpu.num_busy_cycles 36037.917114 # Number of busy cycles
drivesys.cpu.not_idle_fraction 0.022186 # Percentage of non-idle cycles
drivesys.cpu.idle_fraction 0.977814 # Percentage of idle cycles
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.kern.inst.quiesce 41 # number of quiesce instructions executed
drivesys.cpu.kern.inst.hwrei 295 # number of hwrei instructions executed
drivesys.cpu.kern.ipl_count::0 123 41.84% 41.84% # number of times we switched to this ipl
drivesys.cpu.kern.ipl_count::21 40 13.61% 55.44% # number of times we switched to this ipl
drivesys.cpu.kern.ipl_count::22 1 0.34% 55.78% # number of times we switched to this ipl
drivesys.cpu.kern.ipl_count::31 130 44.22% 100.00% # number of times we switched to this ipl
drivesys.cpu.kern.ipl_count::total 294 # number of times we switched to this ipl
drivesys.cpu.kern.ipl_good::0 123 42.86% 42.86% # number of times we switched to this ipl from a different ipl
drivesys.cpu.kern.ipl_good::21 40 13.94% 56.79% # number of times we switched to this ipl from a different ipl
drivesys.cpu.kern.ipl_good::22 1 0.35% 57.14% # number of times we switched to this ipl from a different ipl
drivesys.cpu.kern.ipl_good::31 123 42.86% 100.00% # number of times we switched to this ipl from a different ipl
drivesys.cpu.kern.ipl_good::total 287 # number of times we switched to this ipl from a different ipl
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.cpu.kern.ipl_ticks::0 399809000 98.46% 98.46% # number of cycles we spent at this ipl
drivesys.cpu.kern.ipl_ticks::21 1620000 0.40% 98.85% # number of cycles we spent at this ipl
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.kern.ipl_ticks::22 21500 0.01% 98.86% # number of cycles we spent at this ipl
drivesys.cpu.kern.ipl_ticks::31 4629500 1.14% 100.00% # number of cycles we spent at this ipl
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.cpu.kern.ipl_ticks::total 406080000 # number of cycles we spent at this ipl
Stats: Update stats for twosys-tsunami after setting CPU clock This patch updates the stats to reflect the addition of a clock period other than the default 1 Tick.
2012-09-25 00:03:43 +02:00
drivesys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
Stats: Update stats for twosys-tsunami after setting CPU clock This patch updates the stats to reflect the addition of a clock period other than the default 1 Tick.
2012-09-25 00:03:43 +02:00
drivesys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.kern.ipl_used::31 0.946154 # fraction of swpipl calls that actually changed the ipl
drivesys.cpu.kern.ipl_used::total 0.976190 # fraction of swpipl calls that actually changed the ipl
drivesys.cpu.kern.callpal::swpipl 212 83.46% 83.46% # number of callpals executed
drivesys.cpu.kern.callpal::rdps 1 0.39% 83.86% # number of callpals executed
drivesys.cpu.kern.callpal::rti 41 16.14% 100.00% # number of callpals executed
drivesys.cpu.kern.callpal::total 254 # number of callpals executed
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.kern.mode_switch::kernel 0 # number of protection mode switches
drivesys.cpu.kern.mode_switch::user 0 # number of protection mode switches
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.cpu.kern.mode_switch::idle 41 # number of protection mode switches
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.kern.mode_good::kernel 0
drivesys.cpu.kern.mode_good::user 0
drivesys.cpu.kern.mode_good::idle 0
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
drivesys.cpu.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches
drivesys.cpu.kern.mode_switch_good::user nan # fraction of useful protection mode switches
Stats: Update stats for twosys-tsunami after setting CPU clock This patch updates the stats to reflect the addition of a clock period other than the default 1 Tick.
2012-09-25 00:03:43 +02:00
drivesys.cpu.kern.mode_switch_good::idle 0 # fraction of useful protection mode switches
drivesys.cpu.kern.mode_switch_good::total 0 # fraction of useful protection mode switches
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.cpu.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode
drivesys.cpu.kern.mode_ticks::user 0 # number of ticks spent at the given mode
drivesys.cpu.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
drivesys.cpu.kern.swap_context 0 # number of times the context was actually changed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.tsunami.ethernet.descDMAReads 4334 # Number of descriptors the device read w/ DMA
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.tsunami.ethernet.descDmaReadBytes 104016 # number of descriptor bytes read w/ DMA
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
drivesys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
drivesys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
drivesys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
drivesys.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
drivesys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.tsunami.ethernet.postedTxIdle 40 # number of TxIdle interrupts posted to CPU
drivesys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.tsunami.ethernet.totalTxIdle 4334 # total number of TxIdle written to ISR
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
drivesys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
drivesys.tsunami.ethernet.postedInterrupts 4334 # number of posts to CPU
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
2006-12-01 07:24:01 +01:00
---------- End Simulation Statistics ----------
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