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Brad Beckmann e983ef9e8c testers: move testers to a new directory 
This patch moves the testers to a new subdirectory under src/cpu and includes
the necessary fixes to work with latest m5 initialization patches.

--HG--
rename : configs/example/determ_test.py => configs/example/ruby_direct_test.py
rename : src/cpu/directedtest/DirectedGenerator.cc => src/cpu/testers/directedtest/DirectedGenerator.cc
rename : src/cpu/directedtest/DirectedGenerator.hh => src/cpu/testers/directedtest/DirectedGenerator.hh
rename : src/cpu/directedtest/InvalidateGenerator.cc => src/cpu/testers/directedtest/InvalidateGenerator.cc
rename : src/cpu/directedtest/InvalidateGenerator.hh => src/cpu/testers/directedtest/InvalidateGenerator.hh
rename : src/cpu/directedtest/RubyDirectedTester.cc => src/cpu/testers/directedtest/RubyDirectedTester.cc
rename : src/cpu/directedtest/RubyDirectedTester.hh => src/cpu/testers/directedtest/RubyDirectedTester.hh
rename : src/cpu/directedtest/RubyDirectedTester.py => src/cpu/testers/directedtest/RubyDirectedTester.py
rename : src/cpu/directedtest/SConscript => src/cpu/testers/directedtest/SConscript
rename : src/cpu/directedtest/SeriesRequestGenerator.cc => src/cpu/testers/directedtest/SeriesRequestGenerator.cc
rename : src/cpu/directedtest/SeriesRequestGenerator.hh => src/cpu/testers/directedtest/SeriesRequestGenerator.hh
rename : src/cpu/memtest/MemTest.py => src/cpu/testers/memtest/MemTest.py
rename : src/cpu/memtest/SConscript => src/cpu/testers/memtest/SConscript
rename : src/cpu/memtest/memtest.cc => src/cpu/testers/memtest/memtest.cc
rename : src/cpu/memtest/memtest.hh => src/cpu/testers/memtest/memtest.hh
rename : src/cpu/rubytest/Check.cc => src/cpu/testers/rubytest/Check.cc
rename : src/cpu/rubytest/Check.hh => src/cpu/testers/rubytest/Check.hh
rename : src/cpu/rubytest/CheckTable.cc => src/cpu/testers/rubytest/CheckTable.cc
rename : src/cpu/rubytest/CheckTable.hh => src/cpu/testers/rubytest/CheckTable.hh
rename : src/cpu/rubytest/RubyTester.cc => src/cpu/testers/rubytest/RubyTester.cc
rename : src/cpu/rubytest/RubyTester.hh => src/cpu/testers/rubytest/RubyTester.hh
rename : src/cpu/rubytest/RubyTester.py => src/cpu/testers/rubytest/RubyTester.py
rename : src/cpu/rubytest/SConscript => src/cpu/testers/rubytest/SConscript
2010-08-24 12:07:22 -07:00
..
checker Minor remote GDB cleanup. 2010-06-03 16:54:26 -07:00
inorder Inorder: Fix compilation of m5.fast. 2010-08-14 01:00:45 -07:00
o3 ISA: Get rid of old, unused utility functions cluttering up the ISAs. 2010-08-23 16:14:20 -07:00
ozone ISA: Get rid of old, unused utility functions cluttering up the ISAs. 2010-08-23 16:14:20 -07:00
pred BPRED: Fixed the treshold-bug in the tournament predictor. 2010-05-13 23:45:57 -04:00
simple CPU: Make Exec trace to print predication result (if false) for memory instructions 2010-08-23 11:18:41 -05:00
testers testers: move testers to a new directory 2010-08-24 12:07:22 -07:00
trace request: rename INST_READ to INST_FETCH. 2009-04-20 18:54:02 -07:00
activity.cc o3cpu: give a name to the activity recorder for better tracing 2009-01-21 14:56:18 -08:00
activity.hh o3cpu: give a name to the activity recorder for better tracing 2009-01-21 14:56:18 -08:00
base.cc commit Soumyaroop's bug catch about max_insts_all_threads 2009-09-29 18:03:10 -04:00
base.hh tick: rename Clock namespace to SimClock 2010-04-15 16:24:12 -07:00
base_dyn_inst.hh CPU: Make Exec trace to print predication result (if false) for memory instructions 2010-08-23 11:18:41 -05:00
base_dyn_inst_impl.hh ARM: mark msr/mrs instructions as SerializeBefore/After 2010-08-23 11:18:41 -05:00
BaseCPU.py ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements. 2010-06-02 12:58:16 -05:00
CheckerCPU.py python: Move more code into m5.util allow SCons to use that code. 2009-09-22 15:24:16 -07:00
cpuevent.cc Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh. 2006-06-06 17:32:21 -04:00
cpuevent.hh eventq: convert all usage of events to use the new API. 2008-10-09 04:58:24 -07:00
exec_context.hh CPU: Add readBytes and writeBytes functions to the exec contexts. 2010-08-13 06:16:02 -07:00
exetrace.cc CPU: Make Exec trace to print predication result (if false) for memory instructions 2010-08-23 11:18:41 -05:00
exetrace.hh includes: sort includes again 2009-05-17 14:34:52 -07:00
ExeTracer.py SimObjects: Clean up handling of C++ namespaces. 2008-10-09 22:19:39 -07:00
func_unit.cc params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
func_unit.hh params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
FuncUnit.py Rename enum from OpType to OpClass so it's consistent with the 2007-06-11 23:10:58 -07:00
inst_seq.hh build: fix compile problems pointed out by gcc 4.4 2009-11-04 16:57:01 -08:00
inteltrace.cc arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh 2009-09-23 08:34:21 -07:00
inteltrace.hh includes: sort includes again 2009-05-17 14:34:52 -07:00
IntelTrace.py SimObjects: Clean up handling of C++ namespaces. 2008-10-09 22:19:39 -07:00
intr_control.cc style: Use the correct m5 style for things relating to interrupts. 2008-10-21 07:12:53 -07:00
intr_control.hh Interrupts: Inline some code and remove duplication. 2007-11-08 10:46:41 -05:00
IntrControl.py Move SimObject python files alongside the C++ and fix 2007-05-27 19:21:17 -07:00
legiontrace.cc build: fix compile problems pointed out by gcc 4.4 2009-11-04 16:57:01 -08:00
legiontrace.hh includes: sort includes again 2009-05-17 14:34:52 -07:00
LegionTrace.py SimObjects: Clean up handling of C++ namespaces. 2008-10-09 22:19:39 -07:00
m5legion_interface.h add fsr to the list of registers we are interested in 2007-01-30 18:27:04 -05:00
nativetrace.cc ARM: Make native trace print out what instruction caused an error. 2009-07-27 00:54:09 -07:00
nativetrace.hh ARM: Make native trace print out what instruction caused an error. 2009-07-27 00:54:09 -07:00
NativeTrace.py ARM: Make native trace print out what instruction caused an error. 2009-07-27 00:54:09 -07:00
op_class.hh Major changes to how SimObjects are created and initialized. Almost all 2007-07-23 21:51:38 -07:00
pc_event.cc debug: Move debug_break into src/base 2009-02-23 11:48:40 -08:00
pc_event.hh types: Move stuff for global types into src/base/types.hh 2009-05-17 14:34:50 -07:00
profile.cc Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh. 2006-06-06 17:32:21 -04:00
profile.hh arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh 2009-09-23 08:34:21 -07:00
quiesce_event.cc eventq: convert all usage of events to use the new API. 2008-10-09 04:58:24 -07:00
quiesce_event.hh Make the Event::description() a const function 2008-02-06 16:32:40 -05:00
SConscript cpu_models: get rid of cpu_models.py and move the stuff into SCons 2010-02-26 18:14:48 -08:00
simple_thread.cc ISA: Fix compilation. 2009-10-17 01:13:41 -07:00
simple_thread.hh CPU: Print out flatten-out register index as with IntRegs/FloatRegs traceflag 2010-08-23 11:18:41 -05:00
smt.hh types: add a type for thread IDs and try to use it everywhere 2009-05-26 09:23:13 -07:00
static_inst.cc inorder-tlb-cunit: merge the TLB as implicit to any memory access 2009-05-12 15:01:16 -04:00
static_inst.hh CPU: Make the constants for StaticInst flags visible outside the class. 2010-08-23 09:44:19 -07:00
thread_context.cc arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh 2009-09-23 08:34:21 -07:00
thread_context.hh ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate. 2010-08-23 11:18:40 -05:00
thread_state.cc Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions. 2009-07-08 23:02:22 -07:00
thread_state.hh arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh 2009-09-23 08:34:21 -07:00
translation.hh CPU: Added comments to address translation classes. 2010-03-25 12:43:52 +00:00