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gem5/cpu
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Korey Sewell c32b4ecac1 infinitesimal small baby steps toward MIPS actually working 
arch/mips/isa/formats/branch.isa:
    let user know that we alter r31 in disassembly
arch/mips/isa_traits.cc:
    add copyRegs function ...
    comment out serialize float code for now
arch/mips/isa_traits.hh:
    make FloatRegFile a class ... change values of architectural regs
arch/mips/process.cc:
    change MIPS to Mips
base/loader/elf_object.cc:
    get global pointer initialized to a value
base/loader/elf_object.hh:
    Add global_ptr to elf_object constructor
base/loader/object_file.hh:
    MIPS to Mips
base/traceflags.py:
    SimpleCPU trace flag
cpu/simple/cpu.cc:
    DPRINTF flags for SimpleCPU
cpu/static_inst.hh:
    Add Decoder functions to static_inst.hh

--HG--
extra : convert_revision : 0544a8524d3fe4229428cb06822f7da208c72459
2006-03-15 16:26:40 -05:00
..
memtest Steps towards setting up the infrastructure to allow the new CPU model to work in full system mode. 2006-03-04 15:18:40 -05:00
o3 Changed the floating point register file into a class with appropriate accessor functions. The width of the floating point register to access can be specified, and if not, it will be accessed at its "natural" width. That is, the width of each individual register. Also, the functions which access the bit representation of floating point registers can use the blahblahBits functions now instead of blahblahInt. 2006-03-14 15:55:00 -05:00
ozone Changed the floating point register file into a class with appropriate accessor functions. The width of the floating point register to access can be specified, and if not, it will be accessed at its "natural" width. That is, the width of each individual register. Also, the functions which access the bit representation of floating point registers can use the blahblahBits functions now instead of blahblahInt. 2006-03-14 15:55:00 -05:00
simple infinitesimal small baby steps toward MIPS actually working 2006-03-15 16:26:40 -05:00
trace Made Addr a global type 2006-02-21 03:38:21 -05:00
base.cc Hand merge. Stuff probably doesn't compile. 2006-03-09 18:35:28 -05:00
base.hh Replace Memory with MemObject; no need for two different levels of hierarchy there. 2006-03-12 17:21:59 -05:00
base_dyn_inst.cc Merge ktlim@zizzer:/bk/m5 2006-03-05 00:34:54 -05:00
base_dyn_inst.hh Steps towards setting up the infrastructure to allow the new CPU model to work in full system mode. 2006-03-04 15:18:40 -05:00
cpu_exec_context.cc Changed the floating point register file into a class with appropriate accessor functions. The width of the floating point register to access can be specified, and if not, it will be accessed at its "natural" width. That is, the width of each individual register. Also, the functions which access the bit representation of floating point registers can use the blahblahBits functions now instead of blahblahInt. 2006-03-14 15:55:00 -05:00
cpu_exec_context.hh Merge m5.eecs.umich.edu:/bk/newmem 2006-03-14 16:08:32 -05:00
cpu_models.py Enable building only selected CPU models via new scons 2006-02-23 17:00:29 -05:00
exec_context.hh Changed the floating point register file into a class with appropriate accessor functions. The width of the floating point register to access can be specified, and if not, it will be accessed at its "natural" width. That is, the width of each individual register. Also, the functions which access the bit representation of floating point registers can use the blahblahBits functions now instead of blahblahInt. 2006-03-14 15:55:00 -05:00
exetrace.cc Hand merge. Stuff probably doesn't compile. 2006-03-09 18:35:28 -05:00
exetrace.hh Made Addr a global type 2006-02-21 03:38:21 -05:00
inst_seq.hh fix problems on darwin/*BSD for syscall emulation mode 2006-02-10 14:21:32 -05:00
intr_control.cc Updates for the quiesceEvent that was added to the XC. 2006-03-07 19:59:12 -05:00
intr_control.hh Steps towards setting up the infrastructure to allow the new CPU model to work in full system mode. 2006-03-04 15:18:40 -05:00
op_class.cc Move op_class.hh out of encumbered/cpu/full and into cpu. 2006-02-21 22:12:27 -05:00
op_class.hh Move op_class.hh out of encumbered/cpu/full and into cpu. 2006-02-21 22:12:27 -05:00
pc_event.cc Steps towards setting up the infrastructure to allow the new CPU model to work in full system mode. 2006-03-04 15:18:40 -05:00
pc_event.hh Work towards factoring isa_traits.hh into smaller, more specialized files. 2006-03-10 19:11:27 -05:00
profile.cc Updates for the quiesceEvent that was added to the XC. 2006-03-07 19:59:12 -05:00
profile.hh Updates for the quiesceEvent that was added to the XC. 2006-03-07 19:59:12 -05:00
SConscript Make sure cpu/static_inst_exec_sigs.hh get rebuilt when 2006-02-25 22:57:46 -05:00
smt.hh Many files: 2005-06-05 05:16:00 -04:00
static_inst.cc Changes to untemplate StaticInst and StaticInstPtr, change the isa to a namespace instead of a class, an improvement to the architecture specific header file selection system, and fixed up a few include paths. 2006-02-19 02:34:37 -05:00
static_inst.hh infinitesimal small baby steps toward MIPS actually working 2006-03-15 16:26:40 -05:00