e196d20d9d
arch/alpha/arguments.cc:
rather than returning 0, put a panic in... it will actually make us fix
this rather than scratching our respective heads
base/loader/object_file.cc:
base/loader/object_file.hh:
Object loader now takes a port rather than a translating port
cpu/cpu_exec_context.cc:
cpu/cpu_exec_context.hh:
sim/process.cc:
Make translating port a type of port rather than anything special
cpu/simple/cpu.cc:
no need to grab a port from the cpu anymore
mem/physical.cc:
add an additional type of port to physicalmemory called "functional"
Only used for functional accesses (loading binaries/syscall emu)
mem/port.hh:
make readBlok/writeBlob virtual so translating port can do the
translation first
mem/translating_port.cc:
mem/translating_port.hh:
Make TranslatingPort inherit from Port
sim/system.cc:
header file that doesn't exit removed
--HG--
extra : convert_revision : 89b08f6146bba61f5605678d736055feab2fe6f7
|
||
|---|---|---|
| .. | ||
| memtest | ||
| o3 | ||
| ozone | ||
| simple | ||
| trace | ||
| base.cc | ||
| base.hh | ||
| base_dyn_inst.cc | ||
| base_dyn_inst.hh | ||
| cpu_exec_context.cc | ||
| cpu_exec_context.hh | ||
| cpu_models.py | ||
| exec_context.hh | ||
| exetrace.cc | ||
| exetrace.hh | ||
| inst_seq.hh | ||
| intr_control.cc | ||
| intr_control.hh | ||
| op_class.cc | ||
| op_class.hh | ||
| pc_event.cc | ||
| pc_event.hh | ||
| profile.cc | ||
| profile.hh | ||
| SConscript | ||
| smt.hh | ||
| static_inst.cc | ||
| static_inst.hh | ||