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checker
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checker: CheckerCPU handling of MiscRegs was incorrect
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2014-01-24 15:29:30 -06:00 |
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inorder
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cpu: Enable fast-forwarding for MIPS InOrderCPU and O3CPU
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2014-03-01 23:35:23 -06:00 |
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kvm
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kvm: x86: Always assume segments to be usable
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2014-03-03 14:34:33 +01:00 |
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nocpu
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SCons: Support building without an ISA
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2010-11-19 18:00:39 -06:00 |
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o3
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scons: Fixes uninitialized warnings issued by clang
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2014-03-07 15:56:23 -05:00 |
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ozone
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cpu: add consistent guarding to *_impl.hh files.
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2013-10-17 10:20:45 -05:00 |
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pred
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cpu: add consistent guarding to *_impl.hh files.
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2013-10-17 10:20:45 -05:00 |
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simple
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cpu: simple: Add support for using branch predictors
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2014-02-09 20:49:28 +01:00 |
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testers
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cpu: fix bug when TrafficGen deschedules event
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2014-01-29 22:35:04 -06:00 |
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activity.cc
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Fix: Address a few benign memory leaks
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2012-07-09 12:35:30 -04:00 |
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activity.hh
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Fix: Address a few benign memory leaks
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2012-07-09 12:35:30 -04:00 |
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base.cc
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sim: simulate with multiple threads and event queues
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2013-11-25 11:21:00 -06:00 |
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base.hh
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cpu: Add CPU support for generatig wake up events when LLSC adresses are snooped.
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2014-01-24 15:29:30 -06:00 |
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base_dyn_inst.hh
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cpu: Add CPU support for generatig wake up events when LLSC adresses are snooped.
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2014-01-24 15:29:30 -06:00 |
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base_dyn_inst_impl.hh
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cpu: Add support for instructions that zero cache lines.
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2014-01-24 15:29:30 -06:00 |
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BaseCPU.py
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arm: Add support for ARMv8 (AArch64 & AArch32)
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2014-01-24 15:29:34 -06:00 |
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CheckerCPU.py
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sim: Include object header files in SWIG interfaces
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2012-11-02 11:32:01 -05:00 |
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cpuevent.cc
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Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.
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2006-06-06 17:32:21 -04:00 |
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cpuevent.hh
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
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decode_cache.hh
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ISA,CPU: Generalize and split out the components of the decode cache.
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2012-05-26 13:45:12 -07:00 |
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dummy_checker.cc
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sim: Add the notion of clock domains to all ClockedObjects
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2013-06-27 05:49:49 -04:00 |
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dummy_checker.hh
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cpu: Add header files for checker CPUs
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2012-11-02 11:32:01 -05:00 |
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DummyChecker.py
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cpu: Make checker CPUs inherit from CheckerCPU in the Python hierarchy
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2013-02-15 17:40:08 -05:00 |
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exec_context.hh
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SE/FS: Expose the same methods on the CPUs in SE and FS modes.
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2011-11-01 04:01:13 -07:00 |
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exetrace.cc
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debug : Fixes the issue wherein Debug symbols were not getting dumped into trace files for SE mode
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2013-07-15 11:08:34 -04:00 |
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exetrace.hh
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trace: reimplement the DTRACE function so it doesn't use a vector
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2011-04-15 10:44:32 -07:00 |
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ExeTracer.py
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sim: Include object header files in SWIG interfaces
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2012-11-02 11:32:01 -05:00 |
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func_unit.cc
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params: Deprecate old-style constructors; update most SimObject constructors.
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2007-08-30 15:16:59 -04:00 |
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func_unit.hh
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Param: Transition to Cycles for relevant parameters
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2012-09-07 12:34:38 -04:00 |
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FuncUnit.py
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sim: Include object header files in SWIG interfaces
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2012-11-02 11:32:01 -05:00 |
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inst_seq.hh
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build: fix compile problems pointed out by gcc 4.4
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2009-11-04 16:57:01 -08:00 |
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inteltrace.cc
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gcc: Clean-up of non-C++0x compliant code, first steps
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2012-03-19 06:36:09 -04:00 |
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inteltrace.hh
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sim: Include object header files in SWIG interfaces
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2012-11-02 11:32:01 -05:00 |
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IntelTrace.py
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sim: Include object header files in SWIG interfaces
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2012-11-02 11:32:01 -05:00 |
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intr_control.cc
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SE/FS: Get rid of FULL_SYSTEM in the CPU directory.
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2011-11-18 01:33:28 -08:00 |
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intr_control.hh
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arch: Header clean up for NOISA resurrection
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2013-09-04 13:22:55 -04:00 |
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intr_control_noisa.cc
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arch: Resurrect the NOISA build target and rename it NULL
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2013-09-04 13:22:57 -04:00 |
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IntrControl.py
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sim: Include object header files in SWIG interfaces
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2012-11-02 11:32:01 -05:00 |
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legiontrace.cc
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Decoder: Remove the thread context get/set from the decoder.
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2013-01-04 19:00:45 -06:00 |
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legiontrace.hh
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scons: Add warning for missing declarations
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2013-02-19 05:56:07 -05:00 |
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LegionTrace.py
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sim: Include object header files in SWIG interfaces
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2012-11-02 11:32:01 -05:00 |
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m5legion_interface.h
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add fsr to the list of registers we are interested in
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2007-01-30 18:27:04 -05:00 |
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nativetrace.cc
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trace: reimplement the DTRACE function so it doesn't use a vector
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2011-04-15 10:44:32 -07:00 |
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nativetrace.hh
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clang: Enable compiling gem5 using clang 2.9 and 3.0
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2012-01-31 12:05:52 -05:00 |
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NativeTrace.py
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sim: Include object header files in SWIG interfaces
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2012-11-02 11:32:01 -05:00 |
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op_class.hh
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CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.
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2010-11-15 14:04:04 -06:00 |
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pc_event.cc
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arm: Enable support for triggering a sim panic on kernel panics
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2013-04-22 13:20:31 -04:00 |
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pc_event.hh
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arm: Enable support for triggering a sim panic on kernel panics
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2013-04-22 13:20:31 -04:00 |
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profile.cc
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
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profile.hh
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
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quiesce_event.cc
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trace: reimplement the DTRACE function so it doesn't use a vector
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2011-04-15 10:44:32 -07:00 |
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quiesce_event.hh
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clang: Enable compiling gem5 using clang 2.9 and 3.0
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2012-01-31 12:05:52 -05:00 |
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reg_class.cc
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cpu: add a condition-code register class
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2013-10-15 14:22:44 -04:00 |
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reg_class.hh
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cpu: add a condition-code register class
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2013-10-15 14:22:44 -04:00 |
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SConscript
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cpu: clean up architectural register classification
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2013-10-15 14:22:42 -04:00 |
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simple_thread.cc
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x86, cpu: corrects 270c9a75e91f, take over decoder on cpu switch
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2013-01-22 00:10:10 -06:00 |
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simple_thread.hh
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arch, cpu: Add support for flattening misc register indexes.
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2014-01-24 15:29:30 -06:00 |
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smt.hh
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includes: fix up code after sorting
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2011-04-15 10:44:14 -07:00 |
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static_inst.cc
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Decode: Pull instruction decoding out of the StaticInst class into its own.
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2011-09-09 02:30:01 -07:00 |
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static_inst.hh
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cpu: add a condition-code register class
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2013-10-15 14:22:44 -04:00 |
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static_inst_fwd.hh
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StaticInst: Merge StaticInst and StaticInstBase.
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2011-09-09 02:40:11 -07:00 |
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thread_context.cc
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cpu: add a condition-code register class
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2013-10-15 14:22:44 -04:00 |
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thread_context.hh
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arch, cpu: Add support for flattening misc register indexes.
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2014-01-24 15:29:30 -06:00 |
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thread_state.cc
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mem: Set the cache line size on a system level
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2013-07-18 08:31:16 -04:00 |
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thread_state.hh
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cpu: added assertions to ensure the correct proxies are used
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2012-07-10 22:51:53 -07:00 |
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timebuf.hh
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Move sched_list.hh and timebuf.hh from src/base to src/cpu.
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2011-01-03 14:35:47 -08:00 |
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translation.hh
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mem: track per-request latencies and access depths in the cache hierarchy
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2014-01-24 15:29:30 -06:00 |
