cpu: add consistent guarding to *_impl.hh files.

src/cpu/base_dyn_inst_impl.hh

@@ -40,6 +40,9 @@
  * Authors: Kevin Lim
  */
 
+#ifndef __CPU_BASE_DYN_INST_IMPL_HH__
+#define __CPU_BASE_DYN_INST_IMPL_HH__
+
 #include <iostream>
 #include <set>
 #include <sstream>
@@ -228,3 +231,5 @@ BaseDynInst<Impl>::eaSrcsReady()
 
     return true;
 }
+
+#endif//__CPU_BASE_DYN_INST_IMPL_HH__

src/cpu/checker/cpu_impl.hh

@@ -42,6 +42,9 @@
  *          Geoffrey Blake
  */
 
+#ifndef __CPU_CHECKER_CPU_IMPL_HH__
+#define __CPU_CHECKER_CPU_IMPL_HH__
+
 #include <list>
 #include <string>
 
@@ -684,3 +687,5 @@ Checker<Impl>::dumpInsts()
     }
 
 }
+
+#endif//__CPU_CHECKER_CPU_IMPL_HH__

src/cpu/o3/commit_impl.hh

@@ -40,6 +40,8 @@
  * Authors: Kevin Lim
  *          Korey Sewell
  */
+#ifndef __CPU_O3_COMMIT_IMPL_HH__
+#define __CPU_O3_COMMIT_IMPL_HH__
 
 #include <algorithm>
 #include <set>
@@ -1540,3 +1542,5 @@ DefaultCommit<Impl>::oldestReady()
         return InvalidThreadID;
     }
 }
+
+#endif//__CPU_O3_COMMIT_IMPL_HH__

src/cpu/o3/decode_impl.hh

@@ -40,6 +40,9 @@
  * Authors: Kevin Lim
  */
 
+#ifndef __CPU_O3_DECODE_IMPL_HH__
+#define __CPU_O3_DECODE_IMPL_HH__
+
 #include "arch/types.hh"
 #include "base/trace.hh"
 #include "config/the_isa.hh"
@@ -767,3 +770,5 @@ DefaultDecode<Impl>::decodeInsts(ThreadID tid)
         wroteToTimeBuffer = true;
     }
 }
+
+#endif//__CPU_O3_DECODE_IMPL_HH__

src/cpu/o3/dyn_inst_impl.hh

@@ -40,6 +40,9 @@
  * Authors: Kevin Lim
  */
 
+#ifndef __CPU_O3_DYN_INST_IMPL_HH__
+#define __CPU_O3_DYN_INST_IMPL_HH__
+
 #include "base/cp_annotate.hh"
 #include "cpu/o3/dyn_inst.hh"
 #include "sim/full_system.hh"
@@ -255,3 +258,4 @@ BaseO3DynInst<Impl>::syscall(int64_t callnum)
     }
 }
 
+#endif//__CPU_O3_DYN_INST_IMPL_HH__

src/cpu/o3/fetch_impl.hh

@@ -41,6 +41,9 @@
  *          Korey Sewell
  */
 
+#ifndef __CPU_O3_FETCH_IMPL_HH__
+#define __CPU_O3_FETCH_IMPL_HH__
+
 #include <algorithm>
 #include <cstring>
 #include <list>
@@ -1631,3 +1634,5 @@ DefaultFetch<Impl>::profileStall(ThreadID tid) {
              tid, fetchStatus[tid]);
     }
 }
+
+#endif//__CPU_O3_FETCH_IMPL_HH__

src/cpu/o3/iew_impl.hh

@@ -40,6 +40,9 @@
  * Authors: Kevin Lim
  */
 
+#ifndef __CPU_O3_IEW_IMPL_IMPL_HH__
+#define __CPU_O3_IEW_IMPL_IMPL_HH__
+
 // @todo: Fix the instantaneous communication among all the stages within
 // iew.  There's a clear delay between issue and execute, yet backwards
 // communication happens simultaneously.
@@ -1671,3 +1674,5 @@ DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst)
         }
     }
 }
+
+#endif//__CPU_O3_IEW_IMPL_IMPL_HH__

src/cpu/o3/inst_queue_impl.hh

@@ -42,6 +42,9 @@
  *          Korey Sewell
  */
 
+#ifndef __CPU_O3_INST_QUEUE_IMPL_HH__
+#define __CPU_O3_INST_QUEUE_IMPL_HH__
+
 #include <limits>
 #include <vector>
 
@@ -1508,3 +1511,5 @@ InstructionQueue<Impl>::dumpInsts()
         ++num;
     }
 }
+
+#endif//__CPU_O3_INST_QUEUE_IMPL_HH__

src/cpu/o3/lsq_impl.hh

@@ -40,6 +40,9 @@
  * Authors: Korey Sewell
  */
 
+#ifndef __CPU_O3_LSQ_IMPL_HH__
+#define __CPU_O3_LSQ_IMPL_HH__
+
 #include <algorithm>
 #include <list>
 #include <string>
@@ -658,3 +661,5 @@ LSQ<Impl>::dumpInsts() const
         thread[tid].dumpInsts();
     }
 }
+
+#endif//__CPU_O3_LSQ_IMPL_HH__

src/cpu/o3/lsq_unit_impl.hh

@@ -42,6 +42,9 @@
  *          Korey Sewell
  */
 
+#ifndef __CPU_O3_LSQ_UNIT_IMPL_HH__
+#define __CPU_O3_LSQ_UNIT_IMPL_HH__
+
 #include "arch/generic/debugfaults.hh"
 #include "arch/locked_mem.hh"
 #include "base/str.hh"
@@ -1289,3 +1292,5 @@ LSQUnit<Impl>::dumpInsts() const
 
     cprintf("\n");
 }
+
+#endif//__CPU_O3_LSQ_UNIT_IMPL_HH__

src/cpu/o3/mem_dep_unit_impl.hh

@@ -40,6 +40,9 @@
  * Authors: Kevin Lim
  */
 
+#ifndef __CPU_O3_MEM_DEP_UNIT_IMPL_HH__
+#define __CPU_O3_MEM_DEP_UNIT_IMPL_HH__
+
 #include <map>
 
 #include "cpu/o3/inst_queue.hh"
@@ -594,3 +597,5 @@ MemDepUnit<MemDepPred, Impl>::dumpLists()
     cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count);
 #endif
 }
+
+#endif//__CPU_O3_MEM_DEP_UNIT_IMPL_HH__

src/cpu/o3/rename_impl.hh

@@ -42,6 +42,9 @@
  *          Korey Sewell
  */
 
+#ifndef __CPU_O3_RENAME_IMPL_HH__
+#define __CPU_O3_RENAME_IMPL_HH__
+
 #include <list>
 
 #include "arch/isa_traits.hh"
@@ -1383,3 +1386,5 @@ DefaultRename<Impl>::dumpHistory()
         }
     }
 }
+
+#endif//__CPU_O3_RENAME_IMPL_HH__

src/cpu/o3/rob_impl.hh

@@ -41,6 +41,9 @@
  *          Korey Sewell
  */
 
+#ifndef __CPU_O3_ROB_IMPL_HH__
+#define __CPU_O3_ROB_IMPL_HH__
+
 #include <list>
 
 #include "cpu/o3/rob.hh"
@@ -560,3 +563,5 @@ ROB<Impl>::findInst(ThreadID tid, InstSeqNum squash_inst)
     }
     return NULL;
 }
+
+#endif//__CPU_O3_ROB_IMPL_HH__

src/cpu/o3/thread_context_impl.hh

@@ -42,6 +42,9 @@
  *          Korey Sewell
  */
 
+#ifndef __CPU_O3_THREAD_CONTEXT_IMPL_HH__
+#define __CPU_O3_THREAD_CONTEXT_IMPL_HH__
+
 #include "arch/kernel_stats.hh"
 #include "arch/registers.hh"
 #include "config/the_isa.hh"
@@ -297,6 +300,7 @@ O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
     conditionalSquash();
 }
 
+#endif//__CPU_O3_THREAD_CONTEXT_IMPL_HH__
 template <class Impl>
 void
 O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val)

src/cpu/ozone/back_end_impl.hh

@@ -28,6 +28,9 @@
  * Authors: Kevin Lim
  */
 
+#ifndef __CPU_OZONE_BACK_END_IMPL_HH__
+#define __CPU_OZONE_BACK_END_IMPL_HH__
+
 #include "cpu/ozone/back_end.hh"
 #include "encumbered/cpu/full/op_class.hh"
 
@@ -1912,3 +1915,5 @@ BackEnd<Impl>::dumpInsts()
         ++num;
     }
 }
+
+#endif//__CPU_OZONE_BACK_END_IMPL_HH__

src/cpu/ozone/cpu_impl.hh

@@ -30,6 +30,9 @@
  *          Nathan Binkert
  */
 
+#ifndef __CPU_OZONE_CPU_IMPL_HH__
+#define __CPU_OZONE_CPU_IMPL_HH__
+
 #include "arch/alpha/osfpal.hh"
 #include "arch/isa_traits.hh" // For MachInst
 #include "arch/kernel_stats.hh"
@@ -868,6 +871,8 @@ OzoneCPU<Impl>::OzoneTC::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
     }
 }
 
+#endif//__CPU_OZONE_CPU_IMPL_HH__
+
 template <class Impl>
 void
 OzoneCPU<Impl>::OzoneTC::setMiscReg(int misc_reg, const MiscReg &val)

src/cpu/ozone/dyn_inst_impl.hh

@@ -28,6 +28,9 @@
  * Authors: Kevin Lim
  */
 
+#ifndef __CPU_OZONE_DYN_INST_IMPL_HH__
+#define __CPU_OZONE_DYN_INST_IMPL_HH__
+
 #include "config/the_isa.hh"
 #include "cpu/ozone/dyn_inst.hh"
 #include "kern/kernel_stats.hh"
@@ -270,3 +273,5 @@ OzoneDynInst<Impl>::syscall(uint64_t &callnum)
 {
     this->cpu->syscall(callnum);
 }
+
+#endif//__CPU_OZONE_DYN_INST_IMPL_HH__

src/cpu/ozone/front_end_impl.hh

@@ -27,6 +27,8 @@
  *
  * Authors: Kevin Lim
  */
+#ifndef __CPU_OZONE_BACK_END_IMPL_HH__
+#define __CPU_OZONE_BACK_END_IMPL_HH__
 
 #include "arch/isa_traits.hh"
 #include "arch/utility.hh"
@@ -989,3 +991,5 @@ FrontEnd<Impl>::dumpInsts()
         buff_it++;
     }
 }
+
+#endif//__CPU_OZONE_BACK_END_IMPL_HH__

src/cpu/ozone/inorder_back_end_impl.hh

@@ -28,6 +28,9 @@
  * Authors: Kevin Lim
  */
 
+#ifndef __CPU_OZONE_INORDER_BACK_END_IMPL_HH__
+#define __CPU_OZONE_INORDER_BACK_END_IMPL_HH__
+
 #include "arch/types.hh"
 #include "config/the_isa.hh"
 #include "cpu/ozone/inorder_back_end.hh"
@@ -521,3 +524,4 @@ InorderBackEnd<Impl>::DCacheCompletionEvent::description() const
 {
     return "DCache completion";
 }
+#endif//__CPU_OZONE_INORDER_BACK_END_IMPL_HH__

src/cpu/ozone/inst_queue_impl.hh

@@ -28,6 +28,9 @@
  * Authors: Kevin Lim
  */
 
+#ifndef __CPU_OZONE_INST_QUEUE_IMPL_HH__
+#define __CPU_OZONE_INST_QUEUE_IMPL_HH__
+
 // Todo:
 // Current ordering allows for 0 cycle added-to-scheduled.  Could maybe fake
 // it; either do in reverse order, or have added instructions put into a
@@ -1342,3 +1345,5 @@ InstQueue<Impl>::dumpInsts()
 */
     }
 }
+
+#define//__CPU_OZONE_INST_QUEUE_IMPL_HH__

src/cpu/ozone/lsq_unit_impl.hh

@@ -27,6 +27,8 @@
  *
  * Authors: Kevin Lim
  */
+#ifndef __CPU_OZONE_LSQ_UNIT_IMPL_HH__
+#define __CPU_OZONE_LSQ_UNIT_IMPL_HH__
 
 #include "base/str.hh"
 #include "config/the_isa.hh"
@@ -839,3 +841,4 @@ OzoneLSQ<Impl>::decrLdIdx(int &load_idx)
     if (--load_idx < 0)
         load_idx += LQEntries;
 }
+#endif//__CPU_OZONE_LSQ_UNIT_IMPL_HH__

src/cpu/ozone/lw_back_end_impl.hh

@@ -27,6 +27,8 @@
  *
  * Authors: Kevin Lim
  */
+#ifndef __CPU_OZONE_LW_BACK_END_IMPL_HH__
+#define __CPU_OZONE_LW_BACK_END_IMPL_HH__
 
 #include "config/the_isa.hh"
 #include "cpu/checker/cpu.hh"
@@ -1672,3 +1674,4 @@ LWBackEnd<Impl>::dumpInsts()
     }
     cprintf("\n");
 }
+#endif//__CPU_OZONE_LW_BACK_END_IMPL_HH__

src/cpu/ozone/lw_lsq_impl.hh

@@ -28,6 +28,9 @@
  * Authors: Kevin Lim
  */
 
+#ifndef __CPU_OZONE_LW_LSQ_IMPL_HH__
+#define __CPU_OZONE_LW_LSQ_IMPL_HH__
+
 #include "base/str.hh"
 #include "config/the_isa.hh"
 #include "cpu/checker/cpu.hh"
@@ -961,3 +964,5 @@ OzoneLWLSQ<Impl>::takeOverFrom(ThreadContext *old_tc)
 
     blockedLoadSeqNum = 0;
 }
+
+#endif//__CPU_OZONE_LW_LSQ_IMPL_HH__

src/cpu/ozone/rename_table_impl.hh

@@ -27,6 +27,8 @@
  *
  * Authors: Kevin Lim
  */
+#ifndef __CPU_OZONE_RENAME_TABLE_IMPL_HH__
+#define __CPU_OZONE_RENAME_TABLE_IMPL_HH__
 
 #include <cstdlib>  // Not really sure what to include to get NULL
 
@@ -52,3 +54,5 @@ RenameTable<Impl>::copyFrom(const RenameTable<Impl> &table_to_copy)
         table[i] = table_to_copy.table[i];
     }
 }
+
+#endif//__CPU_OZONE_RENAME_TABLE_IMPL_HH__

src/cpu/pred/bpred_unit_impl.hh

@@ -42,6 +42,9 @@
  * Authors: Kevin Lim
  */
 
+#ifndef __CPU_PRED_BPRED_UNIT_IMPL_HH__
+#define __CPU_PRED_BPRED_UNIT_IMPL_HH__
+
 #include <algorithm>
 
 #include "arch/isa_traits.hh"
@@ -534,3 +537,5 @@ BPredUnit::dump()
         }
     }
 }
+
+#endif//__CPU_PRED_BPRED_UNIT_IMPL_HH__

src/mem/cache/cache_impl.hh

@@ -46,6 +46,9 @@
  *          Andreas Sandberg
  */
 
+#ifndef __MEM_CACHE_CACHE_IMPL_HH__
+#define __MEM_CACHE_CACHE_IMPL_HH__
+
 /**
  * @file
  * Cache definitions.
@@ -1899,3 +1902,5 @@ MemSidePort::MemSidePort(const std::string &_name, Cache<TagStore> *_cache,
       _queue(*_cache, *this, _label), cache(_cache)
 {
 }
+
+#endif//__MEM_CACHE_CACHE_IMPL_HH__