| .. |
|
checker
|
x86 isa: This patch attempts an implementation at mwait.
|
2014-11-06 05:42:22 -06:00 |
|
inorder
|
mem: Add const getters for write packet data
|
2014-12-02 06:07:36 -05:00 |
|
kvm
|
Let other objects set up memory like regions in a KVM VM.
|
2014-12-09 21:53:44 -08:00 |
|
minor
|
minor: fixed LSQ MasterPortID
|
2015-01-03 17:51:48 -06:00 |
|
nocpu
|
arch, cpu: Factor out the ExecContext into a proper base class
|
2014-09-03 07:42:22 -04:00 |
|
o3
|
cpu: Only check for PC events on instruction boundaries.
|
2014-12-05 01:47:35 -08:00 |
|
pred
|
cpu: Add branch predictor PMU probe points
|
2014-10-16 05:49:40 -04:00 |
|
simple
|
cpu: Only check for PC events on instruction boundaries.
|
2014-12-05 01:47:35 -08:00 |
|
testers
|
mem: Assume all dynamic packet data is array allocated
|
2014-12-02 06:07:43 -05:00 |
|
activity.cc
|
Fix: Address a few benign memory leaks
|
2012-07-09 12:35:30 -04:00 |
|
activity.hh
|
cpu: Useful getters for ActivityRecorder
|
2014-05-09 18:58:48 -04:00 |
|
base.cc
|
cpu: fix RetiredStores probe point
|
2015-01-10 14:30:53 -06:00 |
|
base.hh
|
x86 isa: This patch attempts an implementation at mwait.
|
2014-11-06 05:42:22 -06:00 |
|
base_dyn_inst.hh
|
x86 isa: This patch attempts an implementation at mwait.
|
2014-11-06 05:42:22 -06:00 |
|
base_dyn_inst_impl.hh
|
arch: Use const StaticInstPtr references where possible
|
2014-09-27 09:08:36 -04:00 |
|
BaseCPU.py
|
mem: Rename Bus to XBar to better reflect its behaviour
|
2014-09-20 17:18:32 -04:00 |
|
CheckerCPU.py
|
sim: Include object header files in SWIG interfaces
|
2012-11-02 11:32:01 -05:00 |
|
cpuevent.cc
|
Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.
|
2006-06-06 17:32:21 -04:00 |
|
cpuevent.hh
|
includes: sort all includes
|
2011-04-15 10:44:06 -07:00 |
|
decode_cache.hh
|
ISA,CPU: Generalize and split out the components of the decode cache.
|
2012-05-26 13:45:12 -07:00 |
|
dummy_checker.cc
|
sim: Add the notion of clock domains to all ClockedObjects
|
2013-06-27 05:49:49 -04:00 |
|
dummy_checker.hh
|
cpu: Add header files for checker CPUs
|
2012-11-02 11:32:01 -05:00 |
|
DummyChecker.py
|
cpu: Make checker CPUs inherit from CheckerCPU in the Python hierarchy
|
2013-02-15 17:40:08 -05:00 |
|
exec_context.cc
|
arch, cpu: Factor out the ExecContext into a proper base class
|
2014-09-03 07:42:22 -04:00 |
|
exec_context.hh
|
x86 isa: This patch attempts an implementation at mwait.
|
2014-11-06 05:42:22 -06:00 |
|
exetrace.cc
|
arch: Use const StaticInstPtr references where possible
|
2014-09-27 09:08:36 -04:00 |
|
exetrace.hh
|
arch: Use const StaticInstPtr references where possible
|
2014-09-27 09:08:36 -04:00 |
|
ExeTracer.py
|
sim: Include object header files in SWIG interfaces
|
2012-11-02 11:32:01 -05:00 |
|
func_unit.cc
|
params: Deprecate old-style constructors; update most SimObject constructors.
|
2007-08-30 15:16:59 -04:00 |
|
func_unit.hh
|
Param: Transition to Cycles for relevant parameters
|
2012-09-07 12:34:38 -04:00 |
|
FuncUnit.py
|
sim: Include object header files in SWIG interfaces
|
2012-11-02 11:32:01 -05:00 |
|
inst_seq.hh
|
build: fix compile problems pointed out by gcc 4.4
|
2009-11-04 16:57:01 -08:00 |
|
inteltrace.cc
|
gcc: Clean-up of non-C++0x compliant code, first steps
|
2012-03-19 06:36:09 -04:00 |
|
inteltrace.hh
|
sim: Include object header files in SWIG interfaces
|
2012-11-02 11:32:01 -05:00 |
|
IntelTrace.py
|
sim: Include object header files in SWIG interfaces
|
2012-11-02 11:32:01 -05:00 |
|
intr_control.cc
|
SE/FS: Get rid of FULL_SYSTEM in the CPU directory.
|
2011-11-18 01:33:28 -08:00 |
|
intr_control.hh
|
arch: Header clean up for NOISA resurrection
|
2013-09-04 13:22:55 -04:00 |
|
intr_control_noisa.cc
|
arch: Resurrect the NOISA build target and rename it NULL
|
2013-09-04 13:22:57 -04:00 |
|
IntrControl.py
|
sim: Include object header files in SWIG interfaces
|
2012-11-02 11:32:01 -05:00 |
|
legiontrace.cc
|
Decoder: Remove the thread context get/set from the decoder.
|
2013-01-04 19:00:45 -06:00 |
|
legiontrace.hh
|
scons: Add warning for missing declarations
|
2013-02-19 05:56:07 -05:00 |
|
LegionTrace.py
|
sim: Include object header files in SWIG interfaces
|
2012-11-02 11:32:01 -05:00 |
|
m5legion_interface.h
|
add fsr to the list of registers we are interested in
|
2007-01-30 18:27:04 -05:00 |
|
nativetrace.cc
|
trace: reimplement the DTRACE function so it doesn't use a vector
|
2011-04-15 10:44:32 -07:00 |
|
nativetrace.hh
|
clang: Enable compiling gem5 using clang 2.9 and 3.0
|
2012-01-31 12:05:52 -05:00 |
|
NativeTrace.py
|
sim: Include object header files in SWIG interfaces
|
2012-11-02 11:32:01 -05:00 |
|
op_class.hh
|
CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.
|
2010-11-15 14:04:04 -06:00 |
|
pc_event.cc
|
arm: Enable support for triggering a sim panic on kernel panics
|
2013-04-22 13:20:31 -04:00 |
|
pc_event.hh
|
arm: Enable support for triggering a sim panic on kernel panics
|
2013-04-22 13:20:31 -04:00 |
|
profile.cc
|
includes: sort all includes
|
2011-04-15 10:44:06 -07:00 |
|
profile.hh
|
arch: Use const StaticInstPtr references where possible
|
2014-09-27 09:08:36 -04:00 |
|
quiesce_event.cc
|
trace: reimplement the DTRACE function so it doesn't use a vector
|
2011-04-15 10:44:32 -07:00 |
|
quiesce_event.hh
|
clang: Enable compiling gem5 using clang 2.9 and 3.0
|
2012-01-31 12:05:52 -05:00 |
|
reg_class.cc
|
cpu: add a condition-code register class
|
2013-10-15 14:22:44 -04:00 |
|
reg_class.hh
|
cpu: add a condition-code register class
|
2013-10-15 14:22:44 -04:00 |
|
SConscript
|
x86 isa: This patch attempts an implementation at mwait.
|
2014-11-06 05:42:22 -06:00 |
|
simple_thread.cc
|
arm: Fixes based on UBSan and static analysis
|
2014-11-14 03:53:51 -05:00 |
|
simple_thread.hh
|
alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivate
|
2014-09-20 17:18:35 -04:00 |
|
smt.hh
|
includes: fix up code after sorting
|
2011-04-15 10:44:14 -07:00 |
|
static_inst.cc
|
cpu: Add flag name printing to StaticInst
|
2014-05-09 18:58:47 -04:00 |
|
static_inst.hh
|
arm: Fixes based on UBSan and static analysis
|
2014-11-14 03:53:51 -05:00 |
|
static_inst_fwd.hh
|
cpu: Don't forward declare RefCountingPtr
|
2014-08-13 06:57:26 -04:00 |
|
StaticInstFlags.py
|
cpu: Add flag name printing to StaticInst
|
2014-05-09 18:58:47 -04:00 |
|
thread_context.cc
|
cpu: add a condition-code register class
|
2013-10-15 14:22:44 -04:00 |
|
thread_context.hh
|
alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivate
|
2014-09-20 17:18:35 -04:00 |
|
thread_state.cc
|
arm: Fixes based on UBSan and static analysis
|
2014-11-14 03:53:51 -05:00 |
|
thread_state.hh
|
cpu, arm: Allow the specification of a socket field
|
2014-05-09 18:58:46 -04:00 |
|
timebuf.hh
|
cpu: Timebuf const accessors
|
2014-05-09 18:58:47 -04:00 |
|
timing_expr.cc
|
arch: Use const StaticInstPtr references where possible
|
2014-09-27 09:08:36 -04:00 |
|
timing_expr.hh
|
arch: Use const StaticInstPtr references where possible
|
2014-09-27 09:08:36 -04:00 |
|
TimingExpr.py
|
cpu: `Minor' in-order CPU model
|
2014-07-23 16:09:04 -05:00 |
|
translation.hh
|
arch: Pass faults by const reference where possible
|
2014-09-19 10:35:18 -04:00 |
