minor: fixed LSQ MasterPortID
Minor was reporting the data cache access as ".inst" accesses. This just switches the MasterPortID to dataMasterPortId. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
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@ -1503,7 +1503,7 @@ LSQ::pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data,
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request->request.setThreadContext(cpu.cpuId(), /* thread id */ 0);
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request->request.setVirt(0 /* asid */,
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addr, size, flags, cpu.instMasterId(),
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addr, size, flags, cpu.dataMasterId(),
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/* I've no idea why we need the PC, but give it */
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inst->pc.instAddr());
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