Commit graph

591 commits

Author SHA1 Message Date
Ali Saidi
e1b9c8c169 ARM: Fix configuration files for bare-metal binaries. 2013-08-26 10:58:06 -05:00
Nilay Vaish
c4e7e18eeb ruby: add option for number of transitions per cycle
The number of transitions per cycle that a controller can carry out is
a proxy for the number of ports that a controller has. This value is
currently 32 which is way too high. The patch introduces an option
for the number of ports and uses this option in the protocol files
to set the number of transitions. The default value is being set to
4. None of the se regressions change. Ruby stats for the fs regression
change and are being updated.
2013-08-20 11:32:31 -05:00
Andreas Hansson
c26911013c config: Command line support for multi-channel memory
This patch adds support for specifying multi-channel memory
configurations on the command line, e.g. 'se/fs.py
--mem-type=ddr3_1600_x64 --mem-channels=4'. To enable this, it
enhances the functionality of MemConfig and moves the existing
makeMultiChannel class method from SimpleDRAM to the support scripts.

The se/fs.py example scripts are updated to make use of the new
feature.
2013-08-19 03:52:34 -04:00
Andreas Hansson
49d88f08b0 mem: Change AbstractMemory defaults to match the common case
This patch changes the default parameter value of conf_table_reported
to match the common case. It also simplifies the regression and config
scripts to reflect this change.
2013-08-19 03:52:33 -04:00
Akash Bagdia
e7e17f92db power: Add voltage domains to the clock domains
This patch adds the notion of voltage domains, and groups clock
domains that operate under the same voltage (i.e. power supply) into
domains. Each clock domain is required to be associated with a voltage
domain, and the latter requires the voltage to be explicitly set.

A voltage domain is an independently controllable voltage supply being
provided to section of the design. Thus, if you wish to perform
dynamic voltage scaling on a CPU, its clock domain should be
associated with a separate voltage domain.

The current implementation of the voltage domain does not take into
consideration cases where there are derived voltage domains running at
ratio of native voltage domains, as with the case where there can be
on-chip buck/boost (charge pumps) voltage regulation logic.

The regression and configuration scripts are updated with a generic
voltage domain for the system, and one for the CPUs.
2013-08-19 03:52:28 -04:00
Andreas Hansson
a8480fe1c3 config: Move the memory instantiation outside FSConfig
This patch moves the instantiation of the memory controller outside
FSConfig and instead relies on the mem_ranges to pass the information
to the caller (e.g. fs.py or one of the regression scripts). The main
motivation for this change is to expose the structural composition of
the memory system and allow more tuning and configuration without
adding a large number of options to the makeSystem functions.

The patch updates the relevant example scripts to maintain the current
functionality. As the order that ports are connected to the memory bus
changes (in certain regresisons), some bus stats are shuffled
around. For example, what used to be layer 0 is now layer 1.

Going forward, options will be added to support the addition of
multi-channel memory controllers.
2013-08-19 03:52:27 -04:00
Joel Hestness
7aa67f42cb Configs: Fix up maxtick and maxtime
This patch contains three fixes to max tick options handling in Options.py and
Simulation.py:

 1) Since the global simulator frequency isn't bound until m5.instantiate()
is called, the maxtick resolution needs to happen after this call, since
changes to the global frequency will cause m5.simulate() to misinterpret the
maxtick value. Shuffling this also requires tweaking the checkpoint directory
handling to signal the checkpoint restore tick back to run().  Fixing this
completely and correctly will require storing the simulation frequency into
checkpoints, which is beyond the scope of this patch.

 2) The maxtick option in Options.py was defaulted to MaxTicks, so the old code
would always skip over the maxtime part of the conditionals at the beginning
of run(). Change the maxtick default to None, and set the maxtick local
variable in run() appropriately.

 3) To clarify whether max ticks settings are relative or absolute, split the
maxtick option into separate options, for relative and absolute. Ensure that
these two options and the maxtime option are handled appropriately to set the
maxtick variable in Simulation.py.
2013-07-18 14:46:54 -05:00
Andreas Hansson
c20105c2ff config: Update script to set cache line size on system
This patch changes the config scripts such that they do not set the
cache line size per cache instance, but rather for the system as a
whole.
2013-07-18 08:31:19 -04:00
Nilay Vaish
516b7849e8 configs: rearrange the available options in Options.py
It also changes the instantiation of physmem in se.py so as to make
use of the memory size supplied by the mem_size option.
2013-06-28 21:42:26 -05:00
Nilay Vaish
62a93f0bf0 ruby: check for compatibility between mem size and num dirs
The configuration scripts provided for ruby assume that the available
physical memory is equally distributed amongst the directory controllers.
But there is no check to ensure this assumption has been adhered to. This
patch adds the required check.
2013-06-28 21:36:11 -05:00
Akash Bagdia
7d7ab73862 sim: Add the notion of clock domains to all ClockedObjects
This patch adds the notion of source- and derived-clock domains to the
ClockedObjects. As such, all clock information is moved to the clock
domain, and the ClockedObjects are grouped into domains.

The clock domains are either source domains, with a specific clock
period, or derived domains that have a parent domain and a divider
(potentially chained). For piece of logic that runs at a derived clock
(a ratio of the clock its parent is running at) the necessary derived
clock domain is created from its corresponding parent clock
domain. For now, the derived clock domain only supports a divider,
thus ensuring a lower speed compared to its parent. Multiplier
functionality implies a PLL logic that has not been modelled yet
(create a separate clock instead).

The clock domains should be used as a mechanism to provide a
controllable clock source that affects clock for every clocked object
lying beneath it. The clock of the domain can (in a future patch) be
controlled by a handler responsible for dynamic frequency scaling of
the respective clock domains.

All the config scripts have been retro-fitted with clock domains. For
the System a default SrcClockDomain is created. For CPUs that run at a
different speed than the system, there is a seperate clock domain
created. This domain incorporates the CPU and the associated
caches. As before, Ruby runs under its own clock domain.

The clock period of all domains are pre-computed, such that no virtual
functions or multiplications are needed when calling
clockPeriod. Instead, the clock period is pre-computed when any
changes occur. For this to be possible, each clock domain tracks its
children.
2013-06-27 05:49:49 -04:00
Akash Bagdia
597d2aa3a6 config: Rename clock option to Ruby clock
This patch changes the 'clock' option to 'ruby-clock' as it is only
used by Ruby.
2013-06-27 05:49:49 -04:00
Akash Bagdia
076d04a653 config: Add a system clock command-line option
This patch adds a 'sys_clock' command-line option and use it to assign
clocks to the system during instantiation.

As part of this change, the default clock in the System class is
removed and whenever a system is instantiated a system clock value
must be set. A default value is provided for the command-line option.

The configs and tests are updated accordingly.
2013-06-27 05:49:49 -04:00
Akash Bagdia
4459b30525 config: Add a CPU clock command-line option
This patch adds a 'cpu_clock' command-line option and uses the value
to assign clocks to components running at the CPU speed (L1 and L2
including the L2-bus). The configuration scripts are updated
accordingly.

The 'clock' option is left unchanged in this patch as it is still used
by a number of components. In follow-on patches the latter will be
disambiguated further.
2013-06-27 05:49:49 -04:00
Akash Bagdia
7eccb1b779 config: Remove redundant explicit setting of default clocks
This patch removes the explicit setting of the clock period for
certain instances of CoherentBus, NonCoherentBus and IOCache where the
specified clock is same as the default value of the system clock. As
all the values used are the defaults, there are no performance
changes. There are similar cases where the toL2Bus is set to use the
parent CPU clock which is already the default behaviour.

The main motivation for these simplifications is to ease the
introduction of clock domains.
2013-06-27 05:49:49 -04:00
Nilay Vaish
be981772b9 config: Do not instantiate membus when using ruby
This patch moves the instantiation of system.membus in se.py to the area of
code where classic memory system has been dealt with. Ruby does not require
this bus and hence it should not be instantiated.
2013-06-13 07:24:25 -05:00
Andreas Sandberg
d989a3ad50 config: Add missing CPUs to --restore-with-cpu
The --restore-with-cpu option didn't use CpuConfig.cpu_names() to
determine which CPU names are valid, instead it used a static list of
known CPU names. This changeset makes the option parsing code use the
CPU list from the CpuConfig module instead.
2013-06-03 13:40:05 +02:00
Andreas Hansson
3bc4ecdcb4 mem: More descriptive DRAM config names
This patch changes the class names of the variuos DRAM configurations
to better reflect what memory they are based on. The speed and
interface width is now part of the name, and also the alias that is
used to select them on the command line.

Some minor changes are done to the actual parameters, to better
reflect the named configurations. As a result of these changes the
regressions change slightly and the stats will be bumped in a separate
patch.
2013-05-30 12:54:14 -04:00
Andreas Hansson
bf6291460d mem: Add a LPDDR3-1600 configuration
This patch adds a typical (leaning towards fast) LPDDR3 configuration
based on publically available data. As expected, it looks very similar
to the LPDDR2-S4 configuration, only with a slightly lower burst time.
2013-05-30 12:53:56 -04:00
Andreas Hansson
88aa7755f4 mem: Avoid explicitly zeroing the memory backing store
This patch removes the explicit memset as it is redundant and causes
the simulator to touch the entire space, forcing the host system to
allocate the pages.

Anonymous pages are mapped on the first access, and the page-fault
handler is responsible for zeroing them. Thus, the pages are still
zeroed, but we avoid touching the entire allocated space which enables
us to use much larger memory sizes as long as not all the memory is
actually used.
2013-05-30 12:53:54 -04:00
Nilay Vaish
4ef466cc8a ruby: moesi hammer: cosmetic changes
Updates copyright years, removes space at the end of lines, shortens
variable names.
2013-05-21 11:32:45 -05:00
Nilay Vaish
09d5bc7e6f ruby: mesi cmp directory: cosmetic changes
Updates copyright years, removes space at the end of lines, shortens
variable names.
2013-05-21 11:32:38 -05:00
Nilay Vaish
bd3d1955da ruby: moesi cmp token: cosmetic changes
Updates copyright years, removes space at the end of lines, shortens
variable names.
2013-05-21 11:32:24 -05:00
Nilay Vaish
e7ce518168 ruby: moesi cmp directory: cosmetic changes
Updates copyright years, removes space at the end of lines, shortens
variable names.
2013-05-21 11:32:15 -05:00
Nilay Vaish
9bc75e3c58 configs: ruby: pass the option use_map to directory controller
The option was not being passed to directory controllers for the protocols
MOESI_CMP_token and MOESI_CMP_directory. This was resulting in an error
while instantiating the directory controller as it tries to access the
wrong type of memory.
2013-05-21 11:32:08 -05:00
Anthony Gutierrez
d3c33d91b6 cpu: remove local/globalHistoryBits params from branch pred
having separate params for the local/globalHistoryBits and the
local/globalPredictorSize can lead to inconsistencies if they
are not carefully set. this patch dervies the number of bits
necessary to index into the local/global predictors based on
their size.

the value of the localHistoryTableSize for the ARM O3 CPU has been
increased to 1024 from 64, which is more accurate for an A15 based
on some correlation against A15 hardware.
2013-05-14 18:39:47 -04:00
Marco Elver
0c57194a09 config: Fix mem-type option not used in ruby_fs script
This fixes missing mem-type arguments to makeLinuxAlphaRubySystem and
makeLinuxX86System after a recent changeset allowing mem-type to be
configured via options missed fixing these calls.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-04-23 11:56:48 -05:00
Andreas Hansson
3477d60d5c config: Add a mem-type config option to se/fs scripts
This patch enables selection of the memory controller class through a
mem-type command-line option. Behind the scenes, this option is
treated much like the cpu-type, and a similar framework is used to
resolve the valid options, and translate the short-hand description to
a valid class.

The regression scripts are updated with a hardcoded memory class for
the moment. The best solution going forward is probably to get the
memory out of the makeSystem functions, but Ruby complicates things as
it does not connect the memory controller to the membus.

--HG--
rename : configs/common/CpuConfig.py => configs/common/MemConfig.py
2013-04-22 13:20:33 -04:00
Andreas Sandberg
7865d6e838 config: Add a KVM VM to systems with KVM CPUs
KVM-based CPUs need a KVM VM object in the system to manage
system-global KVM stuff (VM creation, interrupt delivery, memory
managment, etc.). This changeset adds a VM to the system if KVM has
been enabled at compile time (the BaseKvmCPU object exists) and a
KVM-based CPU has been selected at runtime.
2013-04-22 13:20:32 -04:00
Dam Sunwoo
2c1e344313 cpu: generate SimPoint basic block vector profiles
This patch is based on http://reviews.m5sim.org/r/1474/ originally written by
Mitch Hayenga. Basic block vectors are generated (simpoint.bb.gz in simout
folder) based on start and end addresses of basic blocks.

Some comments to the original patch are addressed and hooks are added to create
and resume from checkpoints based on instruction counts dictated by external
SimPoint analysis tools.

SimPoint creation/resuming options will be implemented as a separate patch.
2013-04-22 13:20:31 -04:00
Nilay Vaish
407b1a77c8 config: ruby network test: remove piobus check 2013-04-17 16:06:24 -05:00
Joel Hestness
82c6734f6b Configs: Fix handling of maxtick and take_checkpoints
In Simulation.py, calls to m5.simulate(num_ticks) will run the simulated system
for num_ticks after the current tick. Fix calls to m5.simulate in
scriptCheckpoints() and benchCheckpoints() to appropriately handle the maxticks
variable.
2013-04-09 16:25:30 -05:00
Anthony Gutierrez
7fb55b98cc rcs scripts: remove bbench.rcS
this run script shouldn't be used; bbench-ics.rcS or bbench-gb.rcS
should be used instead.
2013-04-02 12:46:49 -04:00
Nilay Vaish
433cab9d95 x86: create space in bios memory map
As of now, we mark the top 1MB of memory space as unusable. Part of
it is actually usable and is required to be marked so by some of the
newer versions of linux kernel. This patch marks the top 639KB as usable.
This value was chosen by looking at QEMU's output for bios memory map.
2013-03-28 09:34:15 -05:00
Nilay Vaish
546ffb2d6d config: return exit event instead of cause
changeset: a4739b6f799d made some changes that where an exit event
should have been returned in place of exit cause. This patch corrects
the error.
2013-03-22 17:31:24 -05:00
Nilay Vaish
5aa43e130a ruby: convert Topology to regular class
The Topology class in Ruby does not need to inherit from SimObject class.
This patch turns it into a regular class. The topology object is now created
in the constructor of the Network class. All the parameters for the topology
class have been moved to the network class.
2013-03-22 15:53:23 -05:00
Nilay Vaish
2d50127642 ruby: network: move routers from topology to network 2013-03-22 15:53:22 -05:00
Nilay Vaish
c061819890 ruby: remove the functional copy of memory in se mode
This patch removes the functional copy of the memory that was maintained in
the se mode. Now ruby itself will provide the data.
2013-03-06 21:53:57 -06:00
Nilay Vaish
e8802fa127 ruby: garnet: fixed: implement functional access 2013-03-06 21:53:16 -06:00
Ali Saidi
82cf1565d0 config: Fix --prog-interval command line option 2013-02-20 08:18:22 -05:00
Anthony Gutierrez
21aa950318 options: add command line option for dtb file 2013-02-15 18:48:59 -05:00
Andreas Sandberg
1c7aa665bf config: Remove O3 dependencies
The default cache configuration script currently import the O3_ARM_v7a
model configuration, which depends on the O3 CPU. This breaks if gem5
has been compiled without O3 support. This changeset removes the
dependency by only importing the model if it is requested by the
user. As a bonus, it actually removes some code duplication in the
configuration scripts.
2013-02-15 17:40:08 -05:00
Andreas Sandberg
e5dca84c3f config: Move CPU handover logic to m5.switchCpus()
CPU switching consists of the following steps:
 1. Drain the system
 2. Switch out old CPUs (cpu.switchOut())
 3. Change the system timing mode to the mode the new CPUs require
 4. Flush caches if switching to hardware virtualization
 5. Inform new CPUs of the handover (cpu.takeOverFrom())
 6. Resume the system

m5.switchCpus() previously only did step 2 & 5. Since information
about the new processors' memory system requirements is now exposed,
do all of the steps above.

This patch adds automatic memory system switching and flush (if
needed) to switchCpus(). Additionally, it adds optional draining to
switchCpus(). This has the following implications:

* changeToTiming and changeToAtomic are no longer needed, so they have
  been removed.

* changeMemoryMode is only used internally, so it is has been renamed
  to be private.

* switchCpus requires a reference to the system containing the CPUs as
  its first parameter.

WARNING: This changeset breaks compatibility with existing
configuration scripts since it changes the signature of
m5.switchCpus().
2013-02-15 17:40:08 -05:00
Andreas Sandberg
e9f66dceac config: Cleanup CPU configuration
The CPUs supported by the configuration scripts used to be
hard-coded. This was not ideal for several reasons. For example, the
configuration scripts depend on all CPU models even though only a
subset might have been compiled.

This changeset adds a new module to the configuration scripts that
automatically discovers the available CPU models from the compiled
SimObjects. As a nice bonus, the use of introspection allows us to
automatically generate a list of available CPU models suitable for
printing. This list is augmented with the Python doc string from the
underlying class if available.
2013-02-15 17:40:08 -05:00
Andreas Sandberg
7cd1fd4324 cpu: Add CPU metadata om the Python classes
The configuration scripts currently hard-code the requirements of each
CPU. This is clearly not optimal as it makes writing new configuration
scripts painful and adding new CPU models requires existing scripts to
be updated. This patch adds the following class methods to the base
CPU and all relevant CPUs:

 * memory_mode -- Return a string describing the current memory mode
                  (invalid/atomic/timing).

 * require_caches -- Does the CPU model require caches?

 * support_take_over -- Does the CPU support CPU handover?
2013-02-15 17:40:08 -05:00
Andreas Sandberg
6155400421 config: Don't call sys.exit in interactive mode in run()
The run() method in Simulation.py used to call sys.exit() when the
simulator exits. This is undesirable when user has requested the
simulator to be run in interactive mode since it causes the simulator
to exit rather than entering the interactive Python environment.
2013-02-10 13:23:54 +01:00
Andreas Hansson
c4898b15bc mem: Add DDR3 and LPDDR2 DRAM controller configurations
This patch moves the default DRAM parameters from the SimpleDRAM class
to two different subclasses, one for DDR3 and one for LPDDR2. More can
be added as we go forward.

The regressions that previously used the SimpleDRAM are now using
SimpleDDR3 as this is the most similar configuration.
2013-01-31 07:49:14 -05:00
Nilay Vaish ext:(%2C%20Timothy%20Jones%20%3Ctimothy.jones%40cl.cam.ac.uk%3E)
dbeabedaf0 branch predictor: move out of o3 and inorder cpus
This patch moves the branch predictor files in the o3 and inorder directories
to src/cpu/pred. This allows sharing the branch predictor across different
cpu models.

This patch was originally posted by Timothy Jones in July 2010
but never made it to the repository.

--HG--
rename : src/cpu/o3/bpred_unit.cc => src/cpu/pred/bpred_unit.cc
rename : src/cpu/o3/bpred_unit.hh => src/cpu/pred/bpred_unit.hh
rename : src/cpu/o3/bpred_unit_impl.hh => src/cpu/pred/bpred_unit_impl.hh
rename : src/cpu/o3/sat_counter.hh => src/cpu/pred/sat_counter.hh
2013-01-24 12:28:51 -06:00
Malek Musleh
3137557cad config: move ruby objects under ruby_system in obj hierarchy
This patch moves the contollers to be children of the ruby_system instead of
'system' under the python object hierarchy. This is so that these objects
can inherit some of the ruby_system's parameter values without resorting to
calling a global system pointer during run-time.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-01-14 10:05:14 -06:00
Ali Saidi
fe3fbe624e config: Fix issue with changeset: a4739b6f799d. 2013-01-08 17:12:22 -05:00