ruby: mesi cmp directory: cosmetic changes
Updates copyright years, removes space at the end of lines, shortens variable names.
This commit is contained in:
Nilay Vaish
parent
bd3d1955da
commit
09d5bc7e6f
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@ -91,8 +91,8 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
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l1_cntrl = L1Cache_Controller(version = i,
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cntrl_id = cntrl_count,
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L1IcacheMemory = l1i_cache,
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L1DcacheMemory = l1d_cache,
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L1Icache = l1i_cache,
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L1Dcache = l1d_cache,
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l2_select_num_bits = l2_bits,
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send_evictions = (
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options.cpu_type == "detailed"),
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@ -132,7 +132,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
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l2_cntrl = L2Cache_Controller(version = i,
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cntrl_id = cntrl_count,
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L2cacheMemory = l2_cache,
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L2cache = l2_cache,
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ruby_system = ruby_system)
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exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
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@ -1,6 +1,5 @@
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/*
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* Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
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* Copyright (c) 1999-2013 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -29,8 +28,8 @@
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machine(L1Cache, "MESI Directory L1 Cache CMP")
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: Sequencer * sequencer,
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CacheMemory * L1IcacheMemory,
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CacheMemory * L1DcacheMemory,
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CacheMemory * L1Icache,
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CacheMemory * L1Dcache,
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Prefetcher * prefetcher = 'NULL',
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int l2_select_num_bits,
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Cycles l1_request_latency = 2,
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@ -155,27 +154,27 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
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// inclusive cache returns L1 entries only
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Entry getCacheEntry(Address addr), return_by_pointer="yes" {
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Entry L1Dcache_entry := static_cast(Entry, "pointer", L1DcacheMemory[addr]);
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Entry L1Dcache_entry := static_cast(Entry, "pointer", L1Dcache[addr]);
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if(is_valid(L1Dcache_entry)) {
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return L1Dcache_entry;
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}
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Entry L1Icache_entry := static_cast(Entry, "pointer", L1IcacheMemory[addr]);
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Entry L1Icache_entry := static_cast(Entry, "pointer", L1Icache[addr]);
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return L1Icache_entry;
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}
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Entry getL1DCacheEntry(Address addr), return_by_pointer="yes" {
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Entry L1Dcache_entry := static_cast(Entry, "pointer", L1DcacheMemory[addr]);
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Entry L1Dcache_entry := static_cast(Entry, "pointer", L1Dcache[addr]);
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return L1Dcache_entry;
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}
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Entry getL1ICacheEntry(Address addr), return_by_pointer="yes" {
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Entry L1Icache_entry := static_cast(Entry, "pointer", L1IcacheMemory[addr]);
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Entry L1Icache_entry := static_cast(Entry, "pointer", L1Icache[addr]);
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return L1Icache_entry;
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}
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State getState(TBE tbe, Entry cache_entry, Address addr) {
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assert((L1DcacheMemory.isTagPresent(addr) && L1IcacheMemory.isTagPresent(addr)) == false);
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assert((L1Dcache.isTagPresent(addr) && L1Icache.isTagPresent(addr)) == false);
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if(is_valid(tbe)) {
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return tbe.TBEState;
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@ -186,7 +185,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
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}
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void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
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assert((L1DcacheMemory.isTagPresent(addr) && L1IcacheMemory.isTagPresent(addr)) == false);
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assert((L1Dcache.isTagPresent(addr) && L1Icache.isTagPresent(addr)) == false);
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// MUST CHANGE
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if(is_valid(tbe)) {
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@ -294,7 +293,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
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L1Dcache_entry, L1_TBEs[in_msg.LineAddress]);
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}
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if (L1IcacheMemory.cacheAvail(in_msg.LineAddress)) {
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if (L1Icache.cacheAvail(in_msg.LineAddress)) {
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// L1 does't have the line, but we have space for it
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// in the L1 so let's see if the L2 has it
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trigger(prefetch_request_type_to_event(in_msg.Type),
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@ -303,9 +302,9 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
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} else {
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// No room in the L1, so we need to make room in the L1
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trigger(Event:L1_Replacement,
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L1IcacheMemory.cacheProbe(in_msg.LineAddress),
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getL1ICacheEntry(L1IcacheMemory.cacheProbe(in_msg.LineAddress)),
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L1_TBEs[L1IcacheMemory.cacheProbe(in_msg.LineAddress)]);
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L1Icache.cacheProbe(in_msg.LineAddress),
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getL1ICacheEntry(L1Icache.cacheProbe(in_msg.LineAddress)),
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L1_TBEs[L1Icache.cacheProbe(in_msg.LineAddress)]);
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}
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} else {
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// Data prefetch
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@ -328,7 +327,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
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L1Icache_entry, L1_TBEs[in_msg.LineAddress]);
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}
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if (L1DcacheMemory.cacheAvail(in_msg.LineAddress)) {
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if (L1Dcache.cacheAvail(in_msg.LineAddress)) {
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// L1 does't have the line, but we have space for it in
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// the L1 let's see if the L2 has it
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trigger(prefetch_request_type_to_event(in_msg.Type),
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@ -337,9 +336,9 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
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} else {
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// No room in the L1, so we need to make room in the L1
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trigger(Event:L1_Replacement,
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L1DcacheMemory.cacheProbe(in_msg.LineAddress),
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getL1DCacheEntry(L1DcacheMemory.cacheProbe(in_msg.LineAddress)),
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L1_TBEs[L1DcacheMemory.cacheProbe(in_msg.LineAddress)]);
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L1Dcache.cacheProbe(in_msg.LineAddress),
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getL1DCacheEntry(L1Dcache.cacheProbe(in_msg.LineAddress)),
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L1_TBEs[L1Dcache.cacheProbe(in_msg.LineAddress)]);
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}
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}
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}
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@ -397,7 +396,8 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
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if (in_msg.Type == CoherenceRequestType:INV) {
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trigger(Event:Inv, in_msg.Address, cache_entry, tbe);
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} else if (in_msg.Type == CoherenceRequestType:GETX || in_msg.Type == CoherenceRequestType:UPGRADE) {
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} else if (in_msg.Type == CoherenceRequestType:GETX ||
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in_msg.Type == CoherenceRequestType:UPGRADE) {
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// upgrade transforms to GETX due to race
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trigger(Event:Fwd_GETX, in_msg.Address, cache_entry, tbe);
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} else if (in_msg.Type == CoherenceRequestType:GETS) {
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@ -436,15 +436,16 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
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L1Dcache_entry, L1_TBEs[in_msg.LineAddress]);
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}
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if (L1IcacheMemory.cacheAvail(in_msg.LineAddress)) {
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// L1 does't have the line, but we have space for it in the L1 so let's see if the L2 has it
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if (L1Icache.cacheAvail(in_msg.LineAddress)) {
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// L1 does't have the line, but we have space for it
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// in the L1 so let's see if the L2 has it.
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trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
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L1Icache_entry, L1_TBEs[in_msg.LineAddress]);
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} else {
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// No room in the L1, so we need to make room in the L1
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trigger(Event:L1_Replacement, L1IcacheMemory.cacheProbe(in_msg.LineAddress),
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getL1ICacheEntry(L1IcacheMemory.cacheProbe(in_msg.LineAddress)),
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L1_TBEs[L1IcacheMemory.cacheProbe(in_msg.LineAddress)]);
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trigger(Event:L1_Replacement, L1Icache.cacheProbe(in_msg.LineAddress),
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getL1ICacheEntry(L1Icache.cacheProbe(in_msg.LineAddress)),
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L1_TBEs[L1Icache.cacheProbe(in_msg.LineAddress)]);
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}
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}
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} else {
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@ -465,15 +466,16 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
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L1Icache_entry, L1_TBEs[in_msg.LineAddress]);
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}
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if (L1DcacheMemory.cacheAvail(in_msg.LineAddress)) {
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// L1 does't have the line, but we have space for it in the L1 let's see if the L2 has it
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if (L1Dcache.cacheAvail(in_msg.LineAddress)) {
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// L1 does't have the line, but we have space for it
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// in the L1 let's see if the L2 has it.
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trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
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L1Dcache_entry, L1_TBEs[in_msg.LineAddress]);
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} else {
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// No room in the L1, so we need to make room in the L1
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trigger(Event:L1_Replacement, L1DcacheMemory.cacheProbe(in_msg.LineAddress),
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getL1DCacheEntry(L1DcacheMemory.cacheProbe(in_msg.LineAddress)),
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L1_TBEs[L1DcacheMemory.cacheProbe(in_msg.LineAddress)]);
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trigger(Event:L1_Replacement, L1Dcache.cacheProbe(in_msg.LineAddress),
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getL1DCacheEntry(L1Dcache.cacheProbe(in_msg.LineAddress)),
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L1_TBEs[L1Dcache.cacheProbe(in_msg.LineAddress)]);
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}
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}
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}
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@ -846,23 +848,23 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
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}
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action(ff_deallocateL1CacheBlock, "\f", desc="Deallocate L1 cache block. Sets the cache to not present, allowing a replacement in parallel with a fetch.") {
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if (L1DcacheMemory.isTagPresent(address)) {
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L1DcacheMemory.deallocate(address);
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if (L1Dcache.isTagPresent(address)) {
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L1Dcache.deallocate(address);
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} else {
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L1IcacheMemory.deallocate(address);
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L1Icache.deallocate(address);
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}
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unset_cache_entry();
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}
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action(oo_allocateL1DCacheBlock, "\o", desc="Set L1 D-cache tag equal to tag of block B.") {
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if (is_invalid(cache_entry)) {
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set_cache_entry(L1DcacheMemory.allocate(address, new Entry));
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set_cache_entry(L1Dcache.allocate(address, new Entry));
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}
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}
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action(pp_allocateL1ICacheBlock, "\p", desc="Set L1 I-cache tag equal to tag of block B.") {
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if (is_invalid(cache_entry)) {
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set_cache_entry(L1IcacheMemory.allocate(address, new Entry));
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set_cache_entry(L1Icache.allocate(address, new Entry));
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}
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}
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@ -875,19 +877,19 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
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}
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action(uu_profileInstMiss, "\uim", desc="Profile the demand miss") {
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++L1IcacheMemory.demand_misses;
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++L1Icache.demand_misses;
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}
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action(uu_profileInstHit, "\uih", desc="Profile the demand hit") {
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++L1IcacheMemory.demand_hits;
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++L1Icache.demand_hits;
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}
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action(uu_profileDataMiss, "\udm", desc="Profile the demand miss") {
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++L1DcacheMemory.demand_misses;
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++L1Dcache.demand_misses;
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}
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action(uu_profileDataHit, "\udh", desc="Profile the demand hit") {
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++L1DcacheMemory.demand_hits;
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++L1Dcache.demand_hits;
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}
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action(po_observeMiss, "\po", desc="Inform the prefetcher about the miss") {
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@ -1,6 +1,5 @@
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/*
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* Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
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* Copyright (c) 1999-2013 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -33,7 +32,7 @@
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*/
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machine(L2Cache, "MESI Directory L2 Cache CMP")
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: CacheMemory * L2cacheMemory,
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: CacheMemory * L2cache,
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Cycles l2_request_latency = 2,
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Cycles l2_response_latency = 2,
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Cycles to_l1_latency = 1
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@ -76,7 +75,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
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MT_IIB, AccessPermission:Busy, desc="Blocked for L1_GETS from MT, waiting for unblock and data";
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MT_IB, AccessPermission:Busy, desc="Blocked for L1_GETS from MT, got unblock, waiting for data";
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MT_SB, AccessPermission:Busy, desc="Blocked for L1_GETS from MT, got data, waiting for unblock";
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}
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// EVENTS
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@ -160,7 +159,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
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// inclusive cache, returns L2 entries only
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Entry getCacheEntry(Address addr), return_by_pointer="yes" {
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return static_cast(Entry, "pointer", L2cacheMemory[addr]);
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return static_cast(Entry, "pointer", L2cache[addr]);
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}
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std::string getCoherenceRequestTypeStr(CoherenceRequestType type) {
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@ -372,20 +371,20 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
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in_msg.Requestor, cache_entry),
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in_msg.Address, cache_entry, tbe);
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} else {
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if (L2cacheMemory.cacheAvail(in_msg.Address)) {
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if (L2cache.cacheAvail(in_msg.Address)) {
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// L2 does't have the line, but we have space for it in the L2
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trigger(L1Cache_request_type_to_event(in_msg.Type, in_msg.Address,
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in_msg.Requestor, cache_entry),
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in_msg.Address, cache_entry, tbe);
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} else {
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// No room in the L2, so we need to make room before handling the request
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Entry L2cache_entry := getCacheEntry(L2cacheMemory.cacheProbe(in_msg.Address));
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Entry L2cache_entry := getCacheEntry(L2cache.cacheProbe(in_msg.Address));
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if (isDirty(L2cache_entry)) {
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trigger(Event:L2_Replacement, L2cacheMemory.cacheProbe(in_msg.Address),
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L2cache_entry, L2_TBEs[L2cacheMemory.cacheProbe(in_msg.Address)]);
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trigger(Event:L2_Replacement, L2cache.cacheProbe(in_msg.Address),
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L2cache_entry, L2_TBEs[L2cache.cacheProbe(in_msg.Address)]);
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} else {
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trigger(Event:L2_Replacement_clean, L2cacheMemory.cacheProbe(in_msg.Address),
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L2cache_entry, L2_TBEs[L2cacheMemory.cacheProbe(in_msg.Address)]);
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trigger(Event:L2_Replacement_clean, L2cache.cacheProbe(in_msg.Address),
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L2cache_entry, L2_TBEs[L2cache.cacheProbe(in_msg.Address)]);
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}
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}
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}
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@ -679,17 +678,17 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
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}
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action(set_setMRU, "\set", desc="set the MRU entry") {
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L2cacheMemory.setMRU(address);
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L2cache.setMRU(address);
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}
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action(qq_allocateL2CacheBlock, "\q", desc="Set L2 cache tag equal to tag of block B.") {
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if (is_invalid(cache_entry)) {
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set_cache_entry(L2cacheMemory.allocate(address, new Entry));
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set_cache_entry(L2cache.allocate(address, new Entry));
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}
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}
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action(rr_deallocateL2CacheBlock, "\r", desc="Deallocate L2 cache block. Sets the cache to not present, allowing a replacement in parallel with a fetch.") {
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L2cacheMemory.deallocate(address);
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L2cache.deallocate(address);
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unset_cache_entry();
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}
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@ -721,11 +720,11 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
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}
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action(uu_profileMiss, "\um", desc="Profile the demand miss") {
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++L2cacheMemory.demand_misses;
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++L2cache.demand_misses;
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}
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action(uu_profileHit, "\uh", desc="Profile the demand hit") {
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++L2cacheMemory.demand_hits;
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++L2cache.demand_hits;
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}
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action(ww_profileMissNoDir, "\w", desc="Profile this transition at the L2 because Dir won't see the request") {
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@ -803,12 +802,12 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
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// Transitions from I (Idle)
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transition({NP, IS, ISS, IM, SS, M, M_I, I_I, S_I, MT_IB, MT_SB}, L1_PUTX) {
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t_sendWBAck;
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t_sendWBAck;
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jj_popL1RequestQueue;
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}
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transition({NP, SS, M, MT, M_I, I_I, S_I, IS, ISS, IM, MT_IB, MT_SB}, L1_PUTX_old) {
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t_sendWBAck;
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t_sendWBAck;
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jj_popL1RequestQueue;
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}
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@ -816,11 +815,11 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
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zz_stallAndWaitL1RequestQueue;
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}
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transition({IM, IS, ISS, SS_MB, MT_MB, MT_IIB, MT_IB, MT_SB}, MEM_Inv) {
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transition({IM, IS, ISS, SS_MB, MT_MB, MT_IIB, MT_IB, MT_SB}, MEM_Inv) {
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zn_recycleResponseNetwork;
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}
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transition({S_I, M_I, MT_I}, MEM_Inv) {
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transition({S_I, M_I, MT_I}, MEM_Inv) {
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o_popIncomingResponseQueue;
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}
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@ -1037,7 +1036,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
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k_popUnblockQueue;
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kd_wakeUpDependents;
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}
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transition(MT_IIB, {L1_PUTX, L1_PUTX_old}){
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zz_stallAndWaitL1RequestQueue;
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}
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@ -1086,14 +1085,14 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
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}
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||||
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||||
transition(MCT_I, {WB_Data_clean, Ack_all}, M_I) {
|
||||
c_exclusiveCleanReplacement;
|
||||
c_exclusiveCleanReplacement;
|
||||
o_popIncomingResponseQueue;
|
||||
}
|
||||
|
||||
transition(MCT_I, {L1_PUTX, L1_PUTX_old}){
|
||||
zz_stallAndWaitL1RequestQueue;
|
||||
zz_stallAndWaitL1RequestQueue;
|
||||
}
|
||||
|
||||
|
||||
// L1 never changed Dirty data
|
||||
transition(MT_I, Ack_all, M_I) {
|
||||
ct_exclusiveReplacementFromTBE;
|
||||
|
|
@ -1101,7 +1100,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
|
|||
}
|
||||
|
||||
transition(MT_I, {L1_PUTX, L1_PUTX_old}){
|
||||
zz_stallAndWaitL1RequestQueue;
|
||||
zz_stallAndWaitL1RequestQueue;
|
||||
}
|
||||
|
||||
// possible race between unblock and immediate replacement
|
||||
|
|
|
|||
|
|
@ -1,6 +1,5 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
|
||||
* Copyright (c) 1999-2013 Mark D. Hill and David A. Wood
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
|
|
@ -35,7 +34,7 @@
|
|||
// Copied here by aep 12/14/07
|
||||
|
||||
|
||||
machine(Directory, "MESI_CMP_filter_directory protocol")
|
||||
machine(Directory, "MESI_CMP_filter_directory protocol")
|
||||
: DirectoryMemory * directory,
|
||||
MemoryControl * memBuffer,
|
||||
Cycles to_mem_ctrl_latency = 1,
|
||||
|
|
@ -53,7 +52,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
|
|||
// Base states
|
||||
I, AccessPermission:Read_Write, desc="dir is the owner and memory is up-to-date, all other copies are Invalid";
|
||||
ID, AccessPermission:Busy, desc="Intermediate state for DMA_READ when in I";
|
||||
ID_W, AccessPermission:Busy, desc="Intermediate state for DMA_WRITE when in I";
|
||||
ID_W, AccessPermission:Busy, desc="Intermediate state for DMA_WRITE when in I";
|
||||
|
||||
M, AccessPermission:Maybe_Stale, desc="memory copy may be stale, i.e. other modified copies may exist";
|
||||
IM, AccessPermission:Busy, desc="Intermediate State I>M";
|
||||
|
|
@ -84,7 +83,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
|
|||
State DirectoryState, desc="Directory state";
|
||||
DataBlock DataBlk, desc="data for the block";
|
||||
NetDest Sharers, desc="Sharers for this block";
|
||||
NetDest Owner, desc="Owner of this block";
|
||||
NetDest Owner, desc="Owner of this block";
|
||||
}
|
||||
|
||||
// TBE entries for DMA requests
|
||||
|
|
@ -94,13 +93,13 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
|
|||
DataBlock DataBlk, desc="Data to be written (DMA write only)";
|
||||
int Len, desc="...";
|
||||
}
|
||||
|
||||
|
||||
structure(TBETable, external="yes") {
|
||||
TBE lookup(Address);
|
||||
void allocate(Address);
|
||||
TBE lookup(Address);
|
||||
void allocate(Address);
|
||||
void deallocate(Address);
|
||||
bool isPresent(Address);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
// ** OBJECTS **
|
||||
|
|
@ -125,22 +124,22 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
|
|||
|
||||
State getState(TBE tbe, Address addr) {
|
||||
if (is_valid(tbe)) {
|
||||
return tbe.TBEState;
|
||||
return tbe.TBEState;
|
||||
} else if (directory.isPresent(addr)) {
|
||||
return getDirectoryEntry(addr).DirectoryState;
|
||||
} else {
|
||||
return State:I;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void setState(TBE tbe, Address addr, State state) {
|
||||
|
||||
if (is_valid(tbe)) {
|
||||
tbe.TBEState := state;
|
||||
}
|
||||
|
||||
|
||||
if (directory.isPresent(addr)) {
|
||||
|
||||
|
||||
if (state == State:I) {
|
||||
assert(getDirectoryEntry(addr).Owner.count() == 0);
|
||||
assert(getDirectoryEntry(addr).Sharers.count() == 0);
|
||||
|
|
@ -148,7 +147,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
|
|||
assert(getDirectoryEntry(addr).Owner.count() == 1);
|
||||
assert(getDirectoryEntry(addr).Sharers.count() == 0);
|
||||
}
|
||||
|
||||
|
||||
getDirectoryEntry(addr).DirectoryState := state;
|
||||
}
|
||||
}
|
||||
|
|
@ -458,10 +457,10 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
|
|||
action(v_allocateTBE, "v", desc="Allocate TBE") {
|
||||
peek(requestNetwork_in, RequestMsg) {
|
||||
TBEs.allocate(address);
|
||||
set_tbe(TBEs[address]);
|
||||
set_tbe(TBEs[address]);
|
||||
tbe.DataBlk := in_msg.DataBlk;
|
||||
tbe.PhysicalAddress := in_msg.Address;
|
||||
tbe.Len := in_msg.Len;
|
||||
tbe.Len := in_msg.Len;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -484,17 +483,17 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
|
|||
//out_msg.DataBlk := in_msg.DataBlk;
|
||||
//out_msg.DataBlk.copyPartial(tbe.DataBlk, tbe.Offset, tbe.Len);
|
||||
out_msg.DataBlk.copyPartial(tbe.DataBlk, addressOffset(tbe.PhysicalAddress), tbe.Len);
|
||||
|
||||
|
||||
out_msg.MessageSize := in_msg.MessageSize;
|
||||
//out_msg.Prefetch := in_msg.Prefetch;
|
||||
|
||||
|
||||
DPRINTF(RubySlicc, "%s\n", out_msg);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
action(w_deallocateTBE, "w", desc="Deallocate TBE") {
|
||||
TBEs.deallocate(address);
|
||||
TBEs.deallocate(address);
|
||||
unset_tbe();
|
||||
}
|
||||
|
||||
|
|
@ -595,7 +594,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
|
|||
transition(M_DWR, Data, M_DWRI) {
|
||||
m_writeDataToMemory;
|
||||
qw_queueMemoryWBRequest_partialTBE;
|
||||
k_popIncomingResponseQueue;
|
||||
k_popIncomingResponseQueue;
|
||||
}
|
||||
|
||||
transition(M_DWRI, Memory_Ack, I) {
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@
|
|||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
machine(DMA, "DMA Controller")
|
||||
machine(DMA, "DMA Controller")
|
||||
: DMASequencer * dma_sequencer,
|
||||
Cycles request_latency = 6
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in a new issue