Dam Sunwoo 2c1e344313 cpu: generate SimPoint basic block vector profiles ... This patch is based on http://reviews.m5sim.org/r/1474/ originally written by Mitch Hayenga. Basic block vectors are generated (simpoint.bb.gz in simout folder) based on start and end addresses of basic blocks. Some comments to the original patch are addressed and hooks are added to create and resume from checkpoints based on instruction counts dictated by external SimPoint analysis tools. SimPoint creation/resuming options will be implemented as a separate patch.		2013-04-22 13:20:31 -04:00
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boot	rcs scripts: remove bbench.rcS	2013-04-02 12:46:49 -04:00
common	cpu: generate SimPoint basic block vector profiles	2013-04-22 13:20:31 -04:00
example	cpu: generate SimPoint basic block vector profiles	2013-04-22 13:20:31 -04:00
ruby	config: ruby network test: remove piobus check	2013-04-17 16:06:24 -05:00
splash2	Bus: Split the bus into a non-coherent and coherent bus	2012-05-31 13:30:04 -04:00
topologies	Ruby: Clean up topology changes	2012-08-10 13:50:42 -05:00