that made ccprintf and friends work, turn it into a
normal function (though it still has a slightly strange
implementation.) All instances of variadic macros
are not yet removed, but I know how, and it will happen.
One side effect of this new implementation is that a
cprintf statement can now only have 16 parameters, though
it's easy enough to raise this number if needed.
--HG--
extra : convert_revision : 85cb3c17f8e2ecf9cd2f31ea80a760a28ea127a7
Created MemCmd class to wrap enum and provide handy methods to
check attributes, convert to string/int, etc.
--HG--
extra : convert_revision : 57f147ad893443e3a2040c6d5b4cdb1a8033930b
Caveats:
- Even though memtest is ISA-independent, it will only
run for the Alpha builds, since there's no way to specify
ISA-independent reference files and I didn't want to commit
3 copies since I'm not sure we want to run it for all the
different ISAs anyway.
- Reference outputs were generated on my laptop,
so performance numbers will be low compared to zizzer.
--HG--
extra : convert_revision : 210fe4abecc19fbab0b15402c6cb4863650bab66
fix unaligned accesses in mmaped disk device
src/arch/sparc/isa/decoder.isa:
get (ld|st)fsr ops working right. In reality the fp enable check needs to go higher up in the emitted code
src/arch/sparc/isa/formats/basic.isa:
move the cexec into the aexec field
src/cpu/exetrace.cc:
copy the exception state from legion when we get it wrong. We aren't going to get it right without an fp emulation layer
src/dev/sparc/mm_disk.cc:
src/dev/sparc/mm_disk.hh:
fix unaligned accesses in the memory mapped disk device
--HG--
extra : convert_revision : aaa33096b08cf0563fe291d984a87493a117e528
src/arch/sparc/floatregfile.cc:
fix fp read/writing to registers... looking for suggestions on cleaner ways if anyone has them
src/arch/sparc/isa/decoder.isa:
fix some fp implementations
src/arch/sparc/isa/formats/basic.isa:
add new fp op class that 0 cexec in fsr and sets rounding mode for the up comming op
src/arch/sparc/isa/includes.isa:
include the appropriate header files for the rounding code
src/arch/sparc/miscregfile.cc:
print fsr out when it's read/written and the Sparc traceflgas in on
src/cpu/exetrace.cc:
fix printing of float registers
--HG--
extra : convert_revision : 49faab27f2e786a8455f9ca0f3f0132380c9d992
src/arch/sparc/floatregfile.cc:
Fix serialization for fpreg
src/arch/sparc/intregfile.cc:
fix serialization for intreg
src/arch/sparc/miscregfile.cc:
fix serialization from miscreg
src/arch/sparc/pagetable.cc:
fix serialization for page table
src/arch/sparc/regfile.cc:
need to serialize nnpc
src/arch/sparc/tlb.cc:
write serialization code for tlb
src/cpu/base.cc:
provide a way to find the thread number a context is
serialize the instruction counter
src/cpu/base.hh:
provide a way to find the thread number a context is
and given a thread number find a context pointer
src/cpu/cpuevent.hh:
provide method to get thread context from a cpu event for serialization
src/dev/sparc/t1000.cc:
src/dev/sparc/t1000.hh:
nothing to serialize in t1000
src/sim/serialize.cc:
src/sim/serialize.hh:
Make findObj() work (it hasn't since we did the python conversion stuff)
--HG--
extra : convert_revision : a95bc4e3c3354304171efbe3797556fdb146bea2
src/arch/sparc/isa/base.isa:
Added passesFpCondition function to help with fbfcc and fbpfcc instructions.
src/arch/sparc/isa/decoder.isa:
Added fbfcc and fbpfcc instructions, and cleaned up branch code slightly.
src/arch/sparc/isa/formats/branch.isa:
Minor cleanup.
--HG--
extra : convert_revision : 6586b46418f1f70bace41407f267fee30c657714
