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Author SHA1 Message Date
Gabe Black 3a1428365a ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem. 
readBytes and writeBytes had the word "bytes" in their names because they
accessed blobs of bytes. This distinguished them from the read and write
functions which handled higher level data types. Because those functions don't
exist any more, this change renames readBytes and writeBytes to more general
names, readMem and writeMem, which reflect the fact that they are how you read
and write memory. This also makes their names more consistent with the
register reading/writing functions, although those are still read and set for
some reason.
 2011-07-02 22:35:04 -07:00
Gabe Black 2e7426664a ExecContext: Get rid of the now unused read/write templated functions. 2011-07-02 22:34:58 -07:00
Gabe Black aade13769f ISA: Use readBytes/writeBytes for all instruction level memory operations. 2011-07-02 22:34:29 -07:00
Gabe Black 2f72d6a1f4 X86: Fix store microops so they don't drop faults in timing mode. 
If a fault was returned by the CPU when a store initiated it's write, the
store instruction would ignore the fault. This change fixes that.
 2011-07-02 22:31:22 -07:00
Nilay Vaish 45b411fc5f Ruby: Commit files missing from previous commit 
The previous commit on functional access support in Ruby did not have
some of the files required. This patch adds those files to the repository.
 2011-07-01 16:29:33 -05:00
Brad Beckmann ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E) c86f849d5a Ruby: Add support for functional accesses 
This patch rpovides functional access support in Ruby. Currently only
the M5Port of RubyPort supports functional accesses. The support for
functional through the PioPort will be added as a separate patch.
 2011-06-30 19:49:26 -05:00
Nilay Vaish f4cfd65d29 arch: print next upc correctly 
The patch corrects the print statement which prints the current and
the next pc. Instead of the next upc, the next pc was being printed.
 2011-06-28 18:27:38 -05:00
Joel Hestness d50aec8d9a Ruby: remove unused functions in CacheMemory: get/setMemoryValue 2011-06-24 15:47:35 -05:00
Deyaun Guo 5aaddc129e mips: fix nmsub and nmadd definitions 
the -/+ signs were flipped for nmsub_s, nmsub_d, and nmadd_d
 2011-06-22 23:35:21 -04:00
Gabe Black efb9f7c2ae X86: Eliminate an unused argument for building store microops. 2011-06-21 19:28:14 -07:00
Gabe Black affad29932 InOder: Fix a compile error. 2011-06-20 02:29:14 -07:00
Korey Sewell 477e7039b3 inorder: clear reg. dep entry after removing from list 
this will safeguard future code from trying to remove
from the list twice. That code wouldnt break but would
waste time.
 2011-06-19 21:43:42 -04:00
Korey Sewell b963b339b9 inorder: se: squash after syscalls 2011-06-19 21:43:42 -04:00
Korey Sewell eedd04e894 inorder: cleanup dprintfs in cache unit 2011-06-19 21:43:42 -04:00
Korey Sewell 078f914e69 inorder: SE mode TLB faults 
handle them like we do in FS mode, by blocking the TLB until the fault
is handled by the fault->invoke()
 2011-06-19 21:43:42 -04:00
Korey Sewell 3cb23bd3a2 inorder:tracing: fix fault tracing bug 2011-06-19 21:43:42 -04:00
Korey Sewell fe3a2aa4a3 inorder: se compile fixes 2011-06-19 21:43:42 -04:00
Korey Sewell e572c01120 inorder: add necessary debug flag header files 2011-06-19 21:43:41 -04:00
Korey Sewell 59686795e3 mips: mark unaligned access flag as true 2011-06-19 21:43:41 -04:00
Korey Sewell 91a88ae8ce inorder: clear fetchbuffer on traps 
implement clearfetchbufferfunction
extend predecoder to use multiple threads and clear those on trap
 2011-06-19 21:43:41 -04:00
Korey Sewell 2dae0e8735 inorder: use separate float-reg bits function in dyninst 
this will make sure we get the correct view of a FP register
 2011-06-19 21:43:41 -04:00
Korey Sewell 8c0def8d03 inorder: use trapPending flag to manage traps 2011-06-19 21:43:41 -04:00
Korey Sewell 5ef0b7a9db inorder/dtb: make sure DTB translate correct address 
The DTB expects the correct PC in the ThreadContext
but how if the memory accesses are speculative? Shouldn't
we send along the requestor's PC to the translate functions?
 2011-06-19 21:43:41 -04:00
Korey Sewell 716e447da8 inorder: handle serializing instructions 
including IPR accesses and store-conditionals. These class of instructions will not
execute correctly in a superscalar machine
 2011-06-19 21:43:41 -04:00
Korey Sewell 83a0fd24f7 alpha: fix warn_once for prefetches 2011-06-19 21:43:40 -04:00
Korey Sewell 33a6020f2e alpha: naming for dtb faults 
Just "dfault" gets confusing while debugging. Why not
differentiate whether it's an access violation or page
fault
 2011-06-19 21:43:40 -04:00
Korey Sewell 561c33f082 inorder: dont handle multiple faults on same cycle 
if a faulting instruction reaches an execution unit,
then ignore it and pass it through the pipeline.

Once we recognize the fault in the graduation unit,
dont allow a second fault to creep in on the same cycle.
 2011-06-19 21:43:40 -04:00
Korey Sewell c4deabfb97 inorder: register ports for FS mode 
handle "snoop" port registration as well as functional
port setup for FS mode
 2011-06-19 21:43:40 -04:00
Korey Sewell f1c3691356 inorder: check for interrupts each tick 
use a dummy instruction to facilitate the squash after
the interrupts trap
 2011-06-19 21:43:40 -04:00
Korey Sewell 0bfdf342da inorder: explicit fault check 
Before graduating an instruction, explicitly check fault
by making the fault check it's own separate command
that can be put on an instruction schedule.
 2011-06-19 21:43:40 -04:00
Korey Sewell 5f608dd2e9 inorder: squash and trap behind a tlb fault 2011-06-19 21:43:39 -04:00
Korey Sewell e0e387c2a9 inorder: stall stores on store conditionals & compare/swaps 2011-06-19 21:43:39 -04:00
Korey Sewell f268d7d004 alpha: make hwrei a control inst 
this always changes the PC and is basically an impromptu branch instruction. why
not speculate on this instead of always be forced to mispredict/squash after the
hwrei gets resolved?

The InOrder model needs this marked as "isControl" so it knows to update the PC
after the ALU executes it. If this isnt marked as control, then it's going to
force the model to check the PC of every instruction at commit (what O3 does?),
and that would be a wasteful check for a very high percentage of instructions.
 2011-06-19 21:43:39 -04:00
Korey Sewell e8b7df072b inorder: make InOrder CPU FS compilable/visible 
make syscall a SE mode only functionality
copy over basic FS functions (hwrei) to make FS compile
 2011-06-19 21:43:39 -04:00
Korey Sewell d71b95d84d inorder: remove memdep tracking for default pipeline 
speculative load/store pipelines can reenable this
 2011-06-19 21:43:39 -04:00
Korey Sewell b72bdcf4f8 inorder: fetchBuffer tracking 
calculate blocks in use for the fetch buffer to figure out how many total blocks
are pending
 2011-06-19 21:43:39 -04:00
Korey Sewell 4d4c7d79d0 inorder: redefine DynInst FP result type 
Sharing the FP value w/the integer values was giving inconsistent results esp. when
their is a 32-bit integer register matched w/a 64-bit float value
 2011-06-19 21:43:38 -04:00
Korey Sewell db8b1e4b78 inorder: treat SE mode syscalls as a trapping instruction 
define a syscallContext to schedule the syscall and then use syscall() to actually perform the action
 2011-06-19 21:43:38 -04:00
Korey Sewell c95fe261ab inorder: bug in mdu 
segfault was caused by squashed multiply thats in the process of an event.
use isProcessing flag to handle this and cleanup the MDU code
 2011-06-19 21:43:38 -04:00
Korey Sewell 4c979f9325 inorder: optionally track faulting instructions 2011-06-19 21:43:38 -04:00
Korey Sewell 22ba1718c4 inorder: cleanup events in resource pool 
remove events in the resource pool that can be called from the CPU event, since the CPU
event is scheduled at the same time at the resource pool event.
----
Also, match the resPool event function names to the cpu event function names
----
 2011-06-19 21:43:38 -04:00
Korey Sewell e8082a28c8 inorder: don't stall after stores 
once a ST is sent off, it's OK to keep processing, however it's a little more
complicated to handle the packet acknowledging the store is completed
 2011-06-19 21:43:38 -04:00
Korey Sewell 379c23199e inorder: don't stall after stores 
once a ST is sent off, it's OK to keep processing, however it's a little more
complicated to handle the packet acknowledging the store is completed
 2011-06-19 21:43:37 -04:00
Korey Sewell 4c9ad53cc5 inorder: remove decode squash 
also, cleanup comments for gem5.fast compilation
 2011-06-19 21:43:37 -04:00
Korey Sewell a444133e73 inorder: support for compare and swap insts 
dont treat read() and write() fields as mut. exclusive
 2011-06-19 21:43:37 -04:00
Korey Sewell 89d0f95bf0 inorder: branch predictor update 
only update BTB on a taken branch and update branch predictor w/pcstate from instruction
---
only pay attention to branch predictor updates if the the inst. is in fact a branch
 2011-06-19 21:43:37 -04:00
Korey Sewell 479195d4cf inorder: priority for grad/squash events 
define separate priority resource pool squash and graduate events
 2011-06-19 21:43:37 -04:00
Korey Sewell 71018f5e8b inorder: remove stalls on trap squash 2011-06-19 21:43:37 -04:00
Korey Sewell 34b2500f09 inorder: no dep. tracking for zero reg 
this causes forwarding a bad value register value
 2011-06-19 21:43:37 -04:00
Korey Sewell d02fa0f6b6 imported patch recoverPCfromTrap 2011-06-19 21:43:37 -04:00