Now we are to the point where more benchmarks and instruction-coverage
is necessary to totally verify/validate correct operation across
all MIPS instructions
arch/mips/isa_traits.hh:
fix for reading double values ... must rearrange bits before using void* to read double.
configs/test/hello_mips:
real hello world MIPS binary
--HG--
extra : convert_revision : 153de1f8a830882c6972bd0bdb56da818f614def
register with the higher # contains the most significant bytes...
arch/mips/isa/decoder.isa:
divide instruction fixes
arch/mips/isa_traits.cc:
use double as argument to cvt & round function.
clean up cout statements in function.
arch/mips/isa_traits.hh:
In MIPS the higher # reg of a doubles pair is ALSO the most significant reg.
Once I switched this the basic MIPS FP test I had worked.
--HG--
extra : convert_revision : 45c80df229e6174d0b52fc7cfb530642b1f1fc35
Edit the convert_and_round function which access FloatRegFile
arch/isa_parser.py:
recognize when we are writing a 'uint64_t' FloatReg and set the width appropriately
arch/mips/isa/decoder.isa:
Send a 'float' to the convert function instead of a unsigned word. Do this so we dont have to worry about the
bit manipulation ourselves. We can just concern ourselves with values.
Use unsigned double to get movd...
arch/mips/isa/formats/fp.isa:
float debug statement
arch/mips/isa_traits.cc:
add different versions of convert_and_round functions
arch/mips/isa_traits.hh:
Use an array of uint32_t unsigned integers to represent the Floating Point Regfile
configs/test/hello_mips:
basic FP program
cpu/simple/cpu.hh:
spacing
--HG--
extra : convert_revision : a6fca91ad6365c83025f1131d71fa1b8ee76d7bc
Have FP conversion instructions use re-defined convert_and_round() function
arch/mips/isa/decoder.isa:
Use lower two bits of FCSR reg to determine rounding mode (may want to move this out of decoder.isa and into a template)
Have FP conversion instructions to use re-defined convert_and_round() function
arch/mips/isa/formats/util.isa:
Remove convert_and_round function from here
arch/mips/isa_traits.cc:
Define convert_and_round function here
arch/mips/isa_traits.hh:
Use "enums" to define FP conversion types & Round Modes
Declare convert_and_round function here
--HG--
extra : convert_revision : 0f4f8c1732a53b277361559ea71af2a1feb4fc64
This class is derived from the original <OS> class and is used to define information that
is both architecure and OS specific (for example, the AlphaLinux class is derived from the
Linux class and defined in arch/alpha/linux/linux.hh).
SConscript:
no need to compile linux.cc and tru64.cc now, since openFlagsTable has been moved
arch/alpha/SConscript:
compile linux.cc and tru64.cc within alpha arch.
arch/alpha/linux/process.cc:
template syscall functions on AlphaLinux instead of Linux ... AlphaLinux is derived off of Linux
arch/alpha/tru64/process.cc:
template syscall functions on AlphaTru64 instead of Linux ... AlphaTru64 is derived off of Linux
moved tableFunc syscall function into this file
arch/mips/SConscript:
compile mips_linux.cc for openFlags table
arch/mips/isa_traits.hh:
remove constants from here
arch/mips/linux_process.cc:
template syscall functions on MipsLinux instead of Linux ... MipsLinux is derived off of Linux
kern/linux/linux.hh:
remove OSFlags
kern/tru64/tru64.hh:
remove OSFlags def., openFlagTable, and tableFunc ...
sim/syscall_emul.hh:
go back to using "OS" instead of "OSFlags"
arch/alpha/linux/linux.cc:
defines openFlagTable
arch/alpha/linux/linux.hh:
arch/alpha/tru64/tru64.hh:
Alpha Linux constants placed here in class derived from Linux class
arch/alpha/tru64/tru64.cc:
defines openFlagTable for AlphaTru64
arch/mips/mips_linux.cc:
MIPS Linux open flag table
arch/mips/mips_linux.hh:
Mips Linux constants placed here in class derived from Linux class
--HG--
extra : convert_revision : e6c1c2c895429c28fd141732e223e897ab19315e
flags for their functions (e.g. OS::OSFlags::TG_MAP_ANONYMOUS)...
arch/alpha/tru64/process.cc:
sim/syscall_emul.hh:
Add OSFlags to code
arch/mips/isa/decoder.isa:
slight decoder changes (more stylistic then anything)
arch/mips/isa/formats/util.isa:
spacing
arch/mips/isa_traits.hh:
add OSFlags struct to MipsISA namespace. The OS classes then use these OSFlags to access architecture-specific and OS-specific
flags for their functions
kern/linux/linux.hh:
remove constant placement ... define OSFlags in linux.hh
kern/tru64/tru64.hh:
define OSFlags in tru64
--HG--
extra : convert_revision : 59be1036eb439ca4ea1eea1d3b52e508023de6c9
into zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-mips
arch/mips/isa/formats/mem.isa:
Filled in Split-Memory Access Code
arch/mips/isa_traits.hh:
Leave IntRegFile as an array instead of class with member functions
mem/page_table.cc:
take out NO ALIGN FAULT page table access code for now... No need to messs up what works
--HG--
extra : convert_revision : cbf1cce9145daf9ee9ceabc9080271ddb0561489
arch/mips/isa/bitfields.isa:
add RS_SRL bitfield ...these must be set to 0 for a SRL instruction
arch/mips/isa/decoder.isa:
Make unimplemented instructions Fail instead of just Warn
Edits to SRA & SRAV instructions
Implement CFC1 instructions
Unaligned Memory Access Support (Maybe Not fully functional yet)
Enforce a more strict decode policy (in terms of different bitfields set to 0 on certain instructions)
arch/mips/isa/formats/branch.isa:
Fix disassembly
arch/mips/isa/formats/int.isa:
Add sign extend Immediate and zero extend Immediate to Int class.
Probably a bit unnecessary in the long run since these manipulations could
be done in the actually instruction instead of keep a int value
arch/mips/isa/formats/mem.isa:
Comment/Remove out split-memory access code... revisit this after SimpleCPU works
arch/mips/isa/formats/unimp.isa:
Add inst2string function to Unimplemented panic. PRints out the instruction
binary to help in debuggin
arch/mips/isa/formats/unknown.isa:
define inst2string function , use in unknown disassembly and panic function
arch/mips/isa/operands.isa:
Make "Mem" default to a unsigned word since this is MIPS32
arch/mips/isa_traits.hh:
change return values to 32 instead of 64
arch/mips/linux_process.cc:
assign some syscalls to the right functions
cpu/static_inst.hh:
more debug functions for MIPS (these will be move to the mips directory soon)
mem/page_table.cc:
mem/page_table.hh:
toward a better implementation for unaligned memory access
mem/request.hh:
NO ALIGN FAULT flag added to support unaligned memory access
sim/syscall_emul.cc:
additional SyscallVerbose comments
--HG--
extra : convert_revision : 1987d80c9f4ede507f1f0148435e0bee97d2428c
arch/alpha/isa_traits.hh:
arch/mips/isa_traits.cc:
Turned the integer register file into a class instead of a typedef to an array.
arch/alpha/regfile.hh:
Changed the integer register file into a class instead of a typedef to an array. Also put the parts of the register file, ie the int, float, and misc register files, pc, npc, and nnpc, behind accessor functions. Added a changeContext function, and ContextParam and ContextVal types, so that things like the register window can be changed through call backs.
arch/mips/isa_traits.hh:
Turned the integer register file into a class instead of a typedef to an array. Also moved a "using namespace" into the namespace definition.
arch/sparc/isa_traits.hh:
Turned the integer register file into a class instead of a typedef to an array. Also "fixed" the max number of src and dest regs. They may need to be even larger.
arch/sparc/regfile.hh:
Changed the integer register file into a class instead of a typedef to an array. Also put the parts of the register file, ie the int, float, and misc register files, pc, npc, and nnpc, behind accessor functions. Added a changeContext function, and ContextParam and ContextVal types, so that things like the register window can be changed through call backs. Created setCWP and setAltGlobals functions for the IntRegFile.
cpu/cpu_exec_context.hh:
Used the accessor functions for the register file, and added a changeRegFileContext function to call back into the RegFile. Used the RegFile clear function rather than memsetting it to 0.
cpu/exec_context.hh:
Added the changeRegFileContext function.
cpu/exetrace.cc:
Use the TheISA::NumIntRegs constant, and use readReg now that the integer register file is a class instead of an array.
cpu/exetrace.hh:
Get the address of the regs object, now that it isn't an array.
--HG--
extra : convert_revision : ea2dd81be1c2e66b3c684af319eb58f8a77fd49c
arch/mips/isa_traits.hh:
use syscall return function from alpha
arch/mips/linux_process.cc:
fix some syntax errors, map some functions to the desc. table
--HG--
extra : convert_revision : 75e8e8893b7d96bb4fc8e8eced53bd16c0a727d1
arch/mips/isa/decoder.isa:
arch/mips/isa_traits.hh:
sim/syscall_emul.cc:
make syscall instruction functional
arch/mips/linux_process.cc:
add all MIPS/Linux syscalls to descriptor list
--HG--
extra : convert_revision : 5455a345e76be921e9f63b248aef874b6358e465
into zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-mips
--HG--
extra : convert_revision : 9bdde9b5bd3049744451eda1134f080b7c4b1b59
is changed
Add a default machine width parameter
Arch based live processes
arch/alpha/linux/process.cc:
arch/alpha/linux/process.hh:
arch/alpha/process.cc:
arch/alpha/process.hh:
arch/alpha/tru64/process.cc:
arch/alpha/tru64/process.hh:
arch/mips/linux_process.cc:
arch/mips/process.cc:
arch/mips/process.hh:
arch/sparc/linux/process.cc:
arch/sparc/linux/process.hh:
arch/sparc/process.cc:
arch/sparc/process.hh:
configs/test/test.py:
python/m5/objects/Process.py:
sim/process.cc:
sim/process.hh:
Architecture based live processes
arch/mips/isa_traits.hh:
arch/sparc/isa_traits.hh:
Add a default machine width parameter
mem/port.hh:
gcc 4 really wants a virtual destructor
sim/byteswap.hh:
remove the comment around long and unsigned long even though uint32_t
and int32_t are defined. Seems to work with gcc 4 and 3.4.3.
sim/syscall_emul.cc:
sim/syscall_emul.hh:
add translations for new sections that are mmapped or when the brk
is changed
--HG--
extra : convert_revision : e2f9f228113c7127c87ef2358209a399c30ed5c6
arch/mips/isa/formats/branch.isa:
let user know that we alter r31 in disassembly
arch/mips/isa_traits.cc:
add copyRegs function ...
comment out serialize float code for now
arch/mips/isa_traits.hh:
make FloatRegFile a class ... change values of architectural regs
arch/mips/process.cc:
change MIPS to Mips
base/loader/elf_object.cc:
get global pointer initialized to a value
base/loader/elf_object.hh:
Add global_ptr to elf_object constructor
base/loader/object_file.hh:
MIPS to Mips
base/traceflags.py:
SimpleCPU trace flag
cpu/simple/cpu.cc:
DPRINTF flags for SimpleCPU
cpu/static_inst.hh:
Add Decoder functions to static_inst.hh
--HG--
extra : convert_revision : 0544a8524d3fe4229428cb06822f7da208c72459
SConscript:
Separate Alpha EIO from syscall building for other architectures
arch/isa_specific.hh:
change MIPS constant to 34k
arch/mips/isa/decoder.isa:
Allow sll,ssnop,nop, and ehb to be determined through decoder using
the different types of default cases
arch/mips/isa/formats/branch.isa:
Delete debug code
arch/mips/isa/formats/noop.isa:
add a Nop format
arch/mips/isa_traits.hh:
use constants instead of enums
arch/mips/process.cc:
point to the correct header file
cpu/simple/cpu.cc:
Output the actual fault name
sim/process.cc:
Inititalize NNPC
--HG--
extra : convert_revision : adb0026dfad25b14c98fb03c98bfe9c681bba6f8
arch/alpha/isa_traits.hh:
used for SimpleCPU instead of explicitly calling the namespace we declare in isa_traits.hhs
so other archs. can use SimpleCPU
arch/mips/SConscript:
dont include common_syscall or tru64
arch/mips/faults.cc:
arch/mips/faults.hh:
arch/mips/isa/formats/unimp.isa:
arch/mips/isa/formats/unknown.isa:
Change Faults to new format
arch/mips/isa/decoder.isa:
Fix readMiscReg access
Made change so that you cant explicitly tell if a instruction nop,ehb,or ssnop... These are all variants
of the sll instruction so I may need to make a separte class of instructions to handle thse better
arch/mips/isa/includes.isa:
add isa_traits.hh and MipsISA included into every auto-gen file
arch/mips/isa_traits.cc:
create copyMiscRegs function...
delete useless code
arch/mips/isa_traits.hh:
clean up for build
arch/mips/linux_process.cc:
mem is now getMemPort(), linux process objects now take in a system argument
arch/mips/linux_process.hh:
new argument for linux process
arch/mips/process.cc:
add system
arch/mips/process.hh:
add system variable
cpu/cpu_exec_context.cc:
Change AlphaISA to TheISA
cpu/exec_context.hh:
add readNextNPC and setNextNPC functions
cpu/simple/cpu.cc:
include isa_traits for namespace declariation
cpu/simple/cpu.hh:
PC & NPC access/modify functions
arch/mips/utility.hh:
file needed for compile
--HG--
extra : convert_revision : 29a327e79c51c6174a6e526aa68c7aab7e7eb535
arch/alpha/isa_traits.hh:
arch/sparc/isa_traits.hh:
add nnpc for compiling purposes in exec_context setNextNPC function
cpu/exec_context.hh:
set NNPC function
cpu/simple/cpu.cc:
use NNPC in determining what PC we are using
--HG--
extra : convert_revision : e810cfbc5dc31879b20d2cc40bf9871613203532
which I need to update the misc. regfile accesses
arch/mips/faults.cc:
arch/mips/faults.hh:
alpha to mips
arch/mips/isa/base.isa:
add includes
arch/mips/isa/bitfields.isa:
more bitfields
arch/mips/isa/decoder.isa:
lots o' lots o' lots o' changes!!!!
arch/mips/isa/formats.isa:
include cop0.isa
arch/mips/isa/formats/basic.isa:
fix faults
arch/mips/isa/formats/branch.isa:
arch/mips/isa/formats/fp.isa:
arch/mips/isa/formats/int.isa:
arch/mips/isa/formats/mem.isa:
arch/mips/isa/formats/noop.isa:
arch/mips/isa/formats/trap.isa:
arch/mips/isa/formats/unimp.isa:
arch/mips/isa/formats/unknown.isa:
arch/mips/isa/formats/util.isa:
arch/mips/isa/operands.isa:
arch/mips/isa_traits.cc:
arch/mips/linux_process.cc:
merge MIPS-specific comilable/buidable files code into multiarch
arch/mips/isa_traits.hh:
merge MIPS-specific comilable/buidable files code into multiarch... the miscRegs file accesses i have
need to be recoded and everything should build then ...
arch/mips/stacktrace.hh:
file copied over
--HG--
extra : convert_revision : 4a72e14fc5fb0a0d1f8b205dadbbf69636b7fb1f
Edits to the CPU model may still need to be made to handle branch likely insts...
arch/isa_parser.py:
add a NNPC operand ...
arch/mips/isa/base.isa:
change SPARC to MIPS
arch/mips/isa/decoder.isa:
typo < to >=
arch/mips/isa/formats/basic.isa:
spacing
arch/mips/isa/formats/branch.isa:
add code for branch instructions (still need adjustments for the branch likely)
arch/mips/isa/operands.isa:
support for NNPC and R31
arch/mips/isa_traits.hh:
NNPC Addr variable
--HG--
extra : convert_revision : df03d2a71c36dbc00270c2e3d7882b4f09ed97ad
SConscript:
Moved some files out of targetarch. The either no longer need to be there, never needed to be there, or should be referred to directly in arch/alpha due to there strictly alpha content.
arch/alpha/isa_traits.hh:
Added alpha's endianness to it's isa_traits.hh
arch/mips/isa_traits.hh:
Added MIPS endianness to it's isa_traits.hh
arch/sparc/isa_traits.hh:
Added SPARCs endianess to it's isa_traits.hh
build/SConstruct:
Added MIPS as a valid architecture
cpu/exec_context.hh:
Included arch/isa_traits.hh to bring in the endianness of the system.
cpu/o3/alpha_cpu.hh:
Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding of little endianness
cpu/o3/fetch_impl.hh:
kern/freebsd/freebsd_system.cc:
Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding to little endianness.
sim/system.cc:
Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding to little endian.
--HG--
extra : convert_revision : b1ab34b7569db531cd1c74f273b24222e63f9007
