Redo the FloatRegFile using unsigned integers
Edit the convert_and_round function which access FloatRegFile
arch/isa_parser.py:
recognize when we are writing a 'uint64_t' FloatReg and set the width appropriately
arch/mips/isa/decoder.isa:
Send a 'float' to the convert function instead of a unsigned word. Do this so we dont have to worry about the
bit manipulation ourselves. We can just concern ourselves with values.
Use unsigned double to get movd...
arch/mips/isa/formats/fp.isa:
float debug statement
arch/mips/isa_traits.cc:
add different versions of convert_and_round functions
arch/mips/isa_traits.hh:
Use an array of uint32_t unsigned integers to represent the Floating Point Regfile
configs/test/hello_mips:
basic FP program
cpu/simple/cpu.hh:
spacing
--HG--
extra : convert_revision : a6fca91ad6365c83025f1131d71fa1b8ee76d7bc
This commit is contained in:
Korey Sewell
parent
2d077df1a0
commit
97429d8eee
7 changed files with 124 additions and 55 deletions
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@ -1251,6 +1251,9 @@ class FloatRegOperand(Operand):
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elif (self.ctype == 'double'):
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width = 64
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func = 'setFloatReg'
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elif (self.ctype == 'uint64_t'):
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func = 'setFloatRegBits'
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width = 64
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else:
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func = 'setFloatRegBits'
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final_ctype = 'uint%d_t' % self.dflt_size
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@ -397,7 +397,7 @@ decode OPCODE_HI default Unknown::unknown() {
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format FloatOp {
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0x0: mfc1 ({{ Rt.uw = Fs.uw<31:0>; }});
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0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>;}});
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0x4: mtc1 ({{ Fs.uw = Rt.uw; }});
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0x4: mtc1 ({{ Fs.uw = Rt.uw; }});
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0x7: mthc1({{
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uint64_t fs_hi = Rt.ud << 32;
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uint64_t fs_lo = Fs.ud & 0x0000FFFF;
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@ -572,7 +572,7 @@ decode OPCODE_HI default Unknown::unknown() {
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format FloatOp {
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0x1: cvt_d_s({{
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int rnd_mode = xc->readMiscReg(FCSR) & 0x03;
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Fd.ud = convert_and_round(Fs.uw, SINGLE_TO_DOUBLE, rnd_mode);
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Fd.ud = convert_and_round(Fs.sf, SINGLE_TO_DOUBLE, rnd_mode);
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}});
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0x4: cvt_w_s({{
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@ -605,7 +605,7 @@ decode OPCODE_HI default Unknown::unknown() {
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0x3: divd({{ Fd.df = Fs.df / Ft.df;}});
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0x4: sqrtd({{ Fd.df = sqrt(Fs.df);}});
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0x5: absd({{ Fd.df = fabs(Fs.df);}});
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0x6: movd({{ Fd.df = Fs.df;}});
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0x6: movd({{ Fd.ud = Fs.ud;}});
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0x7: negd({{ Fd.df = -1 * Fs.df;}});
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}
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}
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@ -32,6 +32,7 @@ output decoder {{
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// Primary format for float operate instructions:
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def format FloatOp(code, *flags) {{
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code = 'std::cout << "Floating Point Op" << std::endl;\n' + code
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iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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@ -41,6 +42,7 @@ def format FloatOp(code, *flags) {{
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// Primary format for float64 operate instructions:
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def format Float64Op(code, *flags) {{
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code = 'std::cout << "Floating Point 64" << std::endl;\n' + code
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iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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@ -30,25 +30,95 @@
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#include "config/full_system.hh"
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#include "cpu/static_inst.hh"
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#include "sim/serialize.hh"
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#include "base/bitfield.hh"
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using namespace MipsISA;
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using namespace std;
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uint64_t
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MipsISA::convert_and_round(uint64_t fp_val, ConvertType cvt_type, int rnd_mode)
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MipsISA::convert_and_round(uint32_t fp_val, ConvertType cvt_type, int rnd_mode)
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{
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uint64_t ret_val = 0;
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switch (cvt_type)
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{
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case SINGLE_TO_DOUBLE:
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uint64_t single_sign = fp_val & 0x80000000;
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break;
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uint64_t single_exp = (fp_val & 0x7F800000) >> 22;
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single_exp -= 127;
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uint64_t single_mantissa = fp_val & 0x007FFFFF;
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uint64_t double_exp = single_exp + 1023;
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double_exp = double_exp << 51;
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uint64_t double_val = single_sign << 63 | double_exp | single_mantissa;
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return double_val;
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default:
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panic("Invalid Floating Point Conversion Type (%d) being used.\n",cvt_type);
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return ret_val;
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}
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}
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return ret_val;
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uint64_t
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MipsISA::convert_and_round(uint64_t fp_val, ConvertType cvt_type, int rnd_mode)
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{
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uint64_t ret_val = 0;
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switch (cvt_type)
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{
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case SINGLE_TO_DOUBLE:
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uint64_t single_sign = fp_val & 0x80000000;
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uint64_t single_exp = (fp_val & 0x7F800000) >> 22;
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single_exp -= 127;
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uint64_t single_mantissa = fp_val & 0x007FFFFF;
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uint64_t double_exp = single_exp + 1023;
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double_exp = double_exp << 51;
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uint64_t double_val = single_sign << 63 | double_exp | single_mantissa;
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return double_val;
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default:
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panic("Invalid Floating Point Conversion Type (%d) being used.\n",cvt_type);
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return ret_val;
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}
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}
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uint64_t
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MipsISA::convert_and_round(float fp_val, ConvertType cvt_type, int rnd_mode)
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{
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void * ptr = &fp_val;
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uint32_t fp_bits = * (uint32_t *) ptr;
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cout << "Converting " << fp_val << " (" << hex << fp_bits << ") " << endl;
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uint64_t ret_val = 0;
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switch (cvt_type)
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{
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case SINGLE_TO_DOUBLE:
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double double_val = fp_val;
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void *double_ptr = &double_val;
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uint64_t dp_bits = *(uint64_t *) double_ptr ;
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cout << "To " << double_val << " (" << hex << dp_bits << ") " << endl;
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double_ptr = &dp_bits;
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cout << "Testing: " << *(double *) double_ptr << endl;
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return dp_bits;
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default:
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panic("Invalid Floating Point Conversion Type (%d) being used.\n",cvt_type);
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return ret_val;
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}
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}
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void
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@ -189,21 +189,24 @@ namespace MipsISA
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};
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typedef double FloatReg;
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typedef float FloatReg;
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typedef uint32_t FloatReg32;
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typedef uint64_t FloatReg64;
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typedef uint64_t FloatRegBits;
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// const uint64_t hi_mask64 = 0xFFFFFFFF00000000;
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//const uint64_t lo_mask64 = 0x00000000FFFFFFFF;
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const int SingleWidth = 32;
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const int SingleBytes = SingleWidth / 4;
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const int SingleBytes = 4;
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const int DoubleWidth = 64;
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const int DoubleBytes = DoubleWidth / 4;
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const int DoubleBytes = 8;
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const int QuadWidth = 128;
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const int QuadBytes = QuadWidth / 4;
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const int FloatRegSize = SingleWidth / SingleBytes;
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const int DoubleRegSize = FloatRegSize * 2;
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class FloatRegFile
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{
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protected:
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@ -211,31 +214,27 @@ namespace MipsISA
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//Since the floating point registers overlap each other,
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//A generic storage space is used. The float to be returned is
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//pulled from the appropriate section of this region.
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char regSpace[FloatRegSize * NumFloatRegs];
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//char regSpace[SingleBytes * NumFloatRegs];
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FloatReg32 regs[NumFloatRegs];
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public:
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void clear()
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{
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bzero(regSpace, sizeof(regSpace));
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bzero(regs, sizeof(regs));
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}
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FloatReg readReg(int floatReg, int width)
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double readReg(int floatReg, int width)
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{
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//In each of these cases, we have to copy the value into a temporary
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//variable. This is because we may otherwise try to access an
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//unaligned portion of memory.
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switch(width)
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{
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case SingleWidth:
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float result32;
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memcpy(&result32, regSpace + 4 * floatReg, FloatRegSize);
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return htog(result32);
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void *float_ptr = ®s[floatReg];
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return *(float *) float_ptr;
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case DoubleWidth:
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double result64;
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memcpy(&result64, regSpace + 4 * floatReg, DoubleRegSize);
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return htog(result64);
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void *double_ptr = ®s[floatReg];
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return *(double *) double_ptr;
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default:
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panic("Attempted to read a %d bit floating point register!", width);
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@ -244,20 +243,17 @@ namespace MipsISA
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FloatRegBits readRegBits(int floatReg, int width)
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{
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//In each of these cases, we have to copy the value into a temporary
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//variable. This is because we may otherwise try to access an
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//unaligned portion of memory.
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using namespace std;
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switch(width)
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{
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case SingleWidth:
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uint32_t result32;
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memcpy(&result32, regSpace + 4 * floatReg, FloatRegSize);
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return htog(result32);
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return regs[floatReg];
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case DoubleWidth:
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uint64_t result64;
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memcpy(&result64, regSpace + 4 * floatReg, DoubleRegSize);
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return htog(result64);
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cout << hex << "Combining " << regs[floatReg + 1] << " & " << regs[floatReg + 1] << endl;
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cout << hex << "Returning " << ((FloatReg64)regs[floatReg] << 32 | regs[floatReg + 1]) << endl;
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return (FloatReg64)regs[floatReg] << 32 | regs[floatReg + 1];
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default:
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panic("Attempted to read a %d bit floating point register!", width);
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@ -266,47 +262,45 @@ namespace MipsISA
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Fault setReg(int floatReg, const FloatReg &val, int width)
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{
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//In each of these cases, we have to copy the value into a temporary
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//variable. This is because we may otherwise try to access an
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//unaligned portion of memory.
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switch(width)
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{
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case SingleWidth:
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uint32_t result32;
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result32 = gtoh((uint32_t)val);
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memcpy(regSpace + 4 * floatReg, &result32, FloatRegSize);
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float temp = val;
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void *float_ptr = &temp;
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regs[floatReg] = *(FloatReg32 *) float_ptr;
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break;
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case DoubleWidth:
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uint64_t result64;
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result64 = gtoh((uint64_t)val);
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memcpy(regSpace + 4 * floatReg, &result64, DoubleRegSize);
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const void *double_ptr = &val;
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FloatReg64 temp_double = *(FloatReg64 *) double_ptr;
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regs[floatReg] = temp_double >> 32;
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regs[floatReg + 1] = temp_double;
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break;
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default:
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panic("Attempted to read a %d bit floating point register!", width);
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}
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return NoFault;
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}
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Fault setRegBits(int floatReg, const FloatRegBits &val, int width)
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{
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//In each of these cases, we have to copy the value into a temporary
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//variable. This is because we may otherwise try to access an
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//unaligned portion of memory.
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using namespace std;
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switch(width)
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{
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case SingleWidth:
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uint32_t result32;
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result32 = gtoh((uint32_t)val);
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memcpy(regSpace + 4 * floatReg, &result32, FloatRegSize);
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regs[floatReg] = val;
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break;
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case DoubleWidth:
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uint64_t result64;
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result64 = gtoh((uint64_t)val);
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memcpy(regSpace + 4 * floatReg, &result64, DoubleRegSize);
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cout << hex << "Setting val: " << val << endl;
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regs[floatReg] = val >> 32;
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regs[floatReg + 1] = val;
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cout << dec << "f" << floatReg << ": " << hex<< readRegBits(floatReg,32) << endl;
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cout << dec << "f" << floatReg + 1 << ": " << hex << readRegBits(floatReg+1,32) << endl;
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break;
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default:
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@ -348,8 +342,9 @@ namespace MipsISA
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RND_NEAREST
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};
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uint64_t convert_and_round(uint32_t fp_val,ConvertType cvt_type, int rnd_mode = 0);
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uint64_t convert_and_round(uint64_t fp_val,ConvertType cvt_type, int rnd_mode = 0);
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uint64_t convert_and_round(float fp_val,ConvertType cvt_type, int rnd_mode = 0);
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void copyRegs(ExecContext *src, ExecContext *dest);
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@ -637,7 +632,6 @@ extern const Addr PageOffset;
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return miscRegFile.setRegWithEffect(miscReg, val, xc);
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}
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FloatReg readFloatReg(int floatReg)
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{
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return floatRegFile.readReg(floatReg,SingleWidth);
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Binary file not shown.
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@ -369,7 +369,7 @@ class SimpleCPU : public BaseCPU
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}
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void setFloatRegBits(const StaticInst *si, int idx,
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FloatRegBits val, int width)
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FloatRegBits val, int width)
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{
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int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
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cpuXC->setFloatRegBits(reg_idx, val, width);
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