a48c24b61e
Edits to the CPU model may still need to be made to handle branch likely insts...
arch/isa_parser.py:
add a NNPC operand ...
arch/mips/isa/base.isa:
change SPARC to MIPS
arch/mips/isa/decoder.isa:
typo < to >=
arch/mips/isa/formats/basic.isa:
spacing
arch/mips/isa/formats/branch.isa:
add code for branch instructions (still need adjustments for the branch likely)
arch/mips/isa/operands.isa:
support for NNPC and R31
arch/mips/isa_traits.hh:
NNPC Addr variable
--HG--
extra : convert_revision : df03d2a71c36dbc00270c2e3d7882b4f09ed97ad
535 lines
22 KiB
C++
535 lines
22 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_MIPS_ISA_TRAITS_HH__
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#define __ARCH_MIPS_ISA_TRAITS_HH__
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//This makes sure the big endian versions of certain functions are used.
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namespace LittleEndianGuest {}
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using namespace LittleEndianGuest
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#include "arch/mips/faults.hh"
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#include "base/misc.hh"
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#include "sim/host.hh"
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class FastCPU;
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class FullCPU;
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class Checkpoint;
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#define TARGET_MIPS
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template <class ISA> class StaticInst;
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template <class ISA> class StaticInstPtr;
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//namespace EV5
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//{
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// int DTB_ASN_ASN(uint64_t reg);
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// int ITB_ASN_ASN(uint64_t reg);
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//}
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class MipsISA
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{
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public:
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typedef uint32_t MachInst;
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typedef uint64_t Addr;
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typedef uint8_t RegIndex;
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enum
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{
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MemoryEnd = 0xffffffffffffffffULL,
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NumFloatRegs = 32,
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NumMiscRegs = 32,
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MaxRegsOfAnyType = 32,
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// Static instruction parameters
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MaxInstSrcRegs = 3,
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MaxInstDestRegs = 2,
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// Maximum trap level
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MaxTL = 4
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// semantically meaningful register indices
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ZeroReg = 0, // architecturally meaningful
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// the rest of these depend on the ABI
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}
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typedef uint64_t IntReg;
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class IntRegFile
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{
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private:
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//For right now, let's pretend the register file is static
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IntReg regs[32];
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public:
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IntReg & operator [] (RegIndex index)
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{
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//Don't allow indexes outside of the 32 registers
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index &= 0x1F
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return regs[index];
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}
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};
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void inline serialize(std::ostream & os)
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{
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SERIALIZE_ARRAY(regs, 32);
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}
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void inline unserialize(Checkpoint &*cp, const std::string §ion)
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{
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UNSERIALIZE_ARRAY(regs, 32);
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}
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class FloatRegFile
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{
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private:
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//By using the largest data type, we ensure everything
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//is aligned correctly in memory
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union
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{
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double double rawRegs[16];
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uint64_t regDump[32];
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};
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class QuadRegs
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{
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private:
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FloatRegFile * parent;
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public:
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QuadRegs(FloatRegFile * p) : parent(p) {;}
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double double & operator [] (RegIndex index)
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{
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//Quad floats are index by the single
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//precision register the start on,
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//and only 16 should be accessed
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index = (index >> 2) & 0xF;
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return parent->rawRegs[index];
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}
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};
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class DoubleRegs
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{
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private:
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FloatRegFile * parent;
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public:
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DoubleRegs(FloatRegFile * p) : parent(p) {;}
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double & operator [] (RegIndex index)
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{
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//Double floats are index by the single
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//precision register the start on,
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//and only 32 should be accessed
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index = (index >> 1) & 0x1F
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return ((double [])parent->rawRegs)[index];
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}
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}
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class SingleRegs
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{
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private:
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FloatRegFile * parent;
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public:
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SingleRegs(FloatRegFile * p) : parent(p) {;}
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double & operator [] (RegFile index)
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{
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//Only 32 single floats should be accessed
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index &= 0x1F
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return ((float [])parent->rawRegs)[index];
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}
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}
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public:
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void inline serialize(std::ostream & os)
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{
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SERIALIZE_ARRAY(regDump, 32);
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}
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void inline unserialize(Checkpoint &* cp, std::string & section)
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{
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UNSERIALIZE_ARRAY(regDump, 32);
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}
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QuadRegs quadRegs;
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DoubleRegs doubleRegs;
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SingleRegs singleRegs;
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FloatRegFile() : quadRegs(this), doubleRegs(this), singleRegs(this)
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{;}
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};
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// control register file contents
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typedef uint64_t MiscReg;
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// The control registers, broken out into fields
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class MiscRegFile
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{
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public:
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union
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{
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uint16_t pstate; // Process State Register
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struct
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{
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uint16_t ag:1; // Alternate Globals
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uint16_t ie:1; // Interrupt enable
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uint16_t priv:1; // Privelege mode
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uint16_t am:1; // Address mask
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uint16_t pef:1; // PSTATE enable floating-point
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uint16_t red:1; // RED (reset, error, debug) state
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uint16_t mm:2; // Memory Model
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uint16_t tle:1; // Trap little-endian
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uint16_t cle:1; // Current little-endian
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} pstateFields;
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}
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uint64_t tba; // Trap Base Address
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union
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{
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uint64_t y; // Y (used in obsolete multiplication)
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struct
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{
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uint64_t value:32; // The actual value stored in y
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const uint64_t :32; // reserved bits
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} yFields;
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}
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uint8_t pil; // Process Interrupt Register
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uint8_t cwp; // Current Window Pointer
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uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured on the previous level)
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union
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{
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uint8_t ccr; // Condition Code Register
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struct
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{
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union
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{
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uint8_t icc:4; // 32-bit condition codes
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struct
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{
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uint8_t c:1; // Carry
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uint8_t v:1; // Overflow
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uint8_t z:1; // Zero
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uint8_t n:1; // Negative
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} iccFields:4;
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} :4;
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union
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{
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uint8_t xcc:4; // 64-bit condition codes
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struct
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{
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uint8_t c:1; // Carry
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uint8_t v:1; // Overflow
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uint8_t z:1; // Zero
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uint8_t n:1; // Negative
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} xccFields:4;
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} :4;
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} ccrFields;
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}
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uint8_t asi; // Address Space Identifier
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uint8_t tl; // Trap Level
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uint64_t tpc[MaxTL]; // Trap Program Counter (value from previous trap level)
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uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from previous trap level)
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union
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{
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uint64_t tstate[MaxTL]; // Trap State
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struct
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{
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//Values are from previous trap level
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uint64_t cwp:5; // Current Window Pointer
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const uint64_t :2; // Reserved bits
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uint64_t pstate:10; // Process State
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const uint64_t :6; // Reserved bits
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uint64_t asi:8; // Address Space Identifier
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uint64_t ccr:8; // Condition Code Register
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} tstateFields[MaxTL];
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}
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union
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{
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uint64_t tick; // Hardware clock-tick counter
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struct
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{
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uint64_t counter:63; // Clock-tick count
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uint64_t npt:1; // Non-priveleged trap
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} tickFields;
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}
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uint8_t cansave; // Savable windows
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uint8_t canrestore; // Restorable windows
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uint8_t otherwin; // Other windows
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uint8_t cleanwin; // Clean windows
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union
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{
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uint8_t wstate; // Window State
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struct
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{
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uint8_t normal:3; // Bits TT<4:2> are set to on a normal
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// register window trap
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uint8_t other:3; // Bits TT<4:2> are set to on an "otherwin"
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// register window trap
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} wstateFields;
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}
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union
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{
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uint64_t ver; // Version
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struct
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{
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uint64_t maxwin:5; // Max CWP value
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const uint64_t :2; // Reserved bits
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uint64_t maxtl:8; // Maximum trap level
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const uint64_t :8; // Reserved bits
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uint64_t mask:8; // Processor mask set revision number
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uint64_t impl:16; // Implementation identification number
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uint64_t manuf:16; // Manufacturer code
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} verFields;
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}
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union
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{
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uint64_t fsr; // Floating-Point State Register
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struct
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{
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union
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{
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uint64_t cexc:5; // Current excpetion
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struct
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{
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uint64_t nxc:1; // Inexact
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uint64_t dzc:1; // Divide by zero
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uint64_t ufc:1; // Underflow
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uint64_t ofc:1; // Overflow
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uint64_t nvc:1; // Invalid operand
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} cexecFields:5;
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} :5;
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union
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{
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uint64_t aexc:5; // Accrued exception
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struct
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{
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uint64_t nxc:1; // Inexact
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uint64_t dzc:1; // Divide by zero
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uint64_t ufc:1; // Underflow
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uint64_t ofc:1; // Overflow
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uint64_t nvc:1; // Invalid operand
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} aexecFields:5;
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} :5;
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uint64_t fcc0:2; // Floating-Point condtion codes
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const uint64_t :1; // Reserved bits
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uint64_t qne:1; // Deferred trap queue not empty
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// with no queue, it should read 0
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uint64_t ftt:3; // Floating-Point trap type
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uint64_t ver:3; // Version (of the FPU)
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const uint64_t :2; // Reserved bits
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uint64_t ns:1; // Nonstandard floating point
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union
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{
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uint64_t tem:5; // Trap Enable Mask
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struct
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{
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uint64_t nxm:1; // Inexact
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uint64_t dzm:1; // Divide by zero
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uint64_t ufm:1; // Underflow
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uint64_t ofm:1; // Overflow
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uint64_t nvm:1; // Invalid operand
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} temFields:5;
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} :5;
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const uint64_t :2; // Reserved bits
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uint64_t rd:2; // Rounding direction
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uint64_t fcc1:2; // Floating-Point condition codes
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uint64_t fcc2:2; // Floating-Point condition codes
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uint64_t fcc3:2; // Floating-Point condition codes
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const uint64_t :26; // Reserved bits
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} fsrFields;
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}
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union
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{
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uint8_t fprs; // Floating-Point Register State
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struct
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{
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dl:1; // Dirty lower
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du:1; // Dirty upper
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fef:1; // FPRS enable floating-Point
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} fprsFields;
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};
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void serialize(std::ostream & os)
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{
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SERIALIZE_SCALAR(pstate);
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SERIAlIZE_SCALAR(tba);
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SERIALIZE_SCALAR(y);
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SERIALIZE_SCALAR(pil);
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SERIALIZE_SCALAR(cwp);
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SERIALIZE_ARRAY(tt, MaxTL);
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SERIALIZE_SCALAR(ccr);
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SERIALIZE_SCALAR(asi);
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SERIALIZE_SCALAR(tl);
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SERIALIZE_SCALAR(tpc);
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SERIALIZE_SCALAR(tnpc);
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SERIALIZE_ARRAY(tstate, MaxTL);
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SERIALIZE_SCALAR(tick);
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SERIALIZE_SCALAR(cansave);
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SERIALIZE_SCALAR(canrestore);
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SERIALIZE_SCALAR(otherwin);
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SERIALIZE_SCALAR(cleanwin);
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SERIALIZE_SCALAR(wstate);
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SERIALIZE_SCALAR(ver);
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SERIALIZE_SCALAR(fsr);
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SERIALIZE_SCALAR(fprs);
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}
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void unserialize(Checkpoint &* cp, std::string & section)
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{
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UNSERIALIZE_SCALAR(pstate);
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UNSERIAlIZE_SCALAR(tba);
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UNSERIALIZE_SCALAR(y);
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UNSERIALIZE_SCALAR(pil);
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UNSERIALIZE_SCALAR(cwp);
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UNSERIALIZE_ARRAY(tt, MaxTL);
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UNSERIALIZE_SCALAR(ccr);
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UNSERIALIZE_SCALAR(asi);
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UNSERIALIZE_SCALAR(tl);
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UNSERIALIZE_SCALAR(tpc);
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UNSERIALIZE_SCALAR(tnpc);
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UNSERIALIZE_ARRAY(tstate, MaxTL);
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UNSERIALIZE_SCALAR(tick);
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UNSERIALIZE_SCALAR(cansave);
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UNSERIALIZE_SCALAR(canrestore);
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UNSERIALIZE_SCALAR(otherwin);
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UNSERIALIZE_SCALAR(cleanwin);
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UNSERIALIZE_SCALAR(wstate);
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UNSERIALIZE_SCALAR(ver);
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UNSERIALIZE_SCALAR(fsr);
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UNSERIALIZE_SCALAR(fprs);
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}
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};
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typedef union
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{
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IntReg intreg;
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FloatReg fpreg;
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MiscReg ctrlreg;
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} AnyReg;
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struct RegFile
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{
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IntRegFile intRegFile; // (signed) integer register file
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FloatRegFile floatRegFile; // floating point register file
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MiscRegFile miscRegFile; // control register file
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Addr pc; // Program Counter
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Addr npc; // Next Program Counter
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Addr nnpc; // Next next program Counter
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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};
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static StaticInstPtr<AlphaISA> decodeInst(MachInst);
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// return a no-op instruction... used for instruction fetch faults
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static const MachInst NoopMachInst;
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// Instruction address compression hooks
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static inline Addr realPCToFetchPC(const Addr &addr)
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{
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return addr;
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}
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static inline Addr fetchPCToRealPC(const Addr &addr)
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{
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return addr;
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}
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// the size of "fetched" instructions (not necessarily the size
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// of real instructions for PISA)
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static inline size_t fetchInstSize()
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{
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return sizeof(MachInst);
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}
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/**
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* Function to insure ISA semantics about 0 registers.
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* @param xc The execution context.
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*/
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template <class XC>
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static void zeroRegisters(XC *xc);
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};
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typedef MIPSISA TheISA;
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typedef TheISA::MachInst MachInst;
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typedef TheISA::Addr Addr;
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typedef TheISA::RegIndex RegIndex;
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typedef TheISA::IntReg IntReg;
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typedef TheISA::IntRegFile IntRegFile;
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typedef TheISA::FloatReg FloatReg;
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typedef TheISA::FloatRegFile FloatRegFile;
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typedef TheISA::MiscReg MiscReg;
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typedef TheISA::MiscRegFile MiscRegFile;
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typedef TheISA::AnyReg AnyReg;
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typedef TheISA::RegFile RegFile;
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const int VMPageSize = TheISA::VMPageSize;
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const int LogVMPageSize = TheISA::LogVMPageSize;
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const int ZeroReg = TheISA::ZeroReg;
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const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
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const int MaxAddr = (Addr)-1;
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#ifndef FULL_SYSTEM
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class SyscallReturn {
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public:
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template <class T>
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SyscallReturn(T v, bool s)
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{
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retval = (uint64_t)v;
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success = s;
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}
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template <class T>
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SyscallReturn(T v)
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{
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success = (v >= 0);
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retval = (uint64_t)v;
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}
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~SyscallReturn() {}
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SyscallReturn& operator=(const SyscallReturn& s) {
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retval = s.retval;
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success = s.success;
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return *this;
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}
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bool successful() { return success; }
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uint64_t value() { return retval; }
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private:
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uint64_t retval;
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bool success;
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};
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#endif
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#ifdef FULL_SYSTEM
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#include "arch/alpha/ev5.hh"
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#endif
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#endif // __ARCH_MIPS_ISA_TRAITS_HH__
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