8ddd509c7c
arch/mips/isa/decoder.isa:
arch/mips/isa_traits.hh:
sim/syscall_emul.cc:
make syscall instruction functional
arch/mips/linux_process.cc:
add all MIPS/Linux syscalls to descriptor list
--HG--
extra : convert_revision : 5455a345e76be921e9f63b248aef874b6358e465
635 lines
18 KiB
C++
635 lines
18 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_MIPS_ISA_TRAITS_HH__
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#define __ARCH_MIPS_ISA_TRAITS_HH__
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//#include "arch/mips/misc_regfile.hh"
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#include "base/misc.hh"
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#include "config/full_system.hh"
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#include "sim/host.hh"
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#include "sim/faults.hh"
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#include <vector>
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class FastCPU;
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class FullCPU;
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class Checkpoint;
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class ExecContext;
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namespace LittleEndianGuest {};
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using namespace LittleEndianGuest;
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#define TARGET_MIPS
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class StaticInst;
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class StaticInstPtr;
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namespace MIPS34K {
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int DTB_ASN_ASN(uint64_t reg);
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int ITB_ASN_ASN(uint64_t reg);
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};
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#if !FULL_SYSTEM
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class SyscallReturn {
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public:
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template <class T>
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SyscallReturn(T v, bool s)
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{
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retval = (uint64_t)v;
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success = s;
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}
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template <class T>
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SyscallReturn(T v)
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{
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success = (v >= 0);
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retval = (uint64_t)v;
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}
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~SyscallReturn() {}
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SyscallReturn& operator=(const SyscallReturn& s) {
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retval = s.retval;
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success = s.success;
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return *this;
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}
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bool successful() { return success; }
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uint64_t value() { return retval; }
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private:
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uint64_t retval;
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bool success;
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};
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#endif
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namespace MipsISA
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{
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typedef uint32_t MachInst;
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typedef uint32_t MachInst;
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typedef uint64_t ExtMachInst;
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typedef uint8_t RegIndex;
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// typedef uint64_t Addr;
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// Constants Related to the number of registers
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const int NumIntArchRegs = 32;
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const int NumPALShadowRegs = 8;
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const int NumFloatArchRegs = 32;
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// @todo: Figure out what this number really should be.
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const int NumMiscArchRegs = 32;
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const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs;
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const int NumFloatRegs = NumFloatArchRegs;
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const int NumMiscRegs = NumMiscArchRegs;
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const int TotalNumRegs = NumIntRegs + NumFloatRegs +
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NumMiscRegs + 0/*NumInternalProcRegs*/;
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const int TotalDataRegs = NumIntRegs + NumFloatRegs;
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// Static instruction parameters
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const int MaxInstSrcRegs = 3;
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const int MaxInstDestRegs = 2;
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// semantically meaningful register indices
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const int ZeroReg = 0;
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const int AssemblerReg = 1;
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const int ReturnValueReg1 = 2;
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const int ReturnValueReg2 = 3;
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const int ArgumentReg0 = 4;
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const int ArgumentReg1 = 5;
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const int ArgumentReg2 = 6;
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const int ArgumentReg3 = 7;
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const int KernelReg0 = 26;
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const int KernelReg1 = 27;
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const int GlobalPointerReg = 28;
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const int StackPointerReg = 29;
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const int FramePointerReg = 30;
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const int ReturnAddressReg = 31;
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const int SyscallNumReg = ReturnValueReg1;
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const int SyscallPseudoReturnReg = ArgumentReg3;
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const int SyscallSuccessReg = 19;
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const int LogVMPageSize = 13; // 8K bytes
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const int VMPageSize = (1 << LogVMPageSize);
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const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
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const int MachineBytes = 4;
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const int WordBytes = 4;
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const int HalfwordBytes = 2;
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const int ByteBytes = 1;
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// These enumerate all the registers for dependence tracking.
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enum DependenceTags {
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// 0..31 are the integer regs 0..31
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// 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
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FP_Base_DepTag = 32,
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Ctrl_Base_DepTag = 64,
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Fpcr_DepTag = 64, // floating point control register
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Uniq_DepTag = 65,
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IPR_Base_DepTag = 66,
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MiscReg_DepTag = 67
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};
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typedef uint64_t IntReg;
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typedef IntReg IntRegFile[NumIntRegs];
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/* floating point register file entry type
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typedef union {
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uint64_t q;
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double d;
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} FloatReg;*/
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typedef double FloatReg;
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typedef uint64_t FloatRegBits;
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/*typedef union {
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uint64_t q[NumFloatRegs]; // integer qword view
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double d[NumFloatRegs]; // double-precision floating point view
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} FloatRegFile;*/
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class FloatRegFile
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{
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protected:
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FloatRegBits q[NumFloatRegs]; // integer qword view
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double d[NumFloatRegs]; // double-precision floating point view
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public:
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FloatReg readReg(int floatReg)
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{
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return d[floatReg];
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}
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FloatReg readReg(int floatReg, int width)
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{
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return readReg(floatReg);
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}
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FloatRegBits readRegBits(int floatReg)
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{
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return q[floatReg];
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}
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FloatRegBits readRegBits(int floatReg, int width)
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{
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return readRegBits(floatReg);
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}
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Fault setReg(int floatReg, const FloatReg &val)
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{
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d[floatReg] = val;
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return NoFault;
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}
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Fault setReg(int floatReg, const FloatReg &val, int width)
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{
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return setReg(floatReg, val);
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}
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Fault setRegBits(int floatReg, const FloatRegBits &val)
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{
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q[floatReg] = val;
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return NoFault;
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}
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Fault setRegBits(int floatReg, const FloatRegBits &val, int width)
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{
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return setRegBits(floatReg, val);
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}
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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};
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void copyRegs(ExecContext *src, ExecContext *dest);
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// cop-0/cop-1 system control register file
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typedef uint64_t MiscReg;
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//typedef MiscReg MiscRegFile[NumMiscRegs];
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class MiscRegFile {
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protected:
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uint64_t fpcr; // floating point condition codes
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uint64_t uniq; // process-unique register
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bool lock_flag; // lock flag for LL/SC
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Addr lock_addr; // lock address for LL/SC
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MiscReg miscRegFile[NumMiscRegs];
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public:
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//These functions should be removed once the simplescalar cpu model
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//has been replaced.
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int getInstAsid();
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int getDataAsid();
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void copyMiscRegs(ExecContext *xc);
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MiscReg readReg(int misc_reg)
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{ return miscRegFile[misc_reg]; }
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MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc)
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{ return miscRegFile[misc_reg];}
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Fault setReg(int misc_reg, const MiscReg &val)
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{ miscRegFile[misc_reg] = val; return NoFault; }
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Fault setRegWithEffect(int misc_reg, const MiscReg &val,
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ExecContext *xc)
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{ miscRegFile[misc_reg] = val; return NoFault; }
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#if FULL_SYSTEM
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void clearIprs() { }
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protected:
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InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
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private:
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MiscReg readIpr(int idx, Fault &fault, ExecContext *xc) { }
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Fault setIpr(int idx, uint64_t val, ExecContext *xc) { }
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#endif
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friend class RegFile;
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};
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enum MiscRegTags {
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//Coprocessor 0 Registers
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//Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
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//(Register Number-Register Select) Summary of Register
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//------------------------------------------------------
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Index = 0, //0-0 Index into the TLB array
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MVPControl = 1, //0-1 Per-processor register containing global
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//MIPS<50> MT configuration data
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MVPConf0 = 2, //0-2 Per-processor register containing global
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//MIPS<50> MT configuration data
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MVPConf1 = 3, //0-3 Per-processor register containing global
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//MIPS<50> MT configuration data
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Random = 8, //1-0 Randomly generated index into the TLB array
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VPEControl = 9, //1-1 Per-VPE register containing relatively volatile
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//thread configuration data
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VPEConf0 = 10, //1-2 Per-VPE multi-thread configuration
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//information
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VPEConf1 = 11, //1-2 Per-VPE multi-thread configuration
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//information
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YQMask = 12, //Per-VPE register defining which YIELD
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//qualifier bits may be used without generating
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//an exception
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VPESchedule = 13,
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VPEScheFBack = 14,
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VPEOpt = 15,
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EntryLo0 = 16, // Bank 3: 16 - 23
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TCStatus = 17,
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TCBind = 18,
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TCRestart = 19,
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TCHalt = 20,
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TCContext = 21,
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TCSchedule = 22,
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TCScheFBack = 23,
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EntryLo1 = 24,// Bank 4: 24 - 31
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Context = 32, // Bank 5: 32 - 39
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ContextConfig = 33,
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//PageMask = 40, //Bank 6: 40 - 47
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PageGrain = 41,
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Wired = 48, //Bank 7:48 - 55
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SRSConf0 = 49,
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SRSConf1 = 50,
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SRSConf2 = 51,
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SRSConf3 = 52,
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SRSConf4 = 53,
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BadVAddr = 54,
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HWRena = 56,//Bank 8:56 - 63
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Count = 64, //Bank 9:64 - 71
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EntryHi = 72,//Bank 10:72 - 79
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Compare = 80,//Bank 11:80 - 87
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Status = 88,//Bank 12:88 - 96 //12-0 Processor status and control
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IntCtl = 89, //12-1 Interrupt system status and control
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SRSCtl = 90, //12-2 Shadow register set status and control
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SRSMap = 91, //12-3 Shadow set IPL mapping
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Cause = 97,//97-104 //13-0 Cause of last general exception
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EPC = 105,//105-112 //14-0 Program counter at last exception
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PRId = 113,//113-120, //15-0 Processor identification and revision
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EBase = 114, //15-1 Exception vector base register
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Config = 121,//Bank 16: 121-128
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Config1 = 122,
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Config2 = 123,
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Config3 = 124,
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Config6 = 127,
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Config7 = 128,
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LLAddr = 129,//Bank 17: 129-136
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WatchLo0 = 137,//Bank 18: 137-144
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WatchLo1 = 138,
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WatchLo2 = 139,
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WatchLo3 = 140,
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WatchLo4 = 141,
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WatchLo5 = 142,
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WatchLo6 = 143,
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WatchLo7 = 144,
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WatchHi0 = 145,//Bank 19: 145-152
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WatchHi1 = 146,
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WatchHi2 = 147,
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WatchHi3 = 148,
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WatchHi4 = 149,
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WatchHi5 = 150,
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WatchHi6 = 151,
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WatchHi7 = 152,
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XCContext64 = 153,//Bank 20: 153-160
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//Bank 21: 161-168
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//Bank 22: 169-176
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Debug = 177, //Bank 23: 177-184
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TraceControl1 = 178,
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TraceControl2 = 179,
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UserTraceData = 180,
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TraceBPC = 181,
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DEPC = 185,//Bank 24: 185-192
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PerfCnt0 = 193,//Bank 25: 193 - 200
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PerfCnt1 = 194,
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PerfCnt2 = 195,
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PerfCnt3 = 196,
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PerfCnt4 = 197,
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PerfCnt5 = 198,
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PerfCnt6 = 199,
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PerfCnt7 = 200,
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ErrCtl = 201, //Bank 26: 201 - 208
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CacheErr0 = 209, //Bank 27: 209 - 216
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CacheErr1 = 210,
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CacheErr2 = 211,
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CacheErr3 = 212,
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TagLo0 = 217,//Bank 28: 217 - 224
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DataLo1 = 218,
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TagLo2 = 219,
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DataLo3 = 220,
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TagLo4 = 221,
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DataLo5 = 222,
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TagLo6 = 223,
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DataLo7 = 234,
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TagHi0 = 233,//Bank 29: 233 - 240
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DataHi1 = 234,
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TagHi2 = 235,
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DataHi3 = 236,
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TagHi4 = 237,
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DataHi5 = 238,
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TagHi6 = 239,
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DataHi7 = 240,
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ErrorEPC = 249,//Bank 30: 241 - 248
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DESAVE = 257,//Bank 31: 249-256
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//More Misc. Regs
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Hi,
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Lo,
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FCSR,
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FPCR,
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//Alpha Regs, but here now, for
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//compiling sake
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UNIQ,
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LockAddr,
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LockFlag
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};
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extern const Addr PageShift;
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extern const Addr PageBytes;
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extern const Addr PageMask;
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extern const Addr PageOffset;
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#if FULL_SYSTEM
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typedef uint64_t InternalProcReg;
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#include "arch/mips/isa_fullsys_traits.hh"
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#else
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enum {
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NumInternalProcRegs = 0
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};
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#endif
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typedef union {
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IntReg intreg;
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FloatReg fpreg;
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MiscReg ctrlreg;
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} AnyReg;
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struct RegFile {
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IntRegFile intRegFile; // (signed) integer register file
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FloatRegFile floatRegFile; // floating point register file
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MiscRegFile miscRegs; // control register file
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Addr pc; // program counter
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Addr npc; // next-cycle program counter
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Addr nnpc; // next-next-cycle program counter
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// used to implement branch delay slot
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// not real register
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MiscReg hi; // MIPS HI Register
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MiscReg lo; // MIPS LO Register
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#if FULL_SYSTEM
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IntReg palregs[NumIntRegs]; // PAL shadow registers
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InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
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int intrflag; // interrupt flag
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bool pal_shadow; // using pal_shadow registers
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inline int instAsid() { return MIPS34K::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); }
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inline int dataAsid() { return MIPS34K::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); }
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#endif // FULL_SYSTEM
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//void initCP0Regs();
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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void createCP0Regs();
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void coldReset();
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};
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StaticInstPtr decodeInst(ExtMachInst);
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// return a no-op instruction... used for instruction fetch faults
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extern const MachInst NoopMachInst;
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enum annotes {
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ANNOTE_NONE = 0,
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// An impossible number for instruction annotations
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ITOUCH_ANNOTE = 0xffffffff,
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};
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//void getMiscRegIdx(int reg_name,int &idx, int &sel);
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static inline ExtMachInst
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makeExtMI(MachInst inst, const uint64_t &pc) {
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#if FULL_SYSTEM
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ExtMachInst ext_inst = inst;
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if (pc && 0x1)
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return ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32);
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else
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return ext_inst;
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#else
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return ExtMachInst(inst);
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#endif
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}
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static inline bool isCallerSaveIntegerRegister(unsigned int reg) {
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panic("register classification not implemented");
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return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
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}
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static inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
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panic("register classification not implemented");
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return (reg >= 9 && reg <= 15);
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}
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static inline bool isCallerSaveFloatRegister(unsigned int reg) {
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panic("register classification not implemented");
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return false;
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}
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static inline bool isCalleeSaveFloatRegister(unsigned int reg) {
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panic("register classification not implemented");
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return false;
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}
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static inline Addr alignAddress(const Addr &addr,
|
||
unsigned int nbytes) {
|
||
return (addr & ~(nbytes - 1));
|
||
}
|
||
|
||
// Instruction address compression hooks
|
||
static inline Addr realPCToFetchPC(const Addr &addr) {
|
||
return addr;
|
||
}
|
||
|
||
static inline Addr fetchPCToRealPC(const Addr &addr) {
|
||
return addr;
|
||
}
|
||
|
||
// the size of "fetched" instructions (not necessarily the size
|
||
// of real instructions for PISA)
|
||
static inline size_t fetchInstSize() {
|
||
return sizeof(MachInst);
|
||
}
|
||
|
||
static inline MachInst makeRegisterCopy(int dest, int src) {
|
||
panic("makeRegisterCopy not implemented");
|
||
return 0;
|
||
}
|
||
|
||
static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs)
|
||
{
|
||
regs->intRegFile[ReturnValueReg1] = 1;
|
||
//panic("Returning from syscall\n");
|
||
}
|
||
|
||
// Machine operations
|
||
|
||
void saveMachineReg(AnyReg &savereg, const RegFile ®_file,
|
||
int regnum);
|
||
|
||
void restoreMachineReg(RegFile ®s, const AnyReg ®,
|
||
int regnum);
|
||
|
||
#if 0
|
||
static void serializeSpecialRegs(const Serializable::Proxy &proxy,
|
||
const RegFile ®s);
|
||
|
||
static void unserializeSpecialRegs(const IniFile *db,
|
||
const std::string &category,
|
||
ConfigNode *node,
|
||
RegFile ®s);
|
||
#endif
|
||
|
||
/**
|
||
* Function to insure ISA semantics about 0 registers.
|
||
* @param xc The execution context.
|
||
*/
|
||
template <class XC>
|
||
void zeroRegisters(XC *xc);
|
||
|
||
const Addr MaxAddr = (Addr)-1;
|
||
};
|
||
|
||
#if FULL_SYSTEM
|
||
//typedef TheISA::InternalProcReg InternalProcReg;
|
||
//const int NumInternalProcRegs = TheISA::NumInternalProcRegs;
|
||
//const int NumInterruptLevels = TheISA::NumInterruptLevels;
|
||
|
||
#include "arch/mips/mips34k.hh"
|
||
#endif
|
||
|
||
using namespace MipsISA;
|
||
|
||
#endif // __ARCH_MIPS_ISA_TRAITS_HH__
|