Commit graph

234 commits

Author SHA1 Message Date
Steve Reinhardt
96737c8a9b Rename 'Machine' to 'SysConfig'.
Clean up a little.

--HG--
extra : convert_revision : db5f36776209c76a593205c46b08aa147358f33a
2006-10-17 11:08:49 -07:00
Kevin Lim
e5b13138b1 Two minor fixes.
configs/common/SysPaths.py:
    Undo accidental change.
src/SConscript:
    Fix.

--HG--
extra : convert_revision : 665b186cff7d8ae560601ced7ae407a41a16cfea
2006-10-10 01:49:46 -04:00
Kevin Lim
bdde892d66 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem

src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/cpu/simple/timing.hh:
tests/configs/o3-timing-mp.py:
    Hand merge.

--HG--
extra : convert_revision : a58cc439eb5e8f900d175ed8b5a85b6c8723e558
2006-10-09 22:59:56 -04:00
Lisa Hsu
67a114fc29 add in checkpoint restoration option, you can restore a checkpoint by giving a directory, and then giving a checkpoint number, the earliest checkpoint is 1, the latest is N. the default checkpoint directory is the cwd.
so you can restore by a command line like this:

m5.opt fs.py --checkpoint_dir="/my/ckpt/dir" -c 3

configs/example/fs.py:
    add in checkpoint restoration option, you can restore a checkpoint by giving a directory, and then giving a checkpoint number, the earliest checkpoint is 1, the latest is N.

--HG--
extra : convert_revision : bf9c8d3265a3875cdfb6a878005baa7ae29af90d
2006-10-09 00:12:16 -04:00
Steve Reinhardt
91c76278b9 Set cpu_id params (required by ll/sc code now).
--HG--
extra : convert_revision : e0f7ccbeccca191a8edb54494d2b4f9369e9914c
2006-10-08 19:11:06 -07:00
Kevin Lim
8949d813ff Clean up configs.
configs/common/FSConfig.py:
configs/common/SysPaths.py:
configs/example/fs.py:
configs/example/se.py:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
    Clean up configs by removing FullO3Config and instead using default values.
src/python/m5/objects/FUPool.py:
    Add in default FUPool.
src/python/m5/objects/O3CPU.py:
    Use defaults better.  Also set checker parameters, and fix up a config bug.

--HG--
extra : convert_revision : 5fd0c000143f4881f10a9a575c3810dc97cb290b
2006-10-08 01:12:42 -04:00
Lisa Hsu
54cf456fd1 add an option for defining a directory in which to place all your checkpoints. if none, default is cwd.
--HG--
extra : convert_revision : 23a602c2d800c922346c9743cc0c583d178a0ee7
2006-10-06 00:42:39 -04:00
Lisa Hsu
868d112578 fix the argument to m5.simulate() on a checkpoint.
src/sim/stat_control.cc:
    add curTick to reset stats printf.

--HG--
extra : convert_revision : da8cf5921e81b73f47d6831d539ca1fbdace3d1d
2006-10-05 13:18:32 -04:00
Kevin Lim
4ed184eade Merge ktlim@zamp:./local/clean/o3-merge/m5
into  zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem

configs/boot/micro_memlat.rcS:
configs/boot/micro_tlblat.rcS:
src/arch/alpha/ev5.cc:
src/arch/alpha/isa/decoder.isa:
src/arch/alpha/isa_traits.hh:
src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/base_dyn_inst.hh:
src/cpu/checker/cpu.hh:
src/cpu/checker/cpu_impl.hh:
src/cpu/o3/alpha/cpu_impl.hh:
src/cpu/o3/alpha/params.hh:
src/cpu/o3/checker_builder.cc:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/lsq_unit_impl.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/checker_builder.cc:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_back_end.hh:
src/cpu/ozone/lw_back_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/simple/base.cc:
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
src/cpu/thread_state.hh:
src/dev/ide_disk.cc:
src/python/m5/objects/O3CPU.py:
src/python/m5/objects/Root.py:
src/python/m5/objects/System.py:
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
src/sim/system.hh:
util/m5/m5.c:
    Hand merge.

--HG--
rename : arch/alpha/ev5.cc => src/arch/alpha/ev5.cc
rename : arch/alpha/freebsd/system.cc => src/arch/alpha/freebsd/system.cc
rename : arch/alpha/isa/decoder.isa => src/arch/alpha/isa/decoder.isa
rename : arch/alpha/isa/mem.isa => src/arch/alpha/isa/mem.isa
rename : arch/alpha/isa_traits.hh => src/arch/alpha/isa_traits.hh
rename : arch/alpha/linux/system.cc => src/arch/alpha/linux/system.cc
rename : arch/alpha/system.cc => src/arch/alpha/system.cc
rename : arch/alpha/tru64/system.cc => src/arch/alpha/tru64/system.cc
rename : cpu/base.cc => src/cpu/base.cc
rename : cpu/base.hh => src/cpu/base.hh
rename : cpu/base_dyn_inst.hh => src/cpu/base_dyn_inst.hh
rename : cpu/checker/cpu.hh => src/cpu/checker/cpu.hh
rename : cpu/checker/cpu.cc => src/cpu/checker/cpu_impl.hh
rename : cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc
rename : cpu/checker/o3_cpu_builder.cc => src/cpu/o3/checker_builder.cc
rename : cpu/o3/commit_impl.hh => src/cpu/o3/commit_impl.hh
rename : cpu/o3/cpu.cc => src/cpu/o3/cpu.cc
rename : cpu/o3/fetch_impl.hh => src/cpu/o3/fetch_impl.hh
rename : cpu/o3/iew.hh => src/cpu/o3/iew.hh
rename : cpu/o3/iew_impl.hh => src/cpu/o3/iew_impl.hh
rename : cpu/o3/inst_queue.hh => src/cpu/o3/inst_queue.hh
rename : cpu/o3/inst_queue_impl.hh => src/cpu/o3/inst_queue_impl.hh
rename : cpu/o3/lsq_impl.hh => src/cpu/o3/lsq_impl.hh
rename : cpu/o3/lsq_unit.hh => src/cpu/o3/lsq_unit.hh
rename : cpu/o3/lsq_unit_impl.hh => src/cpu/o3/lsq_unit_impl.hh
rename : cpu/o3/mem_dep_unit_impl.hh => src/cpu/o3/mem_dep_unit_impl.hh
rename : cpu/o3/rename.hh => src/cpu/o3/rename.hh
rename : cpu/o3/rename_impl.hh => src/cpu/o3/rename_impl.hh
rename : cpu/o3/thread_state.hh => src/cpu/o3/thread_state.hh
rename : cpu/o3/tournament_pred.cc => src/cpu/o3/tournament_pred.cc
rename : cpu/o3/tournament_pred.hh => src/cpu/o3/tournament_pred.hh
rename : cpu/checker/cpu_builder.cc => src/cpu/ozone/checker_builder.cc
rename : cpu/ozone/cpu.hh => src/cpu/ozone/cpu.hh
rename : cpu/ozone/cpu_builder.cc => src/cpu/ozone/cpu_builder.cc
rename : cpu/ozone/cpu_impl.hh => src/cpu/ozone/cpu_impl.hh
rename : cpu/ozone/front_end.hh => src/cpu/ozone/front_end.hh
rename : cpu/ozone/front_end_impl.hh => src/cpu/ozone/front_end_impl.hh
rename : cpu/ozone/inorder_back_end_impl.hh => src/cpu/ozone/inorder_back_end_impl.hh
rename : cpu/ozone/inst_queue_impl.hh => src/cpu/ozone/inst_queue_impl.hh
rename : cpu/ozone/lw_back_end.hh => src/cpu/ozone/lw_back_end.hh
rename : cpu/ozone/lw_back_end_impl.hh => src/cpu/ozone/lw_back_end_impl.hh
rename : cpu/ozone/lw_lsq.hh => src/cpu/ozone/lw_lsq.hh
rename : cpu/ozone/lw_lsq_impl.hh => src/cpu/ozone/lw_lsq_impl.hh
rename : cpu/ozone/simple_params.hh => src/cpu/ozone/simple_params.hh
rename : cpu/ozone/thread_state.hh => src/cpu/ozone/thread_state.hh
rename : cpu/simple/cpu.cc => src/cpu/simple/base.cc
rename : cpu/cpu_exec_context.cc => src/cpu/simple_thread.cc
rename : cpu/thread_state.hh => src/cpu/thread_state.hh
rename : dev/ide_disk.hh => src/dev/ide_disk.hh
rename : python/m5/objects/BaseCPU.py => src/python/m5/objects/BaseCPU.py
rename : python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/O3CPU.py
rename : python/m5/objects/OzoneCPU.py => src/python/m5/objects/OzoneCPU.py
rename : python/m5/objects/Root.py => src/python/m5/objects/Root.py
rename : python/m5/objects/System.py => src/python/m5/objects/System.py
rename : sim/eventq.hh => src/sim/eventq.hh
rename : sim/pseudo_inst.cc => src/sim/pseudo_inst.cc
rename : sim/pseudo_inst.hh => src/sim/pseudo_inst.hh
rename : sim/serialize.cc => src/sim/serialize.cc
rename : sim/stat_control.cc => src/sim/stat_control.cc
rename : sim/stat_control.hh => src/sim/stat_control.hh
rename : sim/system.hh => src/sim/system.hh
extra : convert_revision : 135d90e43f6cea89f9460ba4e23f4b0b85886e7d
2006-09-30 23:43:23 -04:00
Ali Saidi
44c6f953b0 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem.head

--HG--
extra : convert_revision : 14ac24236ff65b7e489c1ce4b4e9a295966013b8
2006-09-11 17:57:30 -04:00
Ali Saidi
46502851ab add annotation code to m5
configs/common/Benchmarks.py:
    add annotate test app
src/SConscript:
    add annotate.cc to lis
src/arch/alpha/isa/decoder.isa:
    add annotate instructions
src/base/traceflags.py:
    Add annotate trace flag
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
    add annotate pseudo ops
util/m5/m5op.S:
util/m5/m5op.h:
    add anotate ops

--HG--
extra : convert_revision : 7f965c0d84e41ce34f2ec8ec27a009276d67d8d6
2006-09-11 17:57:20 -04:00
Steve Reinhardt
545cbec5f7 Enable proxies (Self/Parent) for specifying ports.
Significant revamp of Port code.
Some cleanup of SimObject code too, particularly to
make the SimObject and MetaSimObject implementations of
__setattr__ more consistent.
Unproxy code split out of print_ini().

src/python/m5/multidict.py:
    Make get() return None by default, to match semantics
    of built-in dictionary objects.

--HG--
extra : convert_revision : db73b6cdd004a82a08b2402afd1e16544cb902a4
2006-09-05 22:04:34 -07:00
Steve Reinhardt
8bc3c2b192 Add FULL_SYSTEM check to example/fs.py.
--HG--
extra : convert_revision : 4cab46e73f29d2c9d24d9c0c847d598bf6d5c389
2006-08-29 14:36:35 -07:00
Steve Reinhardt
b0bf1e84e4 Add missing cpu mem param to example/se.py.
configs/example/se.py:
    Add missing cpu mem param.

--HG--
extra : convert_revision : 29a11b09524612f079b8998e99b8f5ee8c67c8a6
2006-08-29 14:14:29 -07:00
Kevin Lim
65741cd048 Updates to configs to support various sampling forms, truncated execution forms.
--HG--
extra : convert_revision : a6cf77f6c902e5f4f0a96206093d123eec2e0167
2006-08-24 18:01:07 -04:00
Steve Reinhardt
21b21c63b0 fs.py:
Add temporary cpu.mem parameter settings.

configs/example/fs.py:
    Add temporary cpu.mem parameter settings.

--HG--
extra : convert_revision : d7c2fcd8df8dc809b0511485877b2a85769aaf43
2006-08-21 12:31:59 -04:00
Steve Reinhardt
b83d0e5544 configs/example/fs.py:
Arg to m5.simulate() is a delta, not an absolute curTick value.
I didn't test this change, but I'm not convinced the previous
example was tested either, so I don't feel too badly about it.

configs/example/fs.py:
    Arg to m5.simulate() is a delta, not an absolute curTick value.
    I didn't test this change, but I'm not convinced the previous
    example was tested either, so I don't feel too badly about it.

--HG--
extra : convert_revision : ef7df7b83b3e2b5da02408c674169ccbed75a441
2006-08-20 19:28:58 -07:00
Lisa Hsu
a99534d429 Merge zizzer:/bk/newmem
into  zed.eecs.umich.edu:/z/hsul/work/m5/newmem

--HG--
extra : convert_revision : 382a9d4b420a9bdb35f93049306b7b7af0d33ad5
2006-08-17 00:02:38 -04:00
Lisa Hsu
a88a6758ce make tree rcS files reflect what we've been actually using in /dist.
also, update all the rcS files so that they are in sync with the new linux-dist build system.

configs/boot/devtime.rcS:
configs/boot/iscsi-client.rcS:
configs/boot/iscsi-server.rcS:
configs/boot/micro_memlat.rcS:
configs/boot/micro_stream.rcS:
configs/boot/micro_tlblat.rcS:
configs/boot/nat-netperf-maerts-client.rcS:
configs/boot/nat-netperf-server.rcS:
configs/boot/nat-netperf-stream-client.rcS:
configs/boot/nat-spec-surge-client.rcS:
configs/boot/nat-spec-surge-server.rcS:
configs/boot/natbox-netperf.rcS:
configs/boot/natbox-spec-surge.rcS:
configs/boot/netperf-rr.rcS:
configs/boot/netperf-server.rcS:
configs/boot/netperf-stream-client.rcS:
configs/boot/netperf-stream-nt-client.rcS:
configs/boot/nfs-client-nhfsstone.rcS:
configs/boot/nfs-client-tcp-smallb.rcS:
configs/boot/nfs-client-tcp.rcS:
configs/boot/nfs-client.rcS:
configs/boot/nfs-server-nhfsstone.rcS:
configs/boot/nfs-server.rcS:
configs/boot/ping-client.rcS:
configs/boot/ping-server.rcS:
configs/boot/spec-surge-client.rcS:
configs/boot/spec-surge-server.rcS:
configs/boot/surge-client.rcS:
configs/boot/surge-server.rcS:
    make tree rcS files reflect what we've been actually using in /dist.

--HG--
extra : convert_revision : 48fe4fe71938ef9d029e428028a271242c8d2faa
2006-08-17 00:00:27 -04:00
Ali Saidi
76ab1c466c add etherdump file option
--HG--
extra : convert_revision : 6b62398778208bc4e64582e06fb73b71a94f3014
2006-08-16 22:17:23 -04:00
Lisa Hsu
c475fd5211 Add in checkpointing in the frontend, so that when a checkpoint is called, the python handles it, and the simulation continues. Also, make it so that the cycle number is part of the cpt dir name, so that multiple checkpoints do not overwrite each other.
--HG--
extra : convert_revision : a55e4ac20da5a57ea8735951b9070960b9b8298f
2006-08-16 17:54:00 -04:00
Steve Reinhardt
bd4ccd6e39 Finish test clean-up & reorg.
configs/common/FSConfig.py:
    Add default Machine() param
configs/example/fs.py:
configs/example/se.py:
    make it work again
src/python/m5/objects/BaseCPU.py:
    Make mem PhysicalMemory so that a Parent.any proxy works well
src/sim/process.cc:
    Increase default stack size so we don't get an
    'increasing stack' message on 'hello world'
tests/SConscript:
    Add full list of current configs.
tests/configs/simple-atomic.py:
tests/configs/simple-timing.py:
    don't need SEConfig anymore
tests/quick/00.hello/test.py:
tests/quick/20.eio-short/test.py:
    fix
tests/run.py:
    move configs to separate dir

--HG--
rename : configs/test/fs.py => configs/example/fs.py
rename : configs/test/test.py => configs/example/se.py
rename : tests/simple-atomic.py => tests/configs/simple-atomic.py
rename : tests/simple-timing.py => tests/configs/simple-timing.py
rename : tests/linux-mpboot/ref/alpha/atomic/config.ini => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
rename : tests/linux-mpboot/ref/alpha/atomic/config.out => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out
rename : tests/linux-mpboot/ref/alpha/atomic/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console
rename : tests/linux-mpboot/ref/alpha/atomic/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt
rename : tests/linux-mpboot/ref/alpha/atomic/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr
rename : tests/linux-mpboot/ref/alpha/atomic/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout
rename : tests/linux-boot/ref/alpha/atomic/config.ini => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
rename : tests/linux-boot/ref/alpha/atomic/config.out => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out
rename : tests/linux-boot/ref/alpha/atomic/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console
rename : tests/linux-boot/ref/alpha/atomic/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt
rename : tests/linux-boot/ref/alpha/atomic/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr
rename : tests/linux-boot/ref/alpha/atomic/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout
rename : tests/linux-mpboot/ref/alpha/timing/config.ini => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
rename : tests/linux-mpboot/ref/alpha/timing/config.out => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out
rename : tests/linux-mpboot/ref/alpha/timing/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console
rename : tests/linux-mpboot/ref/alpha/timing/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt
rename : tests/linux-mpboot/ref/alpha/timing/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr
rename : tests/linux-mpboot/ref/alpha/timing/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout
rename : tests/test-progs/hello/bin/mips/linux/hello_mips => tests/test-progs/hello/bin/mips/linux/hello
rename : tests/test-progs/hello/bin/sparc/bin => tests/test-progs/hello/bin/sparc/linux/hello
extra : convert_revision : d68ee6d7eefa7ba57370f3fb3c3589f86a6ea6b4
2006-08-16 14:42:44 -04:00
Steve Reinhardt
2552e68eb6 More restructuring of regression tests.
Moving work back to zizzer...

configs/common/FSConfig.py:
configs/test/fs.py:
    Move CPU connections out of makeLinuxAlphaSystem()
src/python/m5/objects/BaseCPU.py:
    Create default TLBs in full system.
    Move utility cache functions here.
src/python/m5/objects/O3CPU.py:
    Add _mem_ports
tests/run.py:
    Add binpath()
    Change maxtick default to 'forever'
tests/simple-atomic.py:
    Use connectmemPorts()
tests/simple-timing.py:
    Fix up.

--HG--
rename : tests/quick/eio1/ref/alpha/eio/detailed/config.ini => tests/quick/20.eio-short/ref/alpha/eio/detailed/config.ini
rename : tests/quick/eio1/ref/alpha/eio/detailed/config.out => tests/quick/20.eio-short/ref/alpha/eio/detailed/config.out
rename : tests/quick/eio1/ref/alpha/eio/detailed/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/detailed/m5stats.txt
rename : tests/quick/eio1/ref/alpha/eio/detailed/stderr => tests/quick/20.eio-short/ref/alpha/eio/detailed/stderr
rename : tests/quick/eio1/ref/alpha/eio/detailed/stdout => tests/quick/20.eio-short/ref/alpha/eio/detailed/stdout
rename : tests/quick/eio1/ref/alpha/eio/simple-atomic/config.ini => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
rename : tests/quick/eio1/ref/alpha/eio/simple-atomic/config.out => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out
rename : tests/quick/eio1/ref/alpha/eio/simple-atomic/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt
rename : tests/quick/eio1/ref/alpha/eio/simple-atomic/stderr => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stderr
rename : tests/quick/eio1/ref/alpha/eio/simple-atomic/stdout => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout
rename : tests/quick/eio1/ref/alpha/eio/simple-timing/config.ini => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
rename : tests/quick/eio1/ref/alpha/eio/simple-timing/config.out => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out
rename : tests/quick/eio1/ref/alpha/eio/simple-timing/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
rename : tests/quick/eio1/ref/alpha/eio/simple-timing/stderr => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr
rename : tests/quick/eio1/ref/alpha/eio/simple-timing/stdout => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
rename : tests/quick/eio1/test.py => tests/quick/20.eio-short/test.py
rename : configs/test/hello => tests/test-progs/hello/bin/alpha/linux/hello
rename : configs/test/hello_mips => tests/test-progs/hello/bin/mips/linux/hello_mips
rename : configs/test/sparc_tests/hello_sparc => tests/test-progs/hello/bin/sparc/bin
extra : convert_revision : 1f891392ecc11ffcc3b3182fa673c401c0efc8a5
2006-08-16 09:52:05 -07:00
Ali Saidi
de29f555c4 implement benchmark selection code
--HG--
extra : convert_revision : 84632fdad7019e177e61c56ae30ea2f3fdbc0995
2006-08-15 19:12:19 -04:00
Kevin Lim
de321175f2 Add in a bunch more stuff.
configs/boot/micro_memlat.rcS:
    Update these scripts so they work (not sure why they broke)
configs/boot/micro_tlblat.rcS:
    Update this script to use a different test.

--HG--
extra : convert_revision : 6e8692540a9fac6ae8f2d9975c70d4135354b849
2006-08-11 17:48:41 -04:00
Kevin Lim
08c0919b43 Clean up some more config stuff.
configs/common/FSConfig.py:
    Clean up some code to make functions look less like classes.  Also put makeList function (formerly listWrapper) into m5 itself.
configs/test/fs.py:
    Update for changed code.
src/python/m5/__init__.py:
    Put makeList into m5.

--HG--
extra : convert_revision : 731806a7486f9abf986f52926126df666b024b1d
2006-07-27 17:49:00 -04:00
Kevin Lim
f9729e999f Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

--HG--
extra : convert_revision : 45650c90385b4e13e79ccf271a30bb55552b380f
2006-07-23 00:10:52 -04:00
Kevin Lim
6ef6e9b14d Fix up test.py
configs/test/test.py:
    Fix up this config.

--HG--
extra : convert_revision : e15071ee27b860cc3ad79277aa61f3e6bb7405d3
2006-07-23 00:10:11 -04:00
Gabe Black
c77cb31473 Reorganized SPARC binaries
--HG--
rename : configs/test/hello_sparc => configs/test/sparc_tests/hello_sparc
extra : convert_revision : d8f36fc9b346f0e89dc8406403576e88bb2dc139
2006-07-22 17:30:50 -04:00
Kevin Lim
7ccdb7accc Last minute check in. Very few functional changes other than some minor config updates. Also include some recently generated stats.
SConstruct:
    Make test CPUs option non-sticky.
configs/common/FSConfig.py:
    Be sure to set the memory mode.
configs/test/fs.py:
    Wrong string.
tests/SConscript:
    Only test valid CPUs that have been compiled in.
tests/test1/ref/alpha/atomic/config.ini:
tests/test1/ref/alpha/atomic/config.out:
tests/test1/ref/alpha/atomic/m5stats.txt:
tests/test1/ref/alpha/atomic/stdout:
tests/test1/ref/alpha/detailed/config.ini:
tests/test1/ref/alpha/detailed/config.out:
tests/test1/ref/alpha/detailed/m5stats.txt:
tests/test1/ref/alpha/detailed/stdout:
tests/test1/ref/alpha/timing/config.ini:
tests/test1/ref/alpha/timing/config.out:
tests/test1/ref/alpha/timing/m5stats.txt:
tests/test1/ref/alpha/timing/stdout:
    Update output.

--HG--
extra : convert_revision : 6eee2a5eae0291b5121b41bcd7021179cdd520a3
2006-07-22 15:50:39 -04:00
Kevin Lim
db5f710a7b Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

configs/test/fs.py:
    Hand merge.

--HG--
extra : convert_revision : 78f7c46084f66d52ddfe0386fd7c08de8017331e
2006-07-21 16:08:17 -04:00
Kevin Lim
a6c2e5cca0 Rearrange the FS configs to be more shared. Also check in the full-system tests. Reference stats coming soon.
configs/test/fs.py:
    Pull out a lot of common code and put it into configs/common/FSConfig.py.

--HG--
extra : convert_revision : 175b18d75f82ddecbcc9a6418fe40df314db55d5
2006-07-21 15:56:35 -04:00
Kevin Lim
bd33d8d4ac Some reorganization. Options are all handled at the user level script. Move createCpus function (now called connectCpu) to Util.py, where it can be used by other configs.
--HG--
rename : configs/test/SysPaths.py => configs/common/SysPaths.py
extra : convert_revision : 2b1b95c5f29e7ade08b1abd6f24c129d600fe2e8
2006-07-21 15:42:44 -04:00
Ali Saidi
e8a3295075 Enforce the timing cpu ticking at it's clock rate
Add a max time option in seconds and a single system root clock be 1THz

configs/test/fs.py:
    Add a max time option in seconds and a single system root clock be 1THz
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
    Enforce the timing cpu ticking at it's clock rate

--HG--
extra : convert_revision : a1b0de27abde867f9c3da5bec11639e3d82a95f5
2006-07-20 19:00:40 -04:00
Kevin Lim
1fdf14dd5a Update configs.
configs/test/test.py:
    Update for changes to SEConfig.

--HG--
extra : convert_revision : a089a7db4035889db01d543d9a18ea6526f832ca
2006-07-19 15:24:22 -04:00
Kevin Lim
31ac8e7337 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

configs/test/fs.py:
configs/test/test.py:
    SCCS merged

--HG--
extra : convert_revision : 7b2dbcd5881fac01dec38001c4131e73b5be52b5
2006-07-14 17:54:43 -04:00
Ali Saidi
c368ff0bd8 add system.mem_mode = ['timing', 'atomic']
update scripts acordingly

configs/test/SysPaths.py:
    new syspaths from nate, this one allows you to set script, binary, and disk paths like
    system.dir = 'aouaou' in your script
configs/test/fs.py:
    update for system mem_mode
    Put small checkpoint example
    Make clock 1THz
configs/test/test.py:
src/arch/alpha/freebsd/system.cc:
src/arch/alpha/linux/system.cc:
src/arch/alpha/system.cc:
src/arch/alpha/tru64/system.cc:
src/arch/sparc/system.cc:
src/python/m5/objects/System.py:
src/sim/system.cc:
src/sim/system.hh:
    update for system mem_mode
src/dev/io_device.cc:
    Use time returned from sendAtomic to delay

--HG--
extra : convert_revision : 67eedb3c84ab2584613faf88a534e793926fc92f
2006-07-13 15:48:17 -04:00
Kevin Lim
6dfaf06edf Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

configs/test/test.py:
    Hand merge.

--HG--
extra : convert_revision : e3fce9cf50a65a9400cd3ec887b13e4765274ec2
2006-07-12 17:21:25 -04:00
Kevin Lim
a9ca36639f Initial try of consolidating configuration files so they can be shared more easily, especially across regression tests and simple examples.
configs/test/fs.py:
    Pull a lot of the default options out of the config file now that they are in the Python objects themselves.  Also merge this file with the single_fs.py, allowing one file to be used for both.  Previously they differed only by the system they instantiated.
configs/test/test.py:
    Initial stab at consolidating configuration files so they aren't redundant between the regression tests and the simple examples.

--HG--
extra : convert_revision : e8ae3de5a6d8864831f21089d4fdb8ec690e4731
2006-07-12 17:17:17 -04:00
Nathan Binkert
55ea050d48 Migrate most of main() and and all option parsing to python
configs/test/fs.py:
configs/test/test.py:
    update for the new way that m5 deals with options
src/python/SConscript:
    Compile AUTHORS, LICENSE, README, and RELEASE_NOTES into the
    python stuff.
src/python/m5/__init__.py:
    redo the way options work.
    Move them all to main.py
src/sim/main.cc:
    Migrate more functionality for main() into python.
    Namely option parsing
src/python/m5/attrdict.py:
    A dictionary object that overrides attribute access to
    do item access.
src/python/m5/main.py:
    The new location for M5's option parsing, and the main()
    routine to set up the simulation.

--HG--
extra : convert_revision : c86b87a9f508bde1994088e23fd470c7753ee4c1
2006-07-10 23:00:13 -04:00
Ron Dreslinski
aef232a942 Update FS configs to use cpu connectors for ports
--HG--
extra : convert_revision : 1e2e503401f92c1f30e2e487d7aeed1c7c5b7ee4
2006-07-10 12:07:21 -04:00
Ron Dreslinski
ea11c7bdbe Update cpus to use the getPort function to use a connector object to connect the I/D cache ports to memory
configs/test/test.py:
    Update to use new cpu getPort functionality
src/cpu/base.cc:
    Make cpu's a memObject to expose getPort interface
src/cpu/base.hh:
    Make cpu's a memObject to export getPort interface
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
    Now use the connector via getPort interface
src/mem/cache/base_cache.cc:
    Make sure the cache recognizes all port names

--HG--
extra : convert_revision : dbfefa978ec755bc8aa6f962ae158acf32dafe61
2006-07-07 15:15:11 -04:00
Ali Saidi
93839380e7 Add default responder to bus
Update configuration for new default responder on bus
Update to devices to handle their own pci config space without pciconfigall
Remove most of pciconfigall, it now is a dumbdevice which gets it's address based on the bus it's supposed to respond for
Remove need for pci config space from platform, add registerPciDevice function to prevent more than one device from having same
bus:dev:func and interrupt
Remove pciconfigspace from pci devices, and py files
Add calcConfigAddr that returns address for config space based on bus/dev/function + offset

configs/test/fs.py:
    Update configuration for new default responder on bus
src/dev/ide_ctrl.cc:
src/dev/ide_ctrl.hh:
src/dev/ns_gige.cc:
src/dev/ns_gige.hh:
src/dev/pcidev.cc:
src/dev/pcidev.hh:
    Update to handle it's own pci config space without pciconfigall
src/dev/io_device.cc:
src/dev/io_device.hh:
    change naming for pio port
    break out recvTiming into two functions to reuse code
src/dev/pciconfigall.cc:
src/dev/pciconfigall.hh:
    removing most of pciconfigall, it now is a dumbdevice which gets it's address based on the bus it's supposed to respond for
src/dev/pcireg.h:
    add a max size for PCI config space (per PCI spec)
src/dev/platform.cc:
src/dev/platform.hh:
    remove need for pci config space from platform, add registerPciDevice function to prevent more than one device from having same
    bus:dev:func and interrupt
src/dev/sinic.cc:
    remove pciconfigspace as it's no longer a needed parameter
src/dev/tsunami.cc:
src/dev/tsunami.hh:
src/dev/tsunami_pchip.cc:
src/dev/tsunami_pchip.hh:
    add calcConfigAddr that returns address for config space based on bus/dev/function + offset (per PCI spec)
src/mem/bus.cc:
src/mem/bus.hh:
src/python/m5/objects/Bus.py:
    add idea of default responder to bus
src/python/m5/objects/Pci.py:
    add config port for pci devices
    add latency, bus and size parameters for pci config all (min is 8MB, max is 256MB see pci spec)

--HG--
extra : convert_revision : 99db43b0a3a077f86611d6eaff6664a3885da7c9
2006-07-06 14:41:01 -04:00
Korey Sewell
19083bc4ce Added hook to check for SMT workloads. SMT is identified by adding a semicolon between
the workloads.

Now SMT on the O3CPU can be invoked by "/ALPHA_SE/m5.debug ../configs/test/test.py -d --cmd="hello;hello" -i="file1;file2"

I think I am a novice python magician now!!!!....

configs/test/test.py:
    Added hook to check for SMT workloads. SMT is identified by adding a semicolon between
    the workloads.

    Now SMT on the O3CPU can be invoked by "/ALPHA_SE/m5.debug ../configs/test/test.py -d --cmd="hello;hello" --input="file1;file2"
    (btw, We are back to working for this double hello world case)

    I am a novice python magician now!!!!....

--HG--
extra : convert_revision : b55e10dce33f5a9dc4c78f90409ec0912bad4292
2006-07-03 01:10:19 -04:00
Ali Saidi
88c9b17cb9 Add help strings for options
--HG--
extra : convert_revision : ebbafaf00c56a4d2ee65eea08a12d276f279135d
2006-06-27 14:58:46 -04:00
Ali Saidi
a23f15641e Merge zizzer:/bk/newmem
into  zeep.eecs.umich.edu:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : 39c99c8acadd43f3ec42ae7550289a5075d910e4
2006-06-26 17:50:58 -04:00
Ali Saidi
d80acd37bd add python options for input file and command line options for live process
--HG--
extra : convert_revision : 3db1e6d29846812378aa5174179a0686f0141580
2006-06-26 16:50:19 -04:00
Korey Sewell
ca25e70907 use 'tick' instead of 'cycle'
--HG--
extra : convert_revision : e7119d20ef95deab16081743c885979b0fa85548
2006-06-18 15:58:14 -04:00
Ali Saidi
69c34554e5 minor device fixups
configs/test/SysPaths.py:
    remove some tabs and add /n/poolfs/z/dist/m5/system
src/dev/io_device.cc:
    fix since pio timing dma packts colud be nacked too
src/dev/io_device.hh:
    move DmaReqState into DmaDevie

--HG--
extra : convert_revision : 2b5300d85ab33b3753afc54bc6a04a47b6e00d20
2006-06-18 11:10:08 -04:00
Nathan Binkert
78ea17ea30 Make the system paths more configurable
configs/test/SysPaths.py:
    Make the paths more configurable

--HG--
extra : convert_revision : c426b102dfe55e4b601a23e980e1b01140e0ee93
2006-06-17 18:14:16 -04:00
Steve Reinhardt
4a9c0a7dfc Add --outdir option. Didn't call it "-d" since
that's already being used for "detailed cpu".
Needed to add extra function for user script
to pass parsed options back to m5 module.

configs/test/fs.py:
configs/test/test.py:
    Call setStandardOptions().
src/python/m5/__init__.py:
    Add --outdir option.
    Add setStandardOptions() so user script can
    pass parsed options back to m5 module.
src/sim/main.cc:
    Add SWIG-wrappable function to set output dir.

--HG--
extra : convert_revision : 1323bee69ca920c699a1cd1218e15b7b0875c1e5
2006-06-17 09:58:10 -04:00
Kevin Lim
aa1efe3e72 Update this with the same option as single_fs.py
--HG--
extra : convert_revision : 778d654f515b6af7c45165b0a9bc5ef0d60f0d19
2006-06-16 18:04:34 -04:00
Kevin Lim
4e07f6ca52 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

--HG--
extra : convert_revision : 488b9a9965dd86ca73dc9e510e5b3122cbd357f9
2006-06-16 17:53:33 -04:00
Kevin Lim
baba18ab92 Two updates that got combined into one ChangeSet accidentally. They're both pretty simple so they shouldn't cause any trouble.
First: Rename FullCPU and its variants in the o3 directory to O3CPU to differentiate from the old model, and also to specify it's an out of order model.

Second: Include build options for selecting the Checker to be used.  These options make sure if the Checker is being used there is a CPU that supports it also being compiled.

SConstruct:
    Add in option USE_CHECKER to allow for not compiling in checker code.  The checker is enabled through this option instead of through the CPU_MODELS list.  However it's still necessary to treat the Checker like a CPU model, so it is appended onto the CPU_MODELS list if enabled.
configs/test/test.py:
    Name change for DetailedCPU to DetailedO3CPU.  Also include option for max tick.
src/base/traceflags.py:
    Add in O3CPU trace flag.
src/cpu/SConscript:
    Rename AlphaFullCPU to AlphaO3CPU.

    Only include checker sources if they're necessary.  Also add a list of CPUs that support the Checker, and only allow the Checker to be compiled in if one of those CPUs are also being included.
src/cpu/base_dyn_inst.cc:
src/cpu/base_dyn_inst.hh:
    Rename typedef to ImplCPU instead of FullCPU, to differentiate from the old FullCPU.
src/cpu/cpu_models.py:
src/cpu/o3/alpha_cpu.cc:
src/cpu/o3/alpha_cpu.hh:
src/cpu/o3/alpha_cpu_builder.cc:
src/cpu/o3/alpha_cpu_impl.hh:
    Rename AlphaFullCPU to AlphaO3CPU to differentiate from old FullCPU model.
src/cpu/o3/alpha_dyn_inst.hh:
src/cpu/o3/alpha_dyn_inst_impl.hh:
src/cpu/o3/alpha_impl.hh:
src/cpu/o3/alpha_params.hh:
src/cpu/o3/commit.hh:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/rename.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/rob.hh:
src/cpu/o3/rob_impl.hh:
src/cpu/o3/thread_state.hh:
src/python/m5/objects/AlphaO3CPU.py:
    Rename FullCPU to O3CPU to differentiate from old FullCPU model.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_unit_impl.hh:
    Rename FullCPU to O3CPU to differentiate from old FullCPU model.
    Also #ifdef the checker code so it doesn't need to be included if it's not selected.

--HG--
rename : src/cpu/checker/o3_cpu_builder.cc => src/cpu/checker/o3_builder.cc
rename : src/cpu/checker/cpu_builder.cc => src/cpu/checker/ozone_builder.cc
rename : src/python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/AlphaO3CPU.py
extra : convert_revision : 86619baf257b8b7c8955efd447eba56e0d7acd6a
2006-06-16 17:08:47 -04:00
Steve Reinhardt
f06d508af0 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/z/stever/bk/newmem-head

--HG--
extra : convert_revision : 8a1cd7ff43aa4ebbfce0ff174d2f4ba3f095dd47
2006-06-15 11:46:13 -04:00
Steve Reinhardt
88e22ee081 Get Port stuff working with full-system scripts.
Key was adding support for cloning port references (trickier than it sounds).
Got rid of class/instance thing and go back to instance cloning...
still don't allow changing SimObject parameters/children after a
class (instance) has been subclassed or instantiated (or cloned), which
should avoid bizarre unintended behavior.

configs/test/fs.py:
    Add ".port" to busses to get a port reference.
    Get rid of commented-out code.
src/python/m5/__init__.py:
    resolveSimObject should call getCCObject() instead of createCCObject()
    to avoid cycles in recursively creating objects.
src/python/m5/config.py:
    Get rid of class/instance thing and go back to instance cloning.
    Deep copy has to happen only on instance cloning then (and not on subclassing).
    Add getCCObject() method to force creation of C++ SimObject without
    recursively creating its children.
    Add support for cloning port references (trickier than it sounds).
    Also clean up some very obsolete comments.
src/python/m5/objects/Bridge.py:
src/python/m5/objects/Device.py:
    Add ports.

--HG--
extra : convert_revision : 4816d05ead0de520748aace06dbd1911a33f0af8
2006-06-15 11:45:51 -04:00
Korey Sewell
1c55389578 tried to undo change and it didnt work so might as well put it back
--HG--
extra : convert_revision : 9793917e8a3e4d30f59ff469e4f08da96ce001f9
2006-06-14 22:01:36 -04:00
Korey Sewell
7b44630b95 change back, BK is acting up
--HG--
extra : convert_revision : 11fd5ebbca0408b357e9186d1b3722eb571e874e
2006-06-14 19:53:36 -04:00
Korey Sewell
7cd362ca4e add cycle to exit message
src/arch/mips/isa/formats/trap.isa:
    Take out fix that tried to fix trap
    instruction disassembly. It forces bad
    compile ..
configs/test/test.py:
    add 'cycle' to exit message

--HG--
extra : convert_revision : 568877797fd2806416b4cbb388cc3f7eb2492627
2006-06-14 19:45:15 -04:00
Steve Reinhardt
e981a97dec Move SimObject creation and Port connection loops
into Python.
Add Port and VectorPort objects and support for
specifying port connections via assignment.
The whole C++ ConfigNode hierarchy is gone now, as are
C++ Connector objects.

configs/test/fs.py:
configs/test/test.py:
    Rewrite for new port connector syntax.
src/SConscript:
    Remove unneeded files:
    - mem/connector.*
    - sim/config*
src/dev/io_device.hh:
src/mem/bridge.cc:
src/mem/bridge.hh:
src/mem/bus.cc:
src/mem/bus.hh:
src/mem/mem_object.hh:
src/mem/physical.cc:
src/mem/physical.hh:
    Allow getPort() to take an optional index to
    support vector ports (eventually).
src/python/m5/__init__.py:
    Move SimObject construction and port connection
    operations into Python (with C++ calls).
src/python/m5/config.py:
    Move SimObject construction and port connection
    operations into Python (with C++ calls).
    Add support for declaring and connecting MemObject
    ports in Python.
src/python/m5/objects/Bus.py:
src/python/m5/objects/PhysicalMemory.py:
    Add port declaration.
src/sim/builder.cc:
src/sim/builder.hh:
src/sim/serialize.cc:
src/sim/serialize.hh:
    ConfigNodes are gone; builder just gets the
    name of a .ini file section now.
src/sim/main.cc:
    Move SimObject construction and port connection
    operations into Python (with C++ calls).
    Split remaining initialization operations into two parts,
    loadIniFile() and finalInit().
src/sim/param.cc:
src/sim/param.hh:
    SimObject resolution done globally in Python now
    (not via ConfigNode hierarchy).
src/sim/sim_object.cc:
    Remove unneeded #include.

--HG--
extra : convert_revision : 2fa4001eaaec0c9a4231ef6e854f8e156d930dfe
2006-06-13 23:19:28 -04:00
Kevin Lim
72e4b98b8d Add in DetailedCPU to test.
--HG--
extra : convert_revision : 98c67b45af239e1cf5bad6888da6577a4c3bb45d
2006-06-13 14:15:24 -04:00
Steve Reinhardt
e0140202bd Move LiveProcess::create() from arch-specific files
bcak to main LiveProcess, then automatically select
ISA based on object file type.  Now simulation scripts
no longer need to care about the ISA, as they can just
call LiveProcess().

configs/test/test.py:
    Script no longer cares about ISA.
src/arch/alpha/process.cc:
src/arch/alpha/process.hh:
src/arch/mips/process.cc:
src/arch/mips/process.hh:
src/arch/sparc/process.cc:
src/arch/sparc/process.hh:
src/sim/process.cc:
src/sim/process.hh:
    Move create() from arch-specific files back to
    main LiveProcess, then automatically select ISA
    based on object file type.

--HG--
extra : convert_revision : ef33ffdc79623b77000f5d68edd2026760b76ab6
2006-06-11 21:49:46 -04:00
Steve Reinhardt
bb58e4b851 Don't allow SimObject-valued class params to be set
after the class has been instantiated or subclassed.
This is one of the main situations that leads to
confusing results.

configs/test/fs.py:
    Clean up to avoid modifying BaseCPU after it's been subclassed.

--HG--
extra : convert_revision : 335cb87bc3b211ecc8969cfb99ffc28f62f1f877
2006-06-10 21:13:36 -04:00
Steve Reinhardt
cd65504739 Update scripts for testing ALPHA_FS and MIPS_SE.
Minor fixes to ALPHA_FS and SPARC_SE.
SPARC_SE still does not compile... looks like there
are unresolved issues with ExecContext -> ThreadContext
rename/reorg.

configs/test/fs.py:
    Port to new script interface/model.
configs/test/test.py:
    Add support for running MIPS test(s) too via
    command-line option.
src/arch/alpha/ev5.cc:
    Fix include file.
src/arch/sparc/regfile.hh:
    Make Bit64 a ULL constant to avoid compiler error.

--HG--
extra : convert_revision : c46c179758271c4f00171faaa579915846bf4624
2006-06-10 00:22:42 -04:00
Steve Reinhardt
29e34a739b Move main control from C++ into Python.
User script now invokes initialization and
simulation loop after building configuration.
These functions are exported from C++ to Python
using SWIG.

SConstruct:
    Set up SWIG builder & scanner.
    Set up symlinking of source files into build directory
    (by not disabling the default behavior).
configs/test/test.py:
    Rewrite to use new script-driven interface.
    Include a sample option.
src/SConscript:
    Set up symlinking of source files into build directory
    (by not disabling the default behavior).
    Add SWIG-generated main_wrap.cc to source list.
src/arch/SConscript:
    Set up symlinking of source files into build directory
    (by not disabling the default behavior).
src/arch/alpha/ev5.cc:
src/arch/alpha/isa/decoder.isa:
src/cpu/o3/alpha_cpu_impl.hh:
src/cpu/trace/opt_cpu.cc:
src/cpu/trace/trace_cpu.cc:
src/sim/pseudo_inst.cc:
src/sim/root.cc:
src/sim/serialize.cc:
src/sim/syscall_emul.cc:
    SimExit() is now exitSimLoop().
src/cpu/base.cc:
    SimExitEvent is now SimLoopExitEvent
src/python/SConscript:
    Add SWIG build command for main.i.
    Use python/m5 in build dir as source for zip archive...
    easy now with file duplication enabled.
src/python/m5/__init__.py:
    - Move copyright notice back to C++ so we can print
    it right away, even for interactive sessions.
    - Get rid of argument parsing code; just provide default
    option descriptors for user script to call optparse with.
    - Don't clutter m5 namespace by sucking in all of m5.config
    and m5.objects.
    - Move instantiate() function here from config.py.
src/python/m5/config.py:
    - Move instantiate() function to __init__.py.
    - Param.Foo deferred type lookups must use m5.objects
    namespace now (not m5).
src/python/m5/objects/AlphaConsole.py:
src/python/m5/objects/AlphaFullCPU.py:
src/python/m5/objects/AlphaTLB.py:
src/python/m5/objects/BadDevice.py:
src/python/m5/objects/BaseCPU.py:
src/python/m5/objects/BaseCache.py:
src/python/m5/objects/Bridge.py:
src/python/m5/objects/Bus.py:
src/python/m5/objects/CoherenceProtocol.py:
src/python/m5/objects/Device.py:
src/python/m5/objects/DiskImage.py:
src/python/m5/objects/Ethernet.py:
src/python/m5/objects/Ide.py:
src/python/m5/objects/IntrControl.py:
src/python/m5/objects/MemObject.py:
src/python/m5/objects/MemTest.py:
src/python/m5/objects/Pci.py:
src/python/m5/objects/PhysicalMemory.py:
src/python/m5/objects/Platform.py:
src/python/m5/objects/Process.py:
src/python/m5/objects/Repl.py:
src/python/m5/objects/Root.py:
src/python/m5/objects/SimConsole.py:
src/python/m5/objects/SimpleDisk.py:
src/python/m5/objects/System.py:
src/python/m5/objects/Tsunami.py:
src/python/m5/objects/Uart.py:
    Fix up imports (m5 namespace no longer includes m5.config).
src/sim/eventq.cc:
src/sim/eventq.hh:
    Support for Python-called simulate() function:
    - Use IsExitEvent flag to signal events that want
    to exit the simulation loop gracefully (instead of
    calling exit() to terminate the process).
    - Modify interface to hand exit event object back to
    caller so it can be inspected for cause.
src/sim/host.hh:
    Add MaxTick constant.
src/sim/main.cc:
    Move copyright notice back to C++ so we can print
    it right away, even for interactive sessions.
    Use PYTHONPATH environment var to set module path
    (instead of clunky code injection method).
    Move main control from here into Python:
    - Separate initialization code and simulation loop
    into separate functions callable from Python.
    - Make Python interpreter invocation more pure (more
    like directly invoking interpreter).
    Add -i and -p flags (only options on binary itself;
    other options processed by Python).
    Import readline package when using interactive mode.
src/sim/sim_events.cc:
    SimExitEvent is now SimLoopExitEvent, and uses
    IsSimExit flag to terminate loop (instead of
    exiting simulator process).
src/sim/sim_events.hh:
    SimExitEvent is now SimLoopExitEvent, and uses
    IsSimExit flag to terminate loop (instead of
    exiting simulator process).
    Get rid of a few unused constructors.
src/sim/sim_exit.hh:
    SimExit() is now exitSimLoop().
    Get rid of unused functions.
    Add comments.

--HG--
extra : convert_revision : 280b0d671516b25545a6f24cefa64a68319ff3d4
2006-06-09 23:01:31 -04:00
Steve Reinhardt
935ba67b4f Get basic full-system working with AtomicSimpleCPU.
SConscript:
    Comment out sinic for now... needs to be fixed to compile under newmem.
configs/test/SysPaths.py:
    Fix paths.
configs/test/fs.py:
    SimpleCPU -> AtomicSimpleCPU
    Fix vmlinux path
cpu/simple/atomic.cc:
    Fix suspendContext() so quiesce works.
    Don't forget to checkForInterrupts().
cpu/simple/base.cc:
    Minor fix to interrupt check code.
dev/ide_disk.hh:
    Don't declare regStats() in header since it's not in
    .cc file anymore (will need to add it back in when
    stats are added back).
dev/io_device.cc:
    Set packet dest to Packet::Broadcast.
dev/pciconfigall.cc:
    Set PCI config packet result to Success.
python/m5/objects/Root.py:
    Add debug object to Root so things like break_cycles
    can be set from command line.

--HG--
extra : convert_revision : aa1c652fe589784e753e13ad9acb0cd5f3b6eafb
2006-05-17 22:08:44 -04:00
Steve Reinhardt
309e1d8193 Split SimpleCPU into two different models, AtomicSimpleCPU and
TimingSimpleCPU, which use atomic and timing memory accesses
respectively.  Common code is factored into the BaseSimpleCPU class.
AtomicSimpleCPU includes an option (simulate_stalls) to add delays
based on the estimated latency reported by the atomic accesses.
Plain old "SimpleCPU" is gone; I have not updated all the config
files (just test/test.py).
Also fixes to get timing accesses working in new memory model and
to get split-phase memory instruction definitions working with
new memory model as well.

arch/alpha/isa/main.isa:
    Need to include packet_impl.h for functions that use Packet objects.
arch/alpha/isa/mem.isa:
    Change completeAcc() methods to take Packet object pointers.
    Also split out StoreCond template for completeAcc(), since
    that's the only one that needs write_result and we get an
    unused variable warning if we always have it in there.
build/SConstruct:
    Update list of recognized CPU model names.
configs/test/test.py:
    Change SimpleCPU to AtomicSimpleCPU.
cpu/SConscript:
    Define sources for new CPU models.
    Add split memory access methods to CPU model signatures.
cpu/cpu_models.py:
cpu/static_inst.hh:
    Define new CPU models.
cpu/simple/base.cc:
cpu/simple/base.hh:
    Factor out pieces specific to Atomic or Timing models.
mem/bus.cc:
    Bus needs to be able to route timing packets based on explicit dest
    so responses can get back to requester.  Set dest to Packet::Broadcast
    to indicate that dest should be derived from address.
    Also set packet src field based on port from which packet is sent.
mem/bus.hh:
    Set packet src field based on port from which packet is sent.
mem/packet.hh:
    Define Broadcast destination address to indicate that
    packet should be routed based on address.
mem/physical.cc:
    Set packet dest on response so packet is routed
    back to requester properly.
mem/port.cc:
    Flag blob packets as Broadcast.
python/m5/objects/PhysicalMemory.py:
    Change default latency to be 1 cycle.

--HG--
rename : cpu/simple/cpu.cc => cpu/simple/base.cc
rename : cpu/simple/cpu.hh => cpu/simple/base.hh
extra : convert_revision : e9646af6406a20c8c605087936dc4683375c2132
2006-05-16 17:36:50 -04:00
Korey Sewell
0930024b88 Minor changes for FP ... MIPS now works for floating-point programs...
Now we are to the point where more benchmarks and instruction-coverage
is necessary to totally verify/validate correct operation across
all MIPS instructions

arch/mips/isa_traits.hh:
    fix for reading double values ... must rearrange bits before using void* to read double.
configs/test/hello_mips:
    real hello world MIPS binary

--HG--
extra : convert_revision : 153de1f8a830882c6972bd0bdb56da818f614def
2006-05-07 14:09:19 -04:00
Korey Sewell
de8eba6891 Merge zizzer:/bk/newmem
into  zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem

--HG--
extra : convert_revision : c48a8857f5a520ff8061eb3d8f08dcd43661e68c
2006-05-04 21:10:51 -04:00
Korey Sewell
97429d8eee Redo the FloatRegFile using unsigned integers
Edit the convert_and_round function which access FloatRegFile

arch/isa_parser.py:
    recognize when we are writing a 'uint64_t' FloatReg and set the width appropriately
arch/mips/isa/decoder.isa:
    Send a 'float' to the convert function instead of a unsigned word. Do this so we dont have to worry about the
    bit manipulation ourselves. We can just concern ourselves with values.

    Use unsigned double to get movd...
arch/mips/isa/formats/fp.isa:
    float debug statement
arch/mips/isa_traits.cc:
    add different versions of convert_and_round functions
arch/mips/isa_traits.hh:
    Use an array of uint32_t unsigned integers to represent the Floating Point Regfile
configs/test/hello_mips:
    basic FP program
cpu/simple/cpu.hh:
    spacing

--HG--
extra : convert_revision : a6fca91ad6365c83025f1131d71fa1b8ee76d7bc
2006-05-02 20:05:16 -04:00
Ali Saidi
ca8a659394 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : d6f7c4dd146613eeba39249f2d916a77108bc8c1
2006-04-28 15:41:22 -04:00
Ali Saidi
79170b1be5 random mix of tidbits
configs/test/fs.py:
    update fs.py to use a bus bridge
cpu/simple/cpu.hh:
    cpu should just return that it doesn't snoop any address ranges
python/m5/objects/System.py:
    move boot_osflags to system

--HG--
extra : convert_revision : b4256df7eada7e65b69513361de8bffc3fdd680b
2006-04-28 15:40:45 -04:00
Gabe Black
20c8553787 Merge m5.eecs.umich.edu:/bk/newmem
into  ewok.(none):/home/gblack/m5/newmem

cpu/simple/cpu.cc:
    Hand merged

--HG--
extra : convert_revision : 68414730c23d41c30cfb7bcfa604029a5fc8622c
2006-04-28 14:03:42 -04:00
Gabe Black
25bf3125da Changed the hello_sparc executable back to the cross compiled one
--HG--
extra : convert_revision : 565f75f76dd26ca0e25de4c89d1597a9f39483fd
2006-04-28 13:11:32 -04:00
Ali Saidi
8f8d09538f Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working
after merge from head. Checkpointing may need some work now. Endian-happiness still not complete.

SConscript:
    add all devices back into make file
base/inet.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.cc:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/pktfifo.cc:
dev/pktfifo.hh:
    rename PacketPtr EthPacketPtr so it doesn't conflict with the PacketPtr type in the memory system
configs/test/fs.py:
    add nics to fs.py
cpu/cpu_exec_context.cc:
    remove this check, as it's not valid. We may want to add something else back in to make sure that no one can delete the
    static virtual ports in the exec context
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
dev/alpha_console.cc:
dev/ide_ctrl.cc:
    use new methods for accessing packet data
dev/ide_disk.cc:
    add some more dprintfs
dev/io_device.cc:
    delete packets when we are done with them. Update for new packet methods to access data
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart8250.cc:
dev/uart8250.hh:
mem/physical.cc:
mem/port.cc:
    dUpdate for new packet methods to access data
dev/ns_gige.cc:
    Update for new memory system
dev/ns_gige.hh:
python/m5/objects/Ethernet.py:
    update for new memory system
dev/sinic.cc:
dev/sinic.hh:
    Update for new memory system. Untested as need to merge in head because of kernel driver differences between versions
mem/packet.hh:
    Add methods to access data instead of accessing it directly.

--HG--
extra : convert_revision : 223f43876afd404e68337270cd9a5e44d0bf553e
2006-04-24 19:31:50 -04:00
Ali Saidi
6dc3b2fa39 make ide disk work for newmem
SConscript:
    compile ide devices
base/chunk_generator.hh:
    add another parameter to the chuck generator called complete() which
    returns the number of bytes transfered so far. Very useful for
    adding to a pointer.
configs/test/fs.py:
    Add ide disk to fs test configuration
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/ide_disk.cc:
dev/ide_disk.hh:
dev/io_device.cc:
dev/io_device.hh:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/pcidev.cc:
dev/pcidev.hh:
    update for new memory system
mem/bus.cc:
    support devices that return multiple ranges
    remove old ranges before using new info
mem/packet.hh:
    make senderstate void* per steve's request that we use every
    construct possible in C++
mem/physical.cc:
    have memory stamp the packet with the time.
mem/physical.hh:
    actually set the memory latency variable
python/m5/objects/Device.py:
    Add DmaDevice
python/m5/objects/Ide.py:
    Ide disk no longer has a physmem pointer
python/m5/objects/Pci.py:
    update pci device for newmem
python/m5/objects/PhysicalMemory.py:
    add latency parameter for physical memory
sim/byteswap.hh:
    use fast architecture dependent byteswap calls if they exist

--HG--
extra : convert_revision : e3cf2e8f61064ad302d94bc22010a00c59f3f793
2006-04-20 17:14:30 -04:00
Korey Sewell
200205aa85 update Hello World binary for mips... the old one did not have a newline
--HG--
extra : convert_revision : f015cac39e42e11b1a56bbd1c5cf07403eb8f2da
2006-04-13 17:40:16 -04:00
Ali Saidi
81a735a716 fs now gets to the point where it would really like a filesystem.
Time to make the ide device work

arch/alpha/system.cc:
    write the machine type and rev in the correct place
cpu/simple/cpu.cc:
    reset the packet structure every time it's reused... wow the
    simple cpu code  for talking to memory is getting horrible.
dev/alpha_console.cc:
    move the setAlphaAccess to startup() to make sure that the console
    binary is loaded
dev/tsunami_cchip.cc:
dev/tsunami_pchip.cc:
dev/uart8250.cc:
    fix a couple of bugs injected in the newmem fixes
mem/bus.cc:
    More verbose bus tracing
mem/packet.hh:
    Add a constructor to packet to set the result to unknown and a reset
    method in the case it's being reused
mem/vport.hh:
    don't need are own read/write methods since the base functional port
    ones call writeBlob readBlob which do the translation for us

--HG--
extra : convert_revision : 8d0e2b782bfbf13dc5c59dab1a79a084d2a7da0a
2006-04-12 17:46:25 -04:00
Ali Saidi
6a7108897b a sparc binary that can be debugged
--HG--
extra : convert_revision : cb021c1e704b5771e0f86e794b7e59f8a4b96856
2006-04-06 18:32:10 -04:00
Gabe Black
6d8d6d15cd Fixed up the isa description. Also added some capability to the isa_parser in the InstObjParams constructor.
arch/isa_parser.py:
    Expanded the capability of the InstObjParams constructor to allow adding in extra keys for use in templates. These are added as key, value tuples as optional arguements.
arch/sparc/isa/base.isa:
arch/sparc/isa/formats/mem.isa:
arch/sparc/isa/formats/priv.isa:
    The genCompositeIop function is no longer needed, as this functionality is now in the InstObjParams constructor.
arch/sparc/isa/decoder.isa:
    Fixed up alot of instructions, and fixed indentation.
arch/sparc/isa/formats/integerop.isa:
    The genCompositeIop function is no longer needed, as this functionality is now in the InstObjParams constructor. Also changed the immediate values to be signed.
base/traceflags.py:
    Added SPARC traceflag
configs/test/hello_sparc:
    Recompiled without -mflat
cpu/cpu_exec_context.cc:
    Used the regfile clear function rather than memsetting to 0.

--HG--
extra : convert_revision : b9da6f264f3ebc4ce1815008dfff7f476b247ee9
2006-04-06 14:52:44 -04:00
Gabe Black
5c79eb0410 Fixes to SPARC for syscall emulation mode.
arch/sparc/isa/base.isa:
arch/sparc/isa/decoder.isa:
arch/sparc/isa/formats.isa:
arch/sparc/isa/formats/branch.isa:
arch/sparc/isa/formats/integerop.isa:
arch/sparc/isa/formats/mem.isa:
arch/sparc/isa/formats/nop.isa:
arch/sparc/isa/formats/trap.isa:
arch/sparc/isa/formats/unknown.isa:
arch/sparc/isa/includes.isa:
arch/sparc/isa/operands.isa:
    Fixes towards running in syscall emulation mode.
arch/sparc/linux/process.cc:
    Fixed the assert and comment to check that the Num_Syscall_Descs is less than or equal to 284. Why does this assert need to exist anyway?
base/loader/elf_object.cc:
    Cleared out comments about resolved issues.
cpu/simple/cpu.cc:
    Use NNPC for both SPARC and MIPS, instead of just MIPS
configs/test/hello_sparc:
    A test program for SPARC which prints "Hello World!"

--HG--
rename : arch/sparc/isa/formats/noop.isa => arch/sparc/isa/formats/nop.isa
extra : convert_revision : 10b3e3b9f21c215d809cffa930448007102ba698
2006-03-31 20:31:53 -05:00
Ali Saidi
3dcb589ea4 update for connector magic
--HG--
extra : convert_revision : 111af292373edebcd106938e76610f9ac4a6ce58
2006-03-29 17:39:20 -05:00
Ali Saidi
4973a16b34 update for objects having a bus
--HG--
extra : convert_revision : 96b5494b7d0b5ca702ac69cfa0bf8c4d44e1cc3b
2006-03-25 18:34:50 -05:00
Korey Sewell
77a2f97c35 Merge zizzer:/bk/newmem
into  zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-mips

--HG--
extra : convert_revision : 9bdde9b5bd3049744451eda1134f080b7c4b1b59
2006-03-15 23:38:55 -05:00
Ali Saidi
97e424982a add translations for new sections that are mmapped or when the brk
is changed
Add a default machine width parameter
Arch based live processes

arch/alpha/linux/process.cc:
arch/alpha/linux/process.hh:
arch/alpha/process.cc:
arch/alpha/process.hh:
arch/alpha/tru64/process.cc:
arch/alpha/tru64/process.hh:
arch/mips/linux_process.cc:
arch/mips/process.cc:
arch/mips/process.hh:
arch/sparc/linux/process.cc:
arch/sparc/linux/process.hh:
arch/sparc/process.cc:
arch/sparc/process.hh:
configs/test/test.py:
python/m5/objects/Process.py:
sim/process.cc:
sim/process.hh:
    Architecture based live processes
arch/mips/isa_traits.hh:
arch/sparc/isa_traits.hh:
    Add a default machine width parameter
mem/port.hh:
    gcc 4 really wants  a virtual destructor
sim/byteswap.hh:
    remove the comment around long and unsigned long even though uint32_t
    and int32_t are defined. Seems to work with gcc 4 and 3.4.3.
sim/syscall_emul.cc:
sim/syscall_emul.hh:
    add translations for new sections that are mmapped or when the brk
    is changed

--HG--
extra : convert_revision : e2f9f228113c7127c87ef2358209a399c30ed5c6
2006-03-15 17:04:50 -05:00
Korey Sewell
e2b558112b add mips simple test in config directory
configs/test/hello_mips:
    hello world mips binary

--HG--
extra : convert_revision : 5a495e1bfb1cbddc0879f8e80c02bd7435a02acb
2006-03-15 16:29:18 -05:00
Steve Reinhardt
e3d96aa889 Compiles now (with CPU_MODELS=SimpleCPU), but hangs
on execution.

configs/test/test.py:
    Move test binary out of m5-test, don't depend on
    m5-test/Benchmarks.
python/m5/objects/System.py:
    Split out full-system-only parameters (lost in merge).
sim/system.cc:
    Need to be able to instantiate System directly in SE mode
    (lost in merge).
sim/system.hh:
    A few more functions here are FS-only.
configs/test/hello:
    Add in binary.

--HG--
rename : configs/test.py => configs/test/test.py
extra : convert_revision : 4051b18772e0a0dcb97eb591d4373683be9f4395
2006-03-10 10:01:29 -05:00
Steve Reinhardt
22504f8b48 More progress toward actually running a program.
See configs/test.py for test config (using simple
binary in my home directory on zizzer).

base/chunk_generator.hh:
    Fix assertion for chunkSize == 0 (not a power of 2)
base/intmath.hh:
    Fix roundDown to take integer alignments.
cpu/base.cc:
    Register exec contexts regardless of state (not sure why
    this check was in here in the first place).
mem/physical.cc:
    Add breaks to switch.
python/m5/objects/BaseCPU.py:
    Default mem to Parent.any (e.g. get from System).
python/m5/objects/Ethernet.py:
python/m5/objects/Root.py:
    HierParams is gone.
python/m5/objects/PhysicalMemory.py:
    mmu param is full-system only.
sim/process.cc:
    Stack mapping request must be page-aligned and page-sized.
    Don't delete objFile object in create since we are counting
    on it being around for startup().

--HG--
extra : convert_revision : 90c43ee927e7d82a045d6e10302d965797d006f7
2006-03-01 18:45:50 -05:00
Ali Saidi
481219caf6 Add support for multiple streams being configured with the INITPARAM
variable

--HG--
extra : convert_revision : 2cb20845cb7f32589882850156bdd42d9024db7a
2005-11-29 18:06:15 -05:00
Nathan Binkert
61f59f639c Clean up the newly updated iscsi-client script
configs/boot/iscsi-client.rcS:
    Clean up the newly updated iscsi-client script.
    Reduce the writeback period so writes occur more frequently.

--HG--
extra : convert_revision : 21c84f781c6537b28c753291561d23c2d0144627
2005-11-22 13:33:28 -05:00
Lisa Hsu
b018a01f0c new rcS file for open-iscsi rather than the old linux-iscsi
--HG--
extra : convert_revision : 0c12033b38e32f8b2ea69b52813dfed294ec5de4
2005-11-09 16:40:27 -05:00
Nathan Binkert
c7b211e71f various changes to the boot scripts
configs/boot/iscsi-client.rcS:
configs/boot/nfs-client-dbench.rcS:
    don't use the /proc/m5 stuff, use the m5 binary
configs/boot/nfs-client-nhfsstone.rcS:
    set up checkpoints
    change nhfsstone configuration
configs/boot/nfs-client.rcS:
    use more memory
configs/boot/nfs-server.rcS:
    change the writeback frequency
    load a larger simulated disk image.
    create more nfsd threads

--HG--
extra : convert_revision : 242dfd261d62782c06847d64b9f6aa06664a1ec9
2005-09-16 22:54:01 -04:00
Nathan Binkert
02f9ea609a Add NFS-dbench, and iscsi dbench benchmarks
--HG--
extra : convert_revision : 71e416668f4bbcf9785ea2363ec406135a217e32
2005-06-13 11:54:23 -04:00
Steve Reinhardt
ed743cb3b0 Clean up to work with recent python config changes.
configs/splash2/run.py:
    parent is now Parent.
    Need to explicitly instantiate classes.

--HG--
extra : convert_revision : c260fad00ca82cb1032e73af2e5caa2ad013067d
2005-06-04 23:08:26 -04:00
Steve Reinhardt
3e7f660401 A few more config updates. Works with regression now.
configs/splash2/run.py:
    Update file for new config changes.
python/m5/config.py:
    - isParamContext() not defined any more
    - fix bug with re-assigning vectors over scalars
    and vice versa

--HG--
rename : configs/splash2/run.mpy => configs/splash2/run.py
extra : convert_revision : 2eb28a92f8de327f6dfddd01467c61e759275f6b
2005-06-01 17:08:45 -04:00
Nathan Binkert
849c954adf Cleanup rcS files. Make sure there are enough tracked connections.
Delay before singalling peer to make sure that the peer is ready

configs/boot/nat-netperf-server.rcS:
    delay before singalling to make sure that the natbox is ready
configs/boot/nat-netperf-stream-client.rcS:
    increase the number of tracked connections
configs/boot/nat-spec-surge-client.rcS:
configs/boot/nfs-client-nhfsstone.rcS:
configs/boot/nfs-client-smallb.rcS:
configs/boot/nfs-client-tcp-smallb.rcS:
configs/boot/nfs-client-tcp.rcS:
configs/boot/nfs-client.rcS:
configs/boot/nfs-server.rcS:
configs/boot/spec-surge-client.rcS:
configs/boot/spec-surge-server.rcS:
configs/boot/surge-client.rcS:
configs/boot/surge-server.rcS:
    increase the number of tracked connections
    cleanup
configs/boot/nat-spec-surge-server.rcS:
configs/boot/natbox-netperf.rcS:
configs/boot/nfs-server-nhfsstone.rcS:
    delay before singalling to make sure that the natbox is ready
    increase the number of tracked connections
    cleanup
configs/boot/natbox-spec-surge.rcS:
    delay before singalling to make sure that the natbox is ready
    increase the number of tracked connections

--HG--
extra : convert_revision : 9faa5ec11c9c02fed3d1cff922ca42c41d364204
2005-04-30 11:00:43 -04:00
Ron Dreslinski
2bb9126a7a Make ip_conntrack table size larger
--HG--
extra : convert_revision : bda54b29cb15144907b186f06517477dea13ba06
2005-04-28 16:13:30 -04:00
Ali Saidi
97064c5216 Add some new config files
--HG--
extra : convert_revision : b454144b3c00c101e970269c6c084d601cee971f
2005-03-23 15:57:38 -05:00
Ron Dreslinski
14c461c93c Fixed the super/parent change fpr splash2 benchmarks
configs/splash2/run.mpy:
    Change super to parent

--HG--
extra : convert_revision : 61d45880b5e334200ebebc24d757c97cbeb048f6
2005-03-16 15:55:44 -05:00
Ron Dreslinski
1eb5e618de Added config files for splash2 benchmarks. Parameters:
ROOTDIR = root directory of the splash2 code
NP = number of proccessors
BENCHMARK = name of the splash2 benchmark (Cholesky, FFT, LUContig, LUNoncontig, Radix, Barnes, FMM, OceanContig, OceanNoncontig, Raytrace, WaterNSquared, or WaterSpatial)
SYSTEM = Type of system to simulate detailed or simple

Note:  They use MOESI protocol and do_events is enabled (Multiple L1's and a shared L2)

--HG--
extra : convert_revision : c39aa73825ea8108b6c32abd4a4fa4c23391ab09
2005-03-11 18:07:07 -05:00
Ali Saidi
2897665685 Merge zizzer:/bk/m5 into zeep.eecs.umich.edu:/z/saidi/work/m5
--HG--
extra : convert_revision : a61ddd67647fc6a6e8e12d918cc71ae9da69f869
2005-03-09 15:56:29 -05:00
Lisa Hsu
550e6a5010 Merge zizzer:/bk/m5 into zed.eecs.umich.edu:/z/hsul/work/m5/pact05
--HG--
extra : convert_revision : bfaaeebd7ec4ee8ee182909e928581f95ac2af93
2005-03-08 17:38:08 -05:00
Lisa Hsu
91601f4494 make some changes to bonnie - now that the simulator uses more memory the old config didn't fit anymore in pools VM, this does fit.
--HG--
extra : convert_revision : b5fef2896276be675f79791b084ba97dd953d4ca
2005-03-08 17:25:32 -05:00
Nathan Binkert
47dec0f411 Fix the singalling from server to client so that the
benchmark begins properly.

configs/boot/nat-netperf-maerts-client.rcS:
    Fix the echo message
configs/boot/nat-netperf-server.rcS:
    Wait a second before signalling the natbox to make sure it's
    had time to boot.
    Fix echo message.

--HG--
extra : convert_revision : f9d32c98f24b9617ebf917790a4ca554b7b02bba
2005-03-08 12:37:08 -05:00
Lisa Hsu
0804a7530f the client and server aren't rate-matched anymore and the timing of the netcats are off - add a sleep 1 to make it actually work.
--HG--
extra : convert_revision : 3fa730a94d9270945d34061513ab9ce0ab60e7ba
2005-03-05 15:16:29 -05:00
Ali Saidi
8268426f30 Updated Monet Configuration and validations tests
--HG--
extra : convert_revision : d58aed18f8f809185ad2639eb92465a5fc6695de
2005-03-01 01:03:37 -05:00
Ali Saidi
a84159174a added two validation rcs files
--HG--
extra : convert_revision : 19e57e5192be3435d72652e3b36aac3b6e43d81c
2005-02-23 11:46:28 -05:00
Ali Saidi
7e559f6c50 Add Monet configuration, update p4 parameters, couple of typo fixes
dev/tsunami_cchip.cc:
    add a fake register to tsunami that we can do 32bit reads to.
    Warn on access.

--HG--
extra : convert_revision : d87860f3b527528151c23431556039bca6e12945
2005-02-03 23:50:57 -05:00
Lisa Hsu
c3aaf43c88 make nat runs used vegas congestion avoidance implementation.
--HG--
extra : convert_revision : 29d2c4b70c56f13642466bd88c82f36ba849ed9d
2005-01-28 15:57:40 -05:00
Nathan Binkert
ceec841980 add a no touch stream benchmark clean up a little
--HG--
extra : convert_revision : 41ff3dc85492e1d57fc30389f923d564156b4237
2004-11-18 16:23:28 -05:00
Nathan Binkert
91628e13a9 Merge zizzer.eecs.umich.edu:/bk/m5
into ziff.eecs.umich.edu:/z/binkertn/research/m5/latest

--HG--
extra : convert_revision : e1a178b33e9de6a6a04d4967b1abe9cc7fddcea3
2004-11-17 22:08:36 -05:00
Ali Saidi
72aea04d8d fixed swap disk, now it doesn't have a partition table
--HG--
extra : convert_revision : a2b6ddd25e179b830dd58a1940ca8e1f20684b2e
2004-11-17 22:05:29 -05:00
Nathan Binkert
69039fe101 Reduce the amount of time we delay when dumping a checkpoint for
netperf runs

configs/boot/nat-netperf-maerts-client.rcS:
configs/boot/nat-netperf-stream-client.rcS:
configs/boot/netperf-maerts-client.rcS:
configs/boot/netperf-rr.rcS:
configs/boot/netperf-stream-client.rcS:
    dont' delay for so long when dumping a checkpoint

--HG--
extra : convert_revision : 25f35957ceef3f55c6edb77fa07be0044de5ec36
2004-11-17 21:38:08 -05:00
Ali Saidi
77e0868099 Add the boot scripts for nfs tcp
--HG--
extra : convert_revision : 74625c44f2f7c9bcdc2718bbee891ea112f07583
2004-11-17 18:56:57 -05:00
Ali Saidi
95fdc9e47b added small block nfs script
--HG--
extra : convert_revision : 1fab69c3ccda27cab2cec1375bc1bd02b2b8f156
2004-11-17 02:08:27 -05:00
Lisa Hsu
1d25eb4cbf Merge zizzer:/bk/m5 into zed.eecs.umich.edu:/z/hsul/work/m5
--HG--
extra : convert_revision : 6c02cd3a846edcb915ba5d243bb938a9cc42f154
2004-11-16 22:43:23 -05:00
Lisa Hsu
182425da82 add support for NAT under netperf stream, maerts, and spec-surge.
configs/boot/spec-surge-client.rcS:
configs/boot/surge-client.rcS:
    fix this rcS - don't sleep, instead wait for the server to tell you it's done.
configs/boot/spec-surge-server.rcS:
configs/boot/surge-server.rcS:
    notify the client you're done starting the server.

--HG--
extra : convert_revision : b708bd0a9147e248eed7c27e7078668fbd98b95e
2004-11-16 22:43:12 -05:00
Ali Saidi
9f2df2d621 skip the nfs charecter by charecter and re-write stuff
configs/boot/nfs-client.rcS:
    skip the charecter and rewrite test

--HG--
extra : convert_revision : 2630e1f1a2a52a4e96a45e12769a94de28ad5c93
2004-11-16 21:59:12 -05:00
Ali Saidi
82235799d3 fixed for 768MB runs
--HG--
extra : convert_revision : c86b282788919d414470aaf551094fee1bebbbab
2004-11-16 00:34:45 -05:00
Nathan Binkert
eb7b873b05 Fix up the spec-surge benchmark
configs/boot/spec-surge-client.rcS:
    change the number of connections and add stuff for the
    file set size and checkpointing

--HG--
extra : convert_revision : 9e0fe74f44300893c6050e3eb1ae302f71c02767
2004-11-15 18:20:43 -05:00
Nathan Binkert
63dbaccdc4 more whitespace fixes
configs/boot/spec-surge-client.rcS:
configs/boot/spec-surge-server.rcS:
    whitespace fixes

--HG--
extra : convert_revision : 90eb2a325a3cf4436081c992d6f3e0f903980ff7
2004-11-15 16:07:28 -05:00
Nathan Binkert
abbbea57a7 more formatting
configs/boot/nfs-server.rcS:
    fix whitespace

--HG--
extra : convert_revision : d421d5fa1e041b041d7c47d36abe55a2dd3e7487
2004-11-15 15:45:55 -05:00
Nathan Binkert
2cc34a34df formatting
configs/boot/nfs-client.rcS:
    fix whitespace

--HG--
extra : convert_revision : dc384870de9431fe30b13a2c8c69d97b2d06dca9
2004-11-15 15:44:25 -05:00
Nathan Binkert
49d470a3b5 cleanup the nfs server script
configs/boot/nfs-server.rcS:
    don't need extra IP aliases

    re-order the nfs daemons so they happen in the right order
    and don't have the shell put them in the background since they
    will auto detach anyway.

--HG--
extra : convert_revision : a6b13ac91d1649878d346663f6ddff56d9a8a8ec
2004-11-15 15:42:15 -05:00
Ali Saidi
a89398e262 patched nfs boot scripts
configs/boot/nfs-server.rcS:
    made the partition size correct

--HG--
extra : convert_revision : 4e9bdbe3e465aea2a914fd928b47296031c2523b
2004-11-13 23:09:17 -05:00
Ali Saidi
f63dd31f4e fixed nfs scripts hopefully for the last time
configs/boot/nfs-client.rcS:
    lucky #3

--HG--
extra : convert_revision : a55f29e4c087e7ab95ea584316ad6fe4ebb5df9a
2004-11-13 23:08:08 -05:00
Ali Saidi
2282b0aa61 Merge zizzer:/bk/m5 into zeep.eecs.umich.edu:/tmp/m5
--HG--
extra : convert_revision : 7696b915099bc847bbb9bd9f97fd30b1825c68d5
2004-11-12 18:47:14 -05:00
Ali Saidi
8fc76693d2 slightly different parameters for nfs script
--HG--
extra : convert_revision : 1576f875646567cc661a8e3f07c00c4b282e9f64
2004-11-12 18:47:07 -05:00
Lisa Hsu
78118bffbb add surge and spec-surge readfiles. also make the naming system uniform, there were 3 different ways!!! i like ali's.
--HG--
rename : configs/boot/client.netperf.maerts => configs/boot/netperf-maerts-client.rcS
rename : configs/boot/client.netperf.rr => configs/boot/netperf-rr.rcS
rename : configs/boot/server.netperf => configs/boot/netperf-server.rcS
rename : configs/boot/client.netperf.stream => configs/boot/netperf-stream-client.rcS
extra : convert_revision : 8c841e18dac9634f0680b857f3d0676b100dd448
2004-11-12 15:03:28 -05:00
Ali Saidi
856fdbe5aa Added nfs-client.rcS and nfs-server.rcS
--HG--
extra : convert_revision : 48cf156ce397b68075c07ed072c95644affa3ef1
2004-11-12 14:21:52 -05:00
Nathan Binkert
e3d0e9cf76 commented script with various kernel parameter tweaks for better
network performance

--HG--
extra : convert_revision : 9fd2f18a0d2b79942661d764d90177a50754d9c0
2004-08-11 10:17:11 -04:00
Nathan Binkert
00270ba3a7 tweak a bunch of kernel parameters to get better performance
--HG--
extra : convert_revision : 57cca576fac4013027c2cb6c85cc73cbbcf772ae
2004-08-10 09:08:36 -04:00
Nathan Binkert
7739f32758 fix paths for changes in disk image layout
--HG--
extra : convert_revision : 506ff845efc8d786639c29931eb4abd3a5860fcf
2004-07-14 09:06:56 -04:00
Nathan Binkert
989eb88576 Scripts that can be used with server.readfile and client.readfile
to run the netperf benchmark

--HG--
extra : convert_revision : a2ce490e0c44996d0876a6839ad333643ec252c8
2004-07-08 16:01:13 -04:00