Created the following HBM configurations:
1) HBM gen1 (x128/CH), 2Gb die, 4H stack, 1Gbps, 8 channels
2) HBM gen2 (x64/PC), 8Gb die, 4H stack, 1Gbps, 16 pseudo-channels
The configuration values are based on:
- The HBM gen1 public JEDEC spec
- Publically released data from MemCon presentations
- Timing extrapolated from existing LPDDR configurations
Will adjust once specs become available.
Changeset 4872dbdea907 replaced Address by Addr, but did not make changes to
print statements. So the addresses which were being printed in hex earlier
along with their line address, were now being printed in decimals. This patch
adds a function printAddress(Addr) that can be used to print the address in hex
along with the lines address. This function has been put to use in some of the
places. At other places, change has been made to print just the address in
hex.
The DataMember class in Type.py was being derived from PairContainer. A
separate Var object was also created for the DataMember. This meant some
duplication of across the members of these two classes (Var and DataMember).
This patch changes DataMember from Var instead. There is no obvious reason to
derive from PairContainer which can only hold pairs, something that Var class
already supports. The only thing that DataMember has over Var is init_code,
which is being retained. This change would later on help in having pointers
in DataMembers.
Some blocks in MOESI hammer were not getting deallocated when they were set to
an idle state (e.g. by invalidate or other_getx/s messages). While
functionally correct, this caused some bad effects on performance, such as
blocks in I in the L1s getting sent to the L2 upon eviction, in turn evicting
valid blocks. Also, if a valid block was in LRU, that block could be evicted
rather than a block in I. This patch adds in the missing deallocations.
Committed by: Nilay Vaish<nilay@cs.wisc.edu>
The recent changes to make MessageBuffers SimObjects required them to be
initialized in a particular order, which could break some protocols. Fix this
by calling initNetQueues on the external nodes of each external link in the
constructor of Network.
This patch also refactors the duplicated code for checking network allocation
and setting net queues (which are called by initNetQueues) from the simple and
garnet networks to be in Network.
This patch changes MessageBuffer and TimerTable, two structures used for
buffering messages by components in ruby. These structures would no longer
maintain pointers to clock objects. Functions in these structures have been
changed to take as input current time in Tick. Similarly, these structures
will not operate on Cycle valued latencies for different operations. The
corresponding functions would need to be provided with these latencies by
components invoking the relevant functions. These latencies should also be
in Ticks.
I felt the need for these changes while trying to speed up ruby. The ultimate
aim is to eliminate Consumer class and replace it with an EventManager object in
the MessageBuffer and TimerTable classes. This object would be used for
scheduling events. The event itself would contain information on the object and
function to be invoked.
In hindsight, it seems I should have done this while I was moving away from use
of a single global clock in the memory system. That change led to introduction
of clock objects that replaced the global clock object. It never crossed my
mind that having clock object pointers is not a good design. And now I really
don't like the fact that we have separate consumer, receiver and sender
pointers in message buffers.
The eventual aim of this change is to pass RubySystem pointers through to
objects generated from the SLICC protocol code.
Because some of these objects need to dereference their RubySystem pointers,
they need access to the System.hh header file.
In src/mem/ruby/SConscript, the MakeInclude function creates single-line header
files in the build directory that do nothing except include the corresponding
header file from the source tree.
However, SLICC also generates a list of header files from its symbol table, and
writes it to mem/protocol/Types.hh in the build directory. This code assumes
that the header file name is the same as the class name.
The end result of this is the many of the generated slicc files try to include
RubySystem.hh, when the file they really need is System.hh. The path of least
resistence is just to rename System.hh to RubySystem.hh.
--HG--
rename : src/mem/ruby/system/System.cc => src/mem/ruby/system/RubySystem.cc
rename : src/mem/ruby/system/System.hh => src/mem/ruby/system/RubySystem.hh
This register is writable according to UA2005
Tried to boot NetBSD which starts the kernel by writing to the tick_cmpr
register. Without the patch gem5 crashes with a panic. With the patch NetBSD
starts to boot normally (although sun4v support in NetBSD is not complete yet)
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Handle bad IDE disk image size 0. When image size is 0, gem5 will cause an
exception with log "Floating point exception (core dumped)".
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
When a branch gets squashed, it's speculative branch predictor state should get
rolled back in squash(). However, only the globalHistory state was being
rolled back. This patch adds (at least some) support for rolling back the
local predictor state also.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
This patch enables instructions in LSQ to track two physical addresses for
corresponding two split requests. Later, the information is used in
checksnoop() to search for/invalidate the corresponding LD instructions.
The current implementation has kept track of only the physical address that is
referenced by the first split request. Thus, for checksnoop(), the line
accessed by the second request has not been considered, causing potential
correctness issues.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Refactored the code in operateVnet(), moved partly to a new function
operateMessageBuffer(). This is required since a later patch moves to having a
wakeup event per MessageBuffer instead of one event for the entire Switch.
There are two reasons for doing so:
a. provide a source of clock to PerfectSwitch. A follow on patch removes sender
and receiver pointers from MessageBuffer means that the object owning the
buffer should have some way of providing timing info.
b. schedule events. A follow on patch removes the consumer class. So the
PerfectSwitch needs some EventManager object to schedule events on its own.
Add a stat that counts buffer underruns in the HDLCD controller. The
stat counts at most one underrun per frame since the controller aborts
the current frame if it underruns.
Rewrite the HDLCD controller to use the new DMA engine and pixel
pump. This fixes several bugs in the current implementation:
* Broken/missing interrupt support (VSync, underrun, DMA end)
* Fragile resolution changes (changing resolutions used
to cause assertion errors).
* Support for resolutions with a width that isn't divisible by 32.
* The pixel clock can now be set dynamically.
This breaks checkpoint compatibility. Checkpoints can be upgraded with
the checkpoint conversion script. However, upgraded checkpoints won't
contain the state of the current frame. That means that HDLCD
controllers restoring from a converted checkpoint immediately start
drawing a new frame (i.e, expect timing differences).
Currently the sequencer calls the function setMRU that updates the replacement
policy structures with the first level caches. While functionally this is
correct, the problem is that this requires calling findTagInSet() which is an
expensive function. This patch removes the calls to setMRU from the sequencer.
All controllers should now update the replacement policy on their own.
The set and the way index for a given cache entry can be found within the
AbstractCacheEntry structure. Use these indicies to update the replacement
policy structures.
The current Set data structure is slow and therefore is being reimplemented
using std::bitset. A maximum limit of 64 is being set on the number of
controllers of each type. This means that for simulating a system with more
controllers of a given type, one would need to change the value of the variable
NUMBER_BITS_PER_SET
MessageBuffer is a SimObject now. There were protocols that still declared
some of the message buffers are variables of the controller, but not as input
parameters. Special handling was required for these variables in the SLICC
compiler. This patch changes this. Now all message buffers are declared as
input parameters.
In cases where a newly added target does not have any upstream MSHR to
mark as downstreamPending, remember that nothing is marked. This
allows us to avoid attempting to find the MSHR as part of the clearing
of downstreamPending.
This commit addresses gem5 checkpoints' linear versioning bottleneck.
Since development is distributed across many private trees, there exists
a sort of 'race' for checkpoint version numbers: internally a checkpoint
version may be used but then resynchronizing with the external tree causes
a conflict on that version. This change replaces the linear version number
with a set of unique strings called tags. Now the only conflicts that can
arise are of tag names, where collisions are much easier to avoid.
The checkpoint upgrader (util/cpt_upgrader.py) upgrades the version
representation, as one would expect. Each tag version implements its
upgrader code in a python file in the util/cpt_upgraders directory
rather than adding a function to the upgrader script itself.
The version tags are stored in the 'Globals' section rather than 'root'
(as the version was previously) because 'Globals' gets unserialized
first and can provide a warning before any other unserialization errors
can occur.
This is in support of tag-based checkpoint versioning. It should be
possible to examine an optional parameter in a checkpoint during
unserialization and not have it throw a warning.
We no longer use the C library based random number generator: random().
Instead we use the C++ library provided rng. So setting the random seed for
the RubySystem class has no effect. Hence the variable and the corresponding
option are being dropped.
Event auto-serialization no longer in use and has been broken ever
since the introduction of PDES support almost two years
ago. Additionally, serializing the individual event queues is
undesirable since it exposes the thread structure of the
simulator. What this means in practice is that the number of threads
in the simulator must be the same when taking a checkpoint and when
loading the checkpoint.
This changeset removes support for the AutoSerialize event flag and
the associated serialization code.
EtherLink currently uses a fire-and-forget link delay event that
delays sending of packets by a fixed number of ticks. In order to
serialize this event, it relies on the event queue's auto
serialization support. However, support for event auto serialization
has been broken for more than two years, which means that checkpoints
of multi-system setups are likely to drop in-flight packets.
This changeset the replaces rewrites this part of the EtherLink to use
a packet queue instead. The queue contains a (tick, packet) tuple. The
tick indicates when the packet will be ready. Instead of relying on
event autoserialization, we now explicitly serialize the packet queue
in the EhterLink::Link class.
Note that this changeset changes the way in-flight packages are
serialized. Old checkpoints will still load, but in-flight packets
will be dropped (just as before). There has been no attempt to upgrade
checkpoints since this would actually change the behavior of existing
checkpoints.
This changeset removes the support for the autoserialize parameter in
GlobalSimLoopExitEvent (including exitSimLoop()) and
LocalSimLoopExitEvent.
Auto-serialization of the LocalSimLoopExitEvent was never used, so
this is not expected to affect anything. However, it was sometimes
used for GlobalSimLoopExitEvent. Unfortunately, serialization of
global events has never been supported, so checkpoints with such
events will currently cause simulation panics.
The serialize parameter to exitSimLoop() has been left in-place to
maintain API compatibility (removing it would affect m5ops). Instead
of just dropping it, we now print a warning if the parameter is set
and the exit event is scheduled in the future (i.e., not at the
current tick).
The object resolver isn't serialization specific and shouldn't live in
serialize.hh. Move it to sim_object.hh since it queries to the
SimObject hierarchy.
This member indicates whether or not a particular virtual network is in use.
Instead of having a default big value for the number of virtual networks and
then checking whether a virtual network is in use, the next patch removes the
default value and the protocol configuration file would now specify the
number of virtual networks it requires.
Additionally, the patch also refactors some of the code used for computing the
virtual channel next in the round robin order.
Both FuncCallExprAST and MethodCallExprAST had code for checking the arguments
with which a function is being called. The patch does away with this
duplication. Now the code for checking function call arguments resides in the
Func class.
The new serialization code (kudos to Tim Jones) moves all of the state
mangling in RubySystem to memWriteback. This makes it possible to use
the new const serialization interface.
This changeset moves the cache recorder cleanup from the checkpoint()
method to drainResume() to make checkpointing truly constant and
updates the checkpointing code to use the new interface.
The sequencer takes care of llsc accesses by calling upon functions
from the CacheMemory. This is unnecessary once the required CacheEntry object
is available. Thus some of the calls to findTagInSet() are avoided.
The O3CPU blocks the Fetch when it sees a quiesce instruction (IsQuiesce flag).
When the inst. is executed, a quiesce event is created to reactivate the
context and unblock the Fetch.
If the quiesceNs or quiesceCycles are called with a value of 0, the
QuiesceEvent will not be created and the Fetch stage will remain blocked.
Committed by Joel Hestness <jthestness@gmail.com>
This patch reverts part of (842f56345a42), as apparently there are
use-cases outside the main repository relying on the late setting of
the physical address.
This patch simplifies the packet, and removes the possibility of
creating a packet without a valid address and/or size. Under no
circumstances are these fields set at a later point, and thus they
really have to be provided at construction time.
The patch also fixes a case there the MinorCPU creates a packet
without a valid address and size, only to later delete it.
Cleaning up dead code. The CLREX stores zero directly to
MISCREG_LOCKFLAG and so the request flag is no longer needed. The
corresponding functionality in the cache tags is also removed.
Open up for other subclasses to BaseCache and transition to using the
explicit Cache subclass.
--HG--
rename : src/mem/cache/BaseCache.py => src/mem/cache/Cache.py
This patch serves to avoid name clashes with the classic cache. For
some reason having two 'SimObject' files with the same name creates
problems.
--HG--
rename : src/mem/ruby/structures/Cache.py => src/mem/ruby/structures/RubyCache.py
We no longer use the C library based random number generator: random().
Instead we use the C++ library provided rng. So setting the random seed for
the RubySystem class has no effect. Hence the variable and the corresponding
option are being dropped.
Currently the sequencer calls the function setMRU that updates the replacement
policy structures with the first level caches. While functionally this is
correct, the problem is that this requires calling findTagInSet() which is an
expensive function. This patch removes the calls to setMRU from the sequencer.
All controllers should now update the replacement policy on their own.
The set and the way index for a given cache entry can be found within the
AbstractCacheEntry structure. Use these indicies to update the replacement
policy structures.
Before this patch, while one could declare / define a function with default
argument values, but the actual function call would require one to specify
all the arguments. This patch changes the check for function arguments.
Now a function call needs to specify arguments that are at least as much as
those with default values and at most the total number of arguments taken
as input by the function.
Both FuncCallExprAST and MethodCallExprAST had code for checking the arguments
with which a function is being called. The patch does away with this
duplication. Now the code for checking function call arguments resides in the
Func class.
This is in preparation for adding a second arugment to the lookup
function for the CacheMemory class. The change to *.sm files was made using
the following sed command:
sed -i 's/\[\([0-9A-Za-z._()]*\)\]/.lookup(\1)/' src/mem/protocol/*.sm
The sequencer takes care of llsc accesses by calling upon functions
from the CacheMemory. This is unnecessary once the required CacheEntry object
is available. Thus some of the calls to findTagInSet() are avoided.
This patch eliminates the type Address defined by the ruby memory system.
This memory system would now use the type Addr that is in use by the
rest of the system.
Expose MessageBuffers from SLICC controllers as SimObjects that can be
manipulated in Python. This patch has numerous benefits:
1) First and foremost, it exposes MessageBuffers as SimObjects that can be
manipulated in Python code. This allows parameters to be set and checked in
Python code to avoid obfuscating parameters within protocol files. Further, now
as SimObjects, MessageBuffer parameters are printed to config output files as a
way to track parameters across simulations (e.g. buffer sizes)
2) Cleans up special-case code for responseFromMemory buffers, and aligns their
instantiation and use with mandatoryQueue buffers. These two special buffers
are the only MessageBuffers that are exposed to components outside of SLICC
controllers, and they're both slave ends of these buffers. They should be
exposed outside of SLICC in the same way, and this patch does it.
3) Distinguishes buffer-specific parameters from buffer-to-network parameters.
Specifically, buffer size, randomization, ordering, recycle latency, and ports
are all specific to a MessageBuffer, while the virtual network ID and type are
intrinsics of how the buffer is connected to network ports. The former are
specified in the Python object, while the latter are specified in the
controller *.sm files. Unlike buffer-specific parameters, which may need to
change depending on the simulated system structure, buffer-to-network
parameters can be specified statically for most or all different simulated
systems.
CacheMemory and DirectoryMemory lookup functions return pointers to entries
stored in the memory. Bring PerfectCacheMemory in line with this convention,
and clean up SLICC code generation that was in place solely to handle
references like that which was returned by PerfectCacheMemory::lookup.
The RubyCache (CacheMemory) latency parameter is only used for top-level caches
instantiated for Ruby coherence protocols. However, the top-level cache hit
latency is assessed by the Sequencer as accesses flow through to the cache
hierarchy. Further, protocol state machines should be enforcing these cache hit
latencies, but RubyCaches do not expose their latency to any existng state
machines through the SLICC/C++ interface. Thus, the RubyCache latency parameter
is superfluous for all caches. This is confusing for users.
As a step toward pushing L0/L1 cache hit latency into the top-level cache
controllers, move their latencies out of the RubyCache declarations and over to
their Sequencers. Eventually, these Sequencer parameters should be exposed as
parameters to the top-level cache controllers, which should assess the latency.
NOTE: Assessing these latencies in the cache controllers will require modifying
each to eliminate instantaneous Ruby hit callbacks in transitions that finish
accesses, which is likely a large undertaking.
The Packet::get() and Packet::set() methods both have very strange
semantics. Currently, they automatically convert between the guest
system's endianness and the host system's endianness. This behavior is
usually undesired and unexpected.
This patch introduces three new method pairs to access data:
* getLE() / setLE() - Get data stored as little endian.
* getBE() / setBE() - Get data stored as big endian.
* get(ByteOrder) / set(v, ByteOrder) - Configurable endianness
For example, a little endian device that is receiving a write request
will use teh getLE() method to get the data from the packet.
The old interface will be deprecated once all existing devices have
been ported to the new interface.
Timing generator for a pixel-based display. The timing generator is
intended for display processors driving a standard rasterized
display. The simplest possible display processor needs to derive from
this class and override the nextPixel() method to feed the display
with pixel data.
Pixels are ordered relative to the top left corner of the
display. Scan lines appear in the following order:
* Vertical Sync (starting at line 0)
* Vertical back porch
* Visible lines
* Vertical front porch
Pixel order within a scan line:
* Horizontal Sync
* Horizontal Back Porch
* Visible pixels
* Horizontal Front Porch
All events in the timing generator are automatically suspended on a
drain() request and restarted on drainResume(). This is conceptually
equivalent to clock gating when the pixel clock while the system is
draining. By gating the pixel clock, we prevent display controllers
from disturbing a memory system that is about to drain.
Add support for oscillators that can be programmed using the RealView
/ Versatile Express configuration interface. These oscillators are
typically used for things like the pixel clock in the display
controller.
The default configurations support the oscillators from a Versatile
Express motherboard (V2M-P1) with a CoreTile Express A15x2.
Add a simple DMA engine that sits behind a FIFO. This engine can be
used by devices that need to read large amounts of data (e.g., display
controllers). Most aspects of the controller, such as FIFO size,
maximum number of in-flight accesses, and maximum request sizes can be
configured.
The DMA copies blocks of data into its FIFO. Transfers are initiated
with a call to startFill() command that takes a start address and a
size. Advanced users can create a derived class that overrides the
onEndOfBlock() callback that is triggered when the last request to a
block has been issued. At this point, the DMA engine is ready to start
fetching a new block of data, potentially from a different address
range.
The DMA engine stops issuing new requests while it is draining. Care
must be taken to ensure that devices that are fed by a DMA engine are
suspended while the system is draining to avoid buffer underruns.
Split ClockedObject into two classes: Clocked that provides the basic
clock functionality, and ClockedObject that inherits from Clocked and
SimObject to provide the functionality of the old ClockedObject.
The CircleBuf class has at least one bug causing it to overwrite the
wrong elements when wrapping. The current code has a lot of unused
functionality and duplicated code. This changeset replaces the old
implementation with a new version that supports serialization and
arbitrary types in the buffer (not just char).
