mem: Add explicit Cache subclass and make BaseCache abstract
Open up for other subclasses to BaseCache and transition to using the explicit Cache subclass. --HG-- rename : src/mem/cache/BaseCache.py => src/mem/cache/Cache.py
This commit is contained in:
parent
d71a0d790d
commit
ddfa96cf45
12 changed files with 39 additions and 34 deletions
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@ -46,7 +46,7 @@ from m5.objects import *
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# starting point, and specific parameters can be overridden in the
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# specific instantiations.
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class L1Cache(BaseCache):
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class L1Cache(Cache):
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assoc = 2
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hit_latency = 2
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response_latency = 2
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@ -59,7 +59,7 @@ class L1_ICache(L1Cache):
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class L1_DCache(L1Cache):
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pass
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class L2Cache(BaseCache):
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class L2Cache(Cache):
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assoc = 8
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hit_latency = 20
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response_latency = 20
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@ -67,7 +67,7 @@ class L2Cache(BaseCache):
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tgts_per_mshr = 12
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write_buffers = 8
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class IOCache(BaseCache):
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class IOCache(Cache):
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assoc = 8
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hit_latency = 50
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response_latency = 50
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@ -76,7 +76,7 @@ class IOCache(BaseCache):
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tgts_per_mshr = 12
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forward_snoops = False
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class PageTableWalkerCache(BaseCache):
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class PageTableWalkerCache(Cache):
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assoc = 2
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hit_latency = 2
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response_latency = 2
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@ -142,7 +142,7 @@ class O3_ARM_v7a_3(DerivO3CPU):
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branchPred = O3_ARM_v7a_BP()
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# Instruction Cache
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class O3_ARM_v7a_ICache(BaseCache):
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class O3_ARM_v7a_ICache(Cache):
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hit_latency = 1
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response_latency = 1
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mshrs = 2
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@ -153,7 +153,7 @@ class O3_ARM_v7a_ICache(BaseCache):
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is_read_only = True
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# Data Cache
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class O3_ARM_v7a_DCache(BaseCache):
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class O3_ARM_v7a_DCache(Cache):
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hit_latency = 2
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response_latency = 2
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mshrs = 6
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@ -164,7 +164,7 @@ class O3_ARM_v7a_DCache(BaseCache):
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# TLB Cache
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# Use a cache as a L2 TLB
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class O3_ARM_v7aWalkCache(BaseCache):
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class O3_ARM_v7aWalkCache(Cache):
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hit_latency = 4
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response_latency = 4
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mshrs = 6
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@ -176,7 +176,7 @@ class O3_ARM_v7aWalkCache(BaseCache):
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is_read_only = True
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# L2 Cache
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class O3_ARM_v7aL2(BaseCache):
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class O3_ARM_v7aL2(Cache):
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hit_latency = 12
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response_latency = 12
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mshrs = 16
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@ -152,9 +152,9 @@ for t, m in zip(testerspec, multiplier):
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numtesters += t * m
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# Define a prototype L1 cache that we scale for all successive levels
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proto_l1 = BaseCache(size = '32kB', assoc = 4,
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hit_latency = 1, response_latency = 1,
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tgts_per_mshr = 8)
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proto_l1 = Cache(size = '32kB', assoc = 4,
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hit_latency = 1, response_latency = 1,
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tgts_per_mshr = 8)
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if options.blocking:
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proto_l1.mshrs = 1
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@ -175,9 +175,9 @@ else:
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sys.exit(1)
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# Define a prototype L1 cache that we scale for all successive levels
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proto_l1 = BaseCache(size = '32kB', assoc = 4,
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hit_latency = 1, response_latency = 1,
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tgts_per_mshr = 8)
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proto_l1 = Cache(size = '32kB', assoc = 4,
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hit_latency = 1, response_latency = 1,
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tgts_per_mshr = 8)
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if options.blocking:
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proto_l1.mshrs = 1
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@ -137,7 +137,7 @@ class Water_spatial(LiveProcess):
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# Base L1 Cache Definition
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# ====================
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class L1(BaseCache):
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class L1(Cache):
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latency = options.l1latency
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mshrs = 12
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tgts_per_mshr = 8
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@ -146,7 +146,7 @@ class L1(BaseCache):
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# Base L2 Cache Definition
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# ----------------------
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class L2(BaseCache):
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class L2(Cache):
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latency = options.l2latency
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mshrs = 92
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tgts_per_mshr = 16
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@ -158,7 +158,7 @@ class Water_spatial(LiveProcess):
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# Base L1 Cache Definition
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# ====================
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class L1(BaseCache):
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class L1(Cache):
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latency = options.l1latency
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mshrs = 12
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tgts_per_mshr = 8
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@ -167,7 +167,7 @@ class L1(BaseCache):
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# Base L2 Cache Definition
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# ----------------------
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class L2(BaseCache):
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class L2(Cache):
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latency = options.l2latency
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mshrs = 92
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tgts_per_mshr = 16
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@ -37,6 +37,7 @@
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Nathan Binkert
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# Andreas Hansson
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from m5.params import *
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from m5.proxy import *
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@ -46,6 +47,7 @@ from Tags import *
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class BaseCache(MemObject):
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type = 'BaseCache'
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abstract = True
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cxx_header = "mem/cache/base.hh"
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size = Param.MemorySize("Capacity")
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@ -81,3 +83,7 @@ class BaseCache(MemObject):
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"Address range for the CPU-side port (to allow striping)")
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system = Param.System(Parent.any, "System we belong to")
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class Cache(BaseCache):
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type = 'Cache'
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cxx_header = 'mem/cache/cache.hh'
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2
src/mem/cache/SConscript
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2
src/mem/cache/SConscript
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@ -30,7 +30,7 @@
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Import('*')
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SimObject('BaseCache.py')
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SimObject('Cache.py')
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Source('base.cc')
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Source('cache.cc')
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12
src/mem/cache/base.cc
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12
src/mem/cache/base.cc
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@ -65,13 +65,13 @@ BaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name,
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{
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}
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BaseCache::BaseCache(const Params *p)
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BaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size)
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: MemObject(p),
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cpuSidePort(nullptr), memSidePort(nullptr),
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mshrQueue("MSHRs", p->mshrs, 4, p->demand_mshr_reserve, MSHRQueue_MSHRs),
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writeBuffer("write buffer", p->write_buffers, p->mshrs+1000, 0,
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MSHRQueue_WriteBuffer),
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blkSize(p->system->cacheLineSize()),
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blkSize(blk_size),
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lookupLatency(p->hit_latency),
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forwardLatency(p->hit_latency),
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fillLatency(p->response_latency),
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@ -774,11 +774,3 @@ BaseCache::regStats()
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;
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}
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BaseCache *
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BaseCacheParams::create()
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{
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assert(tags);
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return new Cache(this);
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}
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3
src/mem/cache/base.hh
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3
src/mem/cache/base.hh
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@ -473,8 +473,7 @@ class BaseCache : public MemObject
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virtual void regStats();
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public:
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typedef BaseCacheParams Params;
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BaseCache(const Params *p);
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BaseCache(const BaseCacheParams *p, unsigned blk_size);
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~BaseCache() {}
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virtual void init();
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11
src/mem/cache/cache.cc
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11
src/mem/cache/cache.cc
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@ -63,8 +63,8 @@
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#include "mem/cache/prefetch/base.hh"
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#include "sim/sim_exit.hh"
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Cache::Cache(const Params *p)
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: BaseCache(p),
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Cache::Cache(const CacheParams *p)
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: BaseCache(p, p->system->cacheLineSize()),
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tags(p->tags),
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prefetcher(p->prefetcher),
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doFastWrites(true),
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@ -2382,6 +2382,13 @@ CpuSidePort::CpuSidePort(const std::string &_name, Cache *_cache,
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{
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}
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Cache*
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CacheParams::create()
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{
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assert(tags);
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return new Cache(this);
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}
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///////////////
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//
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// MemSidePort
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3
src/mem/cache/cache.hh
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3
src/mem/cache/cache.hh
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@ -57,6 +57,7 @@
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#include "mem/cache/blk.hh"
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#include "mem/cache/mshr.hh"
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#include "mem/cache/tags/base.hh"
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#include "params/Cache.hh"
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#include "sim/eventq.hh"
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//Forward decleration
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@ -419,7 +420,7 @@ class Cache : public BaseCache
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public:
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/** Instantiates a basic cache object. */
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Cache(const Params *p);
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Cache(const CacheParams *p);
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/** Non-default destructor is needed to deallocate memory. */
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virtual ~Cache();
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