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Author SHA1 Message Date
Korey Sewell
5f608dd2e9 inorder: squash and trap behind a tlb fault 2011-06-19 21:43:39 -04:00
Korey Sewell
e0e387c2a9 inorder: stall stores on store conditionals & compare/swaps 2011-06-19 21:43:39 -04:00
Korey Sewell
f268d7d004 alpha: make hwrei a control inst 
this always changes the PC and is basically an impromptu branch instruction. why
not speculate on this instead of always be forced to mispredict/squash after the
hwrei gets resolved?

The InOrder model needs this marked as "isControl" so it knows to update the PC
after the ALU executes it. If this isnt marked as control, then it's going to
force the model to check the PC of every instruction at commit (what O3 does?),
and that would be a wasteful check for a very high percentage of instructions.
 2011-06-19 21:43:39 -04:00
Korey Sewell
e8b7df072b inorder: make InOrder CPU FS compilable/visible 
make syscall a SE mode only functionality
copy over basic FS functions (hwrei) to make FS compile
 2011-06-19 21:43:39 -04:00
Korey Sewell
d71b95d84d inorder: remove memdep tracking for default pipeline 
speculative load/store pipelines can reenable this
 2011-06-19 21:43:39 -04:00
Korey Sewell
b72bdcf4f8 inorder: fetchBuffer tracking 
calculate blocks in use for the fetch buffer to figure out how many total blocks
are pending
 2011-06-19 21:43:39 -04:00
Korey Sewell
4d4c7d79d0 inorder: redefine DynInst FP result type 
Sharing the FP value w/the integer values was giving inconsistent results esp. when
their is a 32-bit integer register matched w/a 64-bit float value
 2011-06-19 21:43:38 -04:00
Korey Sewell
db8b1e4b78 inorder: treat SE mode syscalls as a trapping instruction 
define a syscallContext to schedule the syscall and then use syscall() to actually perform the action
 2011-06-19 21:43:38 -04:00
Korey Sewell
c95fe261ab inorder: bug in mdu 
segfault was caused by squashed multiply thats in the process of an event.
use isProcessing flag to handle this and cleanup the MDU code
 2011-06-19 21:43:38 -04:00
Korey Sewell
4c979f9325 inorder: optionally track faulting instructions 2011-06-19 21:43:38 -04:00
Korey Sewell
22ba1718c4 inorder: cleanup events in resource pool 
remove events in the resource pool that can be called from the CPU event, since the CPU
event is scheduled at the same time at the resource pool event.
----
Also, match the resPool event function names to the cpu event function names
----
 2011-06-19 21:43:38 -04:00
Korey Sewell
e8082a28c8 inorder: don't stall after stores 
once a ST is sent off, it's OK to keep processing, however it's a little more
complicated to handle the packet acknowledging the store is completed
 2011-06-19 21:43:38 -04:00
Korey Sewell
379c23199e inorder: don't stall after stores 
once a ST is sent off, it's OK to keep processing, however it's a little more
complicated to handle the packet acknowledging the store is completed
 2011-06-19 21:43:37 -04:00
Korey Sewell
4c9ad53cc5 inorder: remove decode squash 
also, cleanup comments for gem5.fast compilation
 2011-06-19 21:43:37 -04:00
Korey Sewell
a444133e73 inorder: support for compare and swap insts 
dont treat read() and write() fields as mut. exclusive
 2011-06-19 21:43:37 -04:00
Korey Sewell
89d0f95bf0 inorder: branch predictor update 
only update BTB on a taken branch and update branch predictor w/pcstate from instruction
---
only pay attention to branch predictor updates if the the inst. is in fact a branch
 2011-06-19 21:43:37 -04:00
Korey Sewell
479195d4cf inorder: priority for grad/squash events 
define separate priority resource pool squash and graduate events
 2011-06-19 21:43:37 -04:00
Korey Sewell
71018f5e8b inorder: remove stalls on trap squash 2011-06-19 21:43:37 -04:00
Korey Sewell
34b2500f09 inorder: no dep. tracking for zero reg 
this causes forwarding a bad value register value
 2011-06-19 21:43:37 -04:00
Korey Sewell
d02fa0f6b6 imported patch recoverPCfromTrap 2011-06-19 21:43:37 -04:00
Korey Sewell
264e8178ff imported patch squash_from_next_stage 2011-06-19 21:43:36 -04:00
Korey Sewell
f0f33ae2b9 inorder: add flatDestReg member to dyninst 
use it in reg. dep. tracking
 2011-06-19 21:43:36 -04:00
Korey Sewell
555bd4d842 inorder: update event priorities 
dont use offset to calculate this but rather an enum
that can be updated
 2011-06-19 21:43:36 -04:00
Korey Sewell
7dea79535c inorder: implement trap handling 2011-06-19 21:43:36 -04:00
Korey Sewell
061b369d28 inorder: cleanup intercomm. structs/squash info 2011-06-19 21:43:35 -04:00
Korey Sewell
b195da9345 inorder: use setupSquash for misspeculation 
implement a clean interface to handle branch misprediction and eventually all pipeline
flushing
 2011-06-19 21:43:35 -04:00
Korey Sewell
d5d4e47f76 sparc: init. cache state in TLB 
valgrind complains and its a potential source of instability, so go ahead
and set it to 0 to start
 2011-06-19 21:43:35 -04:00
Korey Sewell
73cfab8b23 inorder: DynInst handling of stores for big-endian ISAs 
The DynInst was not performing the host-to-guest translation
which ended up breaking stores for SPARC
 2011-06-19 21:43:35 -04:00
Korey Sewell
4f34bc8b7b inorder: make marking of dest. regs an explicit request 
formerly, this was implicit when you accessed the execution unit
or the use-def unit but it's better that this just be something
that a user can specify.
 2011-06-19 21:43:35 -04:00
Korey Sewell
946b0ed4f4 inorder: simplify handling of split accesses 2011-06-19 21:43:35 -04:00
Korey Sewell
1a6d25dc47 inorder: addtl functionaly for inst. skeds 
add find and end functions for inst. schedules
that can search by stage number
 2011-06-19 21:43:35 -04:00
Korey Sewell
8b54858831 inorder: register file stats 
keep stats for int/float reg file usage instead
of aggregating across reg file types
 2011-06-19 21:43:34 -04:00
Korey Sewell
085f30ff9c inorder: scheduling for nonspec insts 
make handling of speculative and nonspeculative insts
more explicit
 2011-06-19 21:43:34 -04:00
Korey Sewell
3c417ea23a inorder: find register dependencies "lazily" 
Architectures like SPARC need to read the window pointer
in order to figure out it's register dependence. However,
this may not get updated until after an instruction gets
executed, so now we lazily detect the register dependence
in the EXE stage (execution unit or use_def). This
makes sure we get the mapping after the most current change.
 2011-06-19 21:43:34 -04:00
Korey Sewell
bd67ee9852 inorder: assert on macro-ops 
provide a sanity check for someone coding
a new architecture
 2011-06-19 21:43:34 -04:00
Korey Sewell
ee7062d94d inorder: handle faults at writeback stage 
call trap function when a fault is received
 2011-06-19 21:43:34 -04:00
Korey Sewell
17f5749dbb inorder: ISA-zero reg handling 
ignore writes to the ISA zero register
 2011-06-19 21:43:34 -04:00
Korey Sewell
2a59fcfbe9 inorder: update support for branch delay slots 2011-06-19 21:43:34 -04:00
Korey Sewell
d4b4ef1324 inorder: inst. iterator cleanup 
get rid of accessing iterators (for instructions) by reference
 2011-06-19 21:43:34 -04:00
Korey Sewell
b43eeaf2e2 cpus/isa: add a != operator for pcstate 2011-06-19 21:43:33 -04:00
Korey Sewell
e2f9266dbf inorder: update bpred code 
clean up control flow to make it easier to understand
 2011-06-19 21:43:33 -04:00
Korey Sewell
6df6365095 inorder: add types for dependency checks 2011-06-19 21:43:33 -04:00
Korey Sewell
19e3eb2915 inorder: use flattenIdx for reg indexing 
- also use "threadId()" instead of readTid() everywhere
- this will help support more complex ISA indexing
 2011-06-19 21:43:33 -04:00
Korey Sewell
b2e5152e16 simple-thread: give a name() function for debugging w/the SimpleThread object 2011-06-19 21:43:33 -04:00
Korey Sewell
76c60c5f93 inorder: use m5_hash_map for skedCache 
since we dont care about if the cache of instruction schedules is sorted or not,
then the hash map should be faster
 2011-06-19 21:43:33 -04:00
Ali Saidi
0b7ca66919 ARM: Cleanup m5ops usage of r0 and r1 a bit. 2011-06-17 12:20:11 -05:00
Gedare Bloom
3f1f16703d ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA. 2011-06-17 12:20:10 -05:00
Ali Saidi
8b4307f8d8 ARM: Handle case where new TLB size is different from previous TLB size. 
After a checkpoint we need to make sure that we restore the right
number of entries.
 2011-06-16 15:08:12 -05:00
Chander Sudanthi
9fe3610b32 ARM: Fix memset on TLB flush and initialization 
Instead of clearing the entire TLB on initialization and flush, the code was
clearing only one element.  This patch corrects the memsets in the init and
flush routines.
 2011-06-16 15:08:11 -05:00
Nilay Vaish
8bf92329ee Ruby: Correct set LONG_BITS and INDEX_SHIFT in class Set. 
The code for Set class was written under the assumption that
std::numeric_limits<long>::digits returns the number of bits used for
data type long, which was presumed to be either 32 or 64. But return value
is actually one less, that is, it is either 31 or 63. The value is now
being incremented by 1 so as to correctly set it.
 2011-06-14 19:51:44 -05:00