Commit graph

7554 commits

Author SHA1 Message Date
Brad Beckmann
6a4f99899b ruby: Resurrected Ruby's deterministic tests
Added the request series and invalidate deterministic tests as new cpu models
and removed the no longer needed ruby tests

--HG--
rename : configs/example/rubytest.py => configs/example/determ_test.py
rename : src/mem/ruby/tester/DetermGETXGenerator.cc => src/cpu/directedtest/DirectedGenerator.cc
rename : src/mem/ruby/tester/DetermGETXGenerator.hh => src/cpu/directedtest/DirectedGenerator.hh
rename : src/mem/ruby/tester/DetermGETXGenerator.cc => src/cpu/directedtest/InvalidateGenerator.cc
rename : src/mem/ruby/tester/DetermGETXGenerator.hh => src/cpu/directedtest/InvalidateGenerator.hh
rename : src/cpu/rubytest/RubyTester.cc => src/cpu/directedtest/RubyDirectedTester.cc
rename : src/cpu/rubytest/RubyTester.hh => src/cpu/directedtest/RubyDirectedTester.hh
rename : src/mem/ruby/tester/DetermGETXGenerator.cc => src/cpu/directedtest/SeriesRequestGenerator.cc
rename : src/mem/ruby/tester/DetermGETXGenerator.hh => src/cpu/directedtest/SeriesRequestGenerator.hh
2010-08-20 11:46:13 -07:00
Brad Beckmann
984adf198a ruby: Updated MOESI_hammer L2 latency behavior
Previously, the MOESI_hammer protocol calculated the same latency for L1 and
L2 hits.  This was because the protocol was written using the old ruby
assumption that L1 hits used the sequencer fast path.  Since ruby no longer
uses the fast-path, the protocol delays L2 hits by placing them on the
trigger queue.
2010-08-20 11:46:13 -07:00
Brad Beckmann
29c45ccd23 ruby: Reduced ruby latencies
The previous slower ruby latencies created a mismatch between the faster M5
cpu models and the much slower ruby memory system.  Specifically smp
interrupts were much slower and infrequent, as well as cpus moving in and out
of spin locks.  The result was many cpus were idle for large periods of time.

These changes fix the latency mismatch.
2010-08-20 11:46:12 -07:00
Brad Beckmann
8e5c441a54 ruby: fix ruby llsc support to sync sc outcomes
Added support so that ruby can determine the outcome of store conditional
operations and reflect that outcome to M5 physical memory and cpus.
2010-08-20 11:46:12 -07:00
Brad Beckmann
54d76f0ce5 ruby: Fixed L2 cache miss profiling
Fixed L2 cache miss profiling for the MOESI_CMP_token protocol
2010-08-20 11:46:12 -07:00
Brad Beckmann
a3b4b9b3e3 ruby: Added bcast msg profiling to hammer and token 2010-08-20 11:46:12 -07:00
Brad Beckmann
1f82eb1a03 ruby: Added consolidated network msg stats 2010-08-20 11:46:12 -07:00
Brad Beckmann
4b4e725921 ruby: Reincarnated the responding machine profiling
This patch adds back to ruby the capability to understand the response time
for messages that hit in different levels of the cache heirarchy.
Specifically add support for the MI_example, MOESI_hammer, and MOESI_CMP_token
protocols.
2010-08-20 11:46:12 -07:00
Brad Beckmann
9fb4381ddc MOESI_CMP_token: Fixed dma persistent lockdown bugs 2010-08-20 11:46:12 -07:00
Brad Beckmann
808701a10c memtest: Memtester support for DMA
This patch adds DMA testing to the Memtester and is inherits many changes from
Polina's old tester_dma_extension patch.  Since Ruby does not work in atomic
mode, the atomic mode options are removed.
2010-08-20 11:46:12 -07:00
Brad Beckmann
64b2205992 ruby: Added ruby_request_type ostream def to libruby.hh 2010-08-20 11:46:12 -07:00
Brad Beckmann
d694cc1384 slicc: Consolidated the protocol stats printing
Created a separate ProfileDumper that consolidates the generated stats for
each controller of a certain type.
2010-08-20 11:46:12 -07:00
Brad Beckmann
10e25cb1d0 config: Improve ruby simobject names
This patch attaches ruby objects to the system before the topology is
created so that their simobject names read their meaningful variable
names instead of their topology name.
2010-08-20 11:46:11 -07:00
Brad Beckmann
09854be558 config: Added the topology description to m5 config.ini 2010-08-20 11:46:11 -07:00
Brad Beckmann
c7bd896448 ruby: added token broadcast config params to cmd options 2010-08-20 11:46:11 -07:00
Brad Beckmann
5c801090a3 config: reorganized how ruby specifies command-line options 2010-08-20 11:44:09 -07:00
Brad Beckmann
eb1e5636e3 ruby: Fixed printout when Sequencer detects a deadlock 2010-08-20 11:41:35 -07:00
Brad Beckmann
d7d73680c4 MESI_CMP_directory: bug fix for old PUTX requests 2010-08-20 11:41:35 -07:00
Brad Beckmann
7816d0d12b config: moved python protocol config files
Moved the python protocol config files back to their original location to avoid
addToPath calls.

--HG--
rename : configs/ruby/protocols/MESI_CMP_directory.py => configs/ruby/MESI_CMP_directory.py
rename : configs/ruby/protocols/MI_example.py => configs/ruby/MI_example.py
rename : configs/ruby/protocols/MOESI_CMP_directory.py => configs/ruby/MOESI_CMP_directory.py
rename : configs/ruby/protocols/MOESI_CMP_token.py => configs/ruby/MOESI_CMP_token.py
rename : configs/ruby/protocols/MOESI_hammer.py => configs/ruby/MOESI_hammer.py
2010-08-20 11:41:35 -07:00
Steve Reinhardt
e0754c0f6c misc: add some AMD copyright notices
Meant to add these with the previous batch of csets.
2010-08-17 05:49:05 -07:00
Steve Reinhardt
164a211f10 x86: minor checkpointing bug fixes 2010-08-17 05:20:39 -07:00
Steve Reinhardt
f064aa3060 sim: revamp unserialization procedure
Replace direct call to unserialize() on each SimObject with a pair of
calls for better control over initialization in both ckpt and non-ckpt
cases.

If restoring from a checkpoint, loadState(ckpt) is called on each
SimObject.  The default implementation simply calls unserialize() if
there is a corresponding checkpoint section, so we get backward
compatibility for existing objects.  However, objects can override
loadState() to get other behaviors, e.g., doing other programmed
initializations after unserialize(), or complaining if no checkpoint
section is found.  (Note that the default warning for a missing
checkpoint section is now gone.)

If not restoring from a checkpoint, we call the new initState() method
on each SimObject instead.  This provides a hook for state
initializations that are only required when *not* restoring from a
checkpoint.

Given this new framework, do some cleanup of LiveProcess subclasses
and X86System, which were (in some cases) emulating initState()
behavior in startup via a local flag or (in other cases) erroneously
doing initializations in startup() that clobbered state loaded earlier
by unserialize().
2010-08-17 05:17:06 -07:00
Steve Reinhardt
2519d116c9 sim: fold checkpoint restore code into instantiate()
The separate restoreCheckpoint() call is gone; just pass
the checkpoint dir as an optional arg to instantiate().
This change is a precursor to some more extensive
reworking of the startup code.
2010-08-17 05:17:06 -07:00
Steve Reinhardt
cfaddd5fd3 configs: clean up checkpoint code in Simulation.py
Small change to clean up some redundant code.
Should not have any functional impact.
2010-08-17 05:17:06 -07:00
Steve Reinhardt
5577048bcf test: Update stats for python object iteration.
Small changes in tests with data races due to new object creation
order.
2010-08-17 05:14:03 -07:00
Steve Reinhardt
c2e1458746 sim: clean up child handling
The old code for handling SimObject children was kind of messy,
with children stored both in _values and _children, and
inconsistent and potentially buggy handling of SimObject
vectors.  Now children are always stored in _children, and
SimObject vectors are consistently handled using the
SimObjectVector class.

Also, by deferring the parenting of SimObject-valued parameters
until the end (instead of doing it at assignment), we eliminate
the hole where one could assign a vector of SimObjects to a
parameter then append to that vector, with the appended objects
never getting parented properly.

This patch induces small stats changes in tests with data races
due to changes in the object creation & initialization order.
The new code does object vectors in order and so should be more
stable.
2010-08-17 05:11:00 -07:00
Steve Reinhardt
5ea906ba16 sim: move iterating over SimObjects into Python. 2010-08-17 05:08:50 -07:00
Steve Reinhardt
c2cce96a0b sim: fail on implicit creation of orphans via ports
Orphan SimObjects (not in the config hierarchy) could get
created implicitly if they have a port connection to a SimObject
that is in the hierarchy.  This means that there are objects on
the C++ SimObject list (created via the C++ SimObject
constructor call) that are unknown to Python and will get
skipped if we walk the hierarchy from the Python side (as we are
about to do).  This patch detects this situation and prints an
error message.

Also fix the rubytester config script which happened to rely on
this behavior.
2010-08-17 05:06:22 -07:00
Steve Reinhardt
1fbe466345 sim: make Python Root object a singleton
Enforce that the Python Root SimObject is instantiated only
once.  The C++ Root object already panics if more than one is
created.  This change avoids the need to track what the root
object is, since it's available from Root.getInstance() (if it
exists).  It's now redundant to have the user pass the root
object to functions like instantiate(), checkpoint(), and
restoreCheckpoint(), so that arg is gone.  Users who use
configs/common/Simulate.py should not notice.
2010-08-17 05:06:22 -07:00
Steve Reinhardt
0f8b5afd7a tests: update reference config.ini files for previous cset
Rename 'responder_set' to 'use_default_range'.
2010-08-17 05:06:22 -07:00
Steve Reinhardt
0685ae7a2d bus: clean up default responder code.
Clean up some minor things left over from the default responder
change in rev 9af6fb59752f.  Mostly renaming the 'responder_set'
param to 'use_default_range' to actually reflect what it does...
old name wasn't that descriptive in the first place, but now
it really doesn't make sense at all.

Also got rid of the bogus obsolete assignment to 'bus.responder'
which used to be a parameter but now is interpreted as an
implicit child assignment, and which was giving me problems in
the config restructuring to come.  (A good argument for not
allowing implicit child assignments, IMO, but that's water under
the bridge, I'm afraid.)

Also moved the Bus constructor to the .cc file since that's
where it should have been all along.
2010-08-17 05:06:21 -07:00
Gabe Black
c4ba6967a5 Inorder: Fix compilation of m5.fast.
printMemData is only used in DPRINTFs. If those are removed by compiling
m5.fast, that function is unused, gcc generates a warning, that gets turned
into an error, and the build fails. This change surrounds the function
definition with #if TRACING_ON so it only gets compiled in if the DPRINTFs do
to.
2010-08-14 01:00:45 -07:00
Gabe Black
961aafc044 Merge with head. 2010-08-13 06:16:30 -07:00
Gabe Black
aa8c6e9c95 CPU: Add readBytes and writeBytes functions to the exec contexts. 2010-08-13 06:16:02 -07:00
Gabe Black
65dbcc6ea1 InOrder: Clean up some DPRINTFs that print data sent to/from the cache. 2010-08-13 06:16:00 -07:00
Gabe Black
52a90a5998 CPU: Tidy up endianness handling for mmapped "IPR"s. 2010-08-13 06:10:45 -07:00
Joel Hestness
73d9a51835 util/m5/m5.c: ensure readfile() buffer pages are in page table
(and marked dirty, in case that matters) by touching them beforehand
2010-08-12 17:16:04 -07:00
Joel Hestness
53c241fc16 TimingSimpleCPU: fix NO_ACCESS memory op handling
When a request is NO_ACCESS (x86 CDA microinstruction), the memory op
doesn't go to the cache, so TimingSimpleCPU::completeDataAccess needs
to handle the case where the current status of the CPU is Running
and not DcacheWaitResponse or DTBWaitResponse
2010-08-12 17:16:02 -07:00
Nathan Binkert
2e9e75447a None, not none 2010-08-08 22:57:16 -07:00
Steve Reinhardt
545a6fcd04 .hgignore: added src/doxygen 2010-07-27 20:00:38 -07:00
Ali Saidi
1b73376b0b ARM: Add regression tests 2010-07-27 01:03:44 -04:00
Timothy M. Jones
97d245278d Power: The condition register should be set or cleared upon a system call
return to indicate success or failure.
2010-07-22 18:54:37 +01:00
Timothy M. Jones
607f519800 LSQ Unit: After deleting part of a split request, set it to NULL so that it
isn't accidentally deleted again later (causing a segmentation fault).
2010-07-22 18:54:37 +01:00
Timothy M. Jones
28a5ea3f99 Port: Only indicate that a SimpleTimingPort is drained if its send event is
not scheduled, as well as the transmit list being empty.
2010-07-22 18:54:37 +01:00
Timothy M. Jones
e50a880297 O3CPU: Fix a bug where stores in the cpu where never marked as split. 2010-07-22 18:52:02 +01:00
Timothy M. Jones
0d301ca4c4 Syscall: Don't close the simulator's standard file descriptors. 2010-07-22 18:47:52 +01:00
Timothy M. Jones
9a3533ec84 O3CPU: O3's tick event gets squashed when it is switched out. When repeatedly
switching between O3 and another CPU, O3's tick event might still be scheduled
in the event queue (as squashed).  Therefore, check for a squashed tick event
as well as a non-scheduled event when taking over from another CPU and deal
with it accordingly.
2010-07-22 18:47:43 +01:00
Timothy M. Jones
8c76715979 Power: Provide a utility function to copy registers from one thread context
to another in the Power ISA.
2010-07-22 18:47:03 +01:00
Nathan Binkert
21bf6ff101 stats: unify the two stats distribution type better 2010-07-21 18:54:53 -07:00
Nathan Binkert
2a1309f213 stats: cleanup a few small problems in stats 2010-07-21 15:53:53 -07:00