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O3CPU: Fix a bug where stores in the cpu where never marked as split.

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Timothy M. Jones 2010-07-22 18:52:02 +01:00
parent 0d301ca4c4
commit e50a880297
1 changed files with 6 additions and 0 deletions
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6
src/cpu/o3/lsq_unit.hh
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@ -822,6 +822,12 @@ LSQUnit<Impl>::write(Request *req, Request *sreqLow, Request *sreqHigh,
storeQueue[store_idx].sreqLow = sreqLow;
storeQueue[store_idx].sreqHigh = sreqHigh;
storeQueue[store_idx].size = sizeof(T);
// Split stores can only occur in ISAs with unaligned memory accesses. If
// a store request has been split, sreqLow and sreqHigh will be non-null.
if (TheISA::HasUnalignedMemAcc && sreqLow) {
storeQueue[store_idx].isSplit = true;
}
assert(sizeof(T) <= sizeof(storeQueue[store_idx].data));
T gData = htog(data);