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TimingSimpleCPU: fix NO_ACCESS memory op handling

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When a request is NO_ACCESS (x86 CDA microinstruction), the memory op
doesn't go to the cache, so TimingSimpleCPU::completeDataAccess needs
to handle the case where the current status of the CPU is Running
and not DcacheWaitResponse or DTBWaitResponse
This commit is contained in:
Joel Hestness 2010-08-12 17:16:02 -07:00
parent 2e9e75447a
commit 53c241fc16
1 changed files with 2 additions and 1 deletions
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3
src/cpu/simple/timing.cc
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@ -868,6 +868,8 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
// received a response from the dcache: complete the load or store
// instruction
assert(!pkt->isError());
assert(_status == DcacheWaitResponse || _status == DTBWaitResponse ||
pkt->req->getFlags().isSet(Request::NO_ACCESS));
numCycles += tickToCycles(curTick - previousTick);
previousTick = curTick;
@ -897,7 +899,6 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
}
}
assert(_status == DcacheWaitResponse || _status == DTBWaitResponse);
_status = Running;
Fault fault = curStaticInst->completeAcc(pkt, this, traceData);