Merge with head.

src/cpu/simple/timing.cc

@@ -891,6 +891,8 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
     // received a response from the dcache: complete the load or store
     // instruction
     assert(!pkt->isError());
+    assert(_status == DcacheWaitResponse || _status == DTBWaitResponse ||
+           pkt->req->getFlags().isSet(Request::NO_ACCESS));
 
     numCycles += tickToCycles(curTick - previousTick);
     previousTick = curTick;
@@ -920,7 +922,6 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
         }
     }
 
-    assert(_status == DcacheWaitResponse || _status == DTBWaitResponse);
     _status = Running;
 
     Fault fault = curStaticInst->completeAcc(pkt, this, traceData);

util/m5/m5.c

@@ -65,6 +65,11 @@ read_file(int dest_fid)
     int offset = 0;
     int len;
 
+    // Touch all buffer pages to ensure they are mapped in the
+    // page table. This is required in the case of X86_FS, where
+    // Linux does demand paging.
+    memset(buf, 0, sizeof(buf));
+
     while ((len = m5_readfile(buf, sizeof(buf), offset)) > 0) {
         write(dest_fid, buf, len);
         offset += len;