Commit graph

128 commits

Author SHA1 Message Date
Ali Saidi
cb172d0332 Get SPARC to the point that it starts running. Add ability to load the ROM bin files, cleanup lockstep printing a bit
Since we don't have a platform yet, you need to comment out the default responder stuff in Bus.py to make it work.

SConstruct:
    Add TARGET_ISA to the list of environment variables that end up in the build_env for python
configs/common/FSConfig.py:
    add a simple SPARC system to being testing with, you'll need to change makeLinuxAlphaSystem to makeSparcSystem in fs.py for now
src/SConscript:
    add a raw file object, at least until we get more info about how to compile openboot properly
src/arch/sparc/system.cc:
src/arch/sparc/system.hh:
    add parameters for ROM files (OBP/Reset/Hypervisor), a ROM, load files into ROM
src/base/loader/object_file.cc:
src/base/loader/object_file.hh:
    add option to try raw when nothing works
src/cpu/exetrace.cc:
    cleanup lockstep printing a little bit
src/cpu/m5legion_interface.h:
    change the instruction to be 32 bits because it is
src/mem/physical.cc:
    fix assert that doesn't work if memory starts somewhere above 0
src/python/m5/objects/BaseCPU.py:
    Add if statement to choose between sparc tlbs and alpha tlbs
src/python/m5/objects/System.py:
    Add a sparc system that sets the rom addresses correctly
src/python/m5/params.py:
    add the ability to add Addr() together

--HG--
extra : convert_revision : bbbd8a56134f2dda2728091f740e2f7119b0c4af
2006-11-09 18:22:46 -05:00
Lisa Hsu
64c0d82dec simplify maxtick parsing in both the python and the c++.
configs/common/Simulation.py:
    simplify maxtick code a little bit - instead of checking for -1, just set it at MaxTick.
src/python/m5/__init__.py:
    make a new m5 param called MaxTick.
src/sim/host.hh:
    fix the M5 def. of MaxTick
src/sim/main.cc:
    Simplify the MaxTick/num_cycles parsing within main.cc

--HG--
extra : convert_revision : f800addfbc1323591c2e05b892276b439b671668
2006-11-08 15:05:23 -05:00
Kevin Lim
344f72dd62 Remove mem parameter. Should have been removed earlier.
src/python/m5/objects/BaseCPU.py:
    These parameters should have been removed in an earlier push.

--HG--
extra : convert_revision : 781b39ca370361e9568b1af0be96ff5848b1f3f4
2006-11-08 13:04:36 -05:00
Kevin Lim
e174ec1815 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix

--HG--
extra : convert_revision : 29426cebe81ac077c1a83f50e914ff6955ce81d4
2006-11-08 11:41:10 -05:00
Ali Saidi
f7a35c33d7 add code to operate in lockstep with legion
src/python/m5/main.py:
    add option to operate in lockstep with legion

--HG--
extra : convert_revision : 2cc90ec0cf7e8d028ee813c2034a77415671a628
2006-11-07 15:51:37 -05:00
Kevin Lim
ea5df46882 Fix error message.
--HG--
extra : convert_revision : 7ac0f40595c89b0d9352e82e447d25380b038408
2006-11-07 15:45:03 -05:00
Kevin Lim
244e0c884c Remove hack by setting configuration better.
src/dev/isa_fake.cc:
src/dev/isa_fake.hh:
    No need for specialized init() function any more.
src/python/m5/objects/Tsunami.py:
    Override responder when set by user.  This avoids having bus.responder floating around and not doing anything when the user has specified their own default responder.

--HG--
extra : convert_revision : c547daf15b23a889c98e62bfd53c293c85d7a041
2006-11-07 14:24:31 -05:00
Ali Saidi
bf3223d7ce delete pcifake, tsunamifake. Combine BadAddr/IsaFake into one
src/SConscript:
    remove pcifake and tsunami fake from sconscript
src/dev/isa_fake.cc:
src/dev/isa_fake.hh:
    combine badaddr and isa fake into one
src/python/m5/objects/Pci.py:
    remove pcifake
src/python/m5/objects/Tsunami.py:
    make badaddr derive from isafake

--HG--
extra : convert_revision : 91470db60aa1de6b85827304e27bd3414cc9d8d1
2006-11-06 16:24:25 -05:00
Kevin Lim
45363ea658 Have bus use the BadAddress device to handle bad addresses. The O3 CPU should be able to boot into Linux with caches on after this change.
src/mem/bus.cc:
src/mem/bus.hh:
    Bus now will be setup with a default responder, unless the user overrides it.  This default responder should return BadAddress if no matching port is found.
src/python/m5/objects/Bus.py:
    Bus now has a default responder for FS mode if the user doesn't override it.  It returns BadAddress if no matching port is found.
src/python/m5/objects/Tsunami.py:
    Add bad address device.  Also record when the user has specified their own default responder.

--HG--
extra : convert_revision : 59070477ae313ee711b2d59baa2369c9a91c5b85
2006-11-02 15:20:37 -05:00
Ali Saidi
0f98905ecc Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem.head

--HG--
extra : convert_revision : 4db140e6e8408b3ed39da327515b8e88a2701e6b
2006-10-24 12:59:19 -04:00
Lisa Hsu
764f27a0c9 Merge zizzer:/bk/newmem
into  zed.eecs.umich.edu:/z/hsul/work/m5/newmem

--HG--
extra : convert_revision : bb58679e101570d50c040519fb08ffbabfee7416
2006-10-23 18:46:05 -04:00
Lisa Hsu
4da3938ed9 get rid of the "resume" step at the end of changeToTiming/Atomic because this will cause an assertion when you do the CPU switch. instead, push the responsibility of the resume upwards towards the user - documented in se.py and fs.py so it should be ok.
--HG--
extra : convert_revision : 7530cf140844e18cc26df80057f8760f29ec952b
2006-10-23 18:45:30 -04:00
Ron Dreslinski
28e9641c2c Use fixPacket function everywhere.
Fix fixPacket assert function.
Stop timing port from forwarding the request if a response was found in its queue on a read.

src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/python/m5/objects/MemTest.py:
    Add parameter to configure what percentage of mem accesses are functional
src/mem/cache/base_cache.cc:
src/mem/cache/cache_impl.hh:
    Use fix Packet function
src/mem/packet.cc:
    Fix an assert that was checking the wrong thing
src/mem/tport.cc:
    Properly detect if we need to do the access to the functional device

--HG--
extra : convert_revision : 447cc1a9a65ddd2a41e937fb09dc0e7c74e9c75e
2006-10-20 13:01:21 -04:00
Ali Saidi
7be58fd5f4 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem.head

--HG--
extra : convert_revision : c0f9bde20585b3811ff906728b003072b69696b5
2006-10-20 13:00:15 -04:00
Ali Saidi
32384b2f6b still working on getting past initialization
--HG--
extra : convert_revision : 7a5fccb9a19d363e479ef24012a7b8598272eaa9
2006-10-20 13:00:05 -04:00
Lisa Hsu
75ecd3be60 how did i not commit this already? the other way doesn't seem to work, need to convert to System ptr first to access System method.
src/python/m5/SimObject.py:
    how did i not commit this already?  the other way doesn't seem to work.

--HG--
extra : convert_revision : 55737d3d10742a1913a376d1febbc5809f2fab8f
2006-10-18 18:04:53 -04:00
Steve Reinhardt
6cd187e1f0 Get rid of obsolete in-cache copy support.
--HG--
extra : convert_revision : a701ed9d078c67718a33f4284c0403a8aaac7b25
2006-10-18 08:16:22 -07:00
Steve Reinhardt
05c487ef3c Enable MP systems via cmd-line flag in fs.py.
configs/example/fs.py:
    Add flag for MP server systems.
src/python/m5/objects/AlphaConsole.py:
src/python/m5/objects/IntrControl.py:
    Change CPU from 'any' to 'cpu[0]' to work better with MP sytems.
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-timing-dual.py:
    Don't need to set console & intrcontrol cpu
    params anymore (default is fixed now).

--HG--
extra : convert_revision : 9417b12b1b395ff7d6a9f2894e4123923c754daf
2006-10-17 21:15:11 -07:00
Lisa Hsu
339b1f8516 Merge zizzer:/bk/newmem
into  zed.eecs.umich.edu:/z/hsul/work/m5/newmem

src/cpu/simple/timing.cc:
    hand merge

--HG--
extra : convert_revision : 083bf102249ad9bc63c447dbf85d3863f935f647
2006-10-12 18:56:57 -04:00
Lisa Hsu
ba795552f5 System not global object, need to preface it with objects.
--HG--
extra : convert_revision : 5e105d7082a8c103fb5d5383c3093734bfd590f5
2006-10-11 18:54:31 -04:00
Lisa Hsu
8acecfef9b since memoryMode was put into the System (from SimObject), things got broken - this fixes it so that changeToTiming/changeToAtomic works.
src/python/m5/SimObject.py:
    now that setMemoryMode is a method in System, need to convert the SimObject * _ccObject into a system ptr to call setMemoryMode.
src/sim/main.cc:
    need this conversion now.
src/sim/sim_object.hh:
    put the enum back into SimObject.
src/sim/system.hh:
    memoryMode is now a part of SimObject, need the ::'s

--HG--
extra : convert_revision : 0ade06957fa57b497798e1f50c237ca1badc821d
2006-10-11 18:53:50 -04:00
Ron Dreslinski
567afbf6ce More cache fixes. Atomic coherence now works as well.
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
    Make Memtester able to test atomic as well
src/mem/bus.cc:
src/mem/bus.hh:
    Handle atomic snoops properly for cache->cache transfers
src/mem/cache/cache_impl.hh:
    Debug output.
    Clean up memleak in atomic mode.
    Set hitLatency.
    Still need to send back reasonable number for atomic return value.
src/mem/packet.cc:
    Add command strings for new commands
src/python/m5/objects/MemTest.py:
    Add param to test atomic memory.

--HG--
extra : convert_revision : 43f880e29215776167c16ea90793ebf8122c785b
2006-10-11 18:28:33 -04:00
Kevin Lim
bdde892d66 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem

src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/cpu/simple/timing.hh:
tests/configs/o3-timing-mp.py:
    Hand merge.

--HG--
extra : convert_revision : a58cc439eb5e8f900d175ed8b5a85b6c8723e558
2006-10-09 22:59:56 -04:00
Gabe Black
a23c6a7193 Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus

--HG--
extra : convert_revision : 8267487b935eaf11665841ace3a5c664751b53b0
2006-10-09 18:19:35 -04:00
Ron Dreslinski
b9fb4d4870 Make memtest work with 8 memtesters
src/mem/physical.cc:
    Update comment to match memtest use
src/python/m5/objects/PhysicalMemory.py:
    Make memtester have a way to connect functionally
tests/configs/memtest.py:
    Properly create 8 memtesters and connect them to the memory system

--HG--
extra : convert_revision : e5a2dd9c8918d58051b553b5c6a14785d48b34ca
2006-10-09 17:13:50 -04:00
Ron Dreslinski
95ca4f9d4a Merge zizzer:/z/m5/Bitkeeper/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : 77b06379a520dd91f124c0a543e30ec3a9cd1452
2006-10-09 00:28:26 -04:00
Ron Dreslinski
6c7ab02682 Update the Memtester, commit a config file/test for it.
src/cpu/SConscript:
    Add memtester to the compilation environment.
    Someone who knows this better should make the MemTest a cpu model parameter.

    For now attached with the build of o3 cpu.
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
    Update Memtest for new mem system
src/python/m5/objects/MemTest.py:
    Update memtest python description

--HG--
extra : convert_revision : d6a63e08fda0975a7abfb23814a86a0caf53e482
2006-10-09 00:26:10 -04:00
Steve Reinhardt
31f3f24214 Fixes for Port proxies and proxy parameters.
--HG--
extra : convert_revision : 76b16fe2926611bd1c12c8ad7392355ad30a5138
2006-10-08 18:26:59 -07:00
Gabe Black
2df9053bb0 Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus

src/mem/bus.cc:
    Hand merged. Needs to be fixed

--HG--
extra : convert_revision : df03219ccfd18431cc726a063bd29d30554944a1
2006-10-08 19:14:09 -04:00
Gabe Black
a82f017591 bus changes
src/mem/bus.cc:
src/mem/bus.hh:
    minor fix and some formatting changes
src/python/m5/objects/Bus.py:
    changed bits to bytes

--HG--
extra : convert_revision : dcd22205604b7a2727eaf2094084c4858f3589c5
2006-10-08 18:44:49 -04:00
Steve Reinhardt
d3fba5aa30 Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)
and PhysicalMemory.  *No* support for caches or O3CPU.
Note that properly setting cpu_id on all CPUs is now required
for correct operation.

src/arch/SConscript:
src/base/traceflags.py:
src/cpu/base.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/request.hh:
src/python/m5/objects/BaseCPU.py:
tests/configs/simple-atomic.py:
tests/configs/simple-timing.py:
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
    Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)
    and PhysicalMemory.  *No* support for caches or O3CPU.

--HG--
extra : convert_revision : 6ce982d44924cc477e049b9adf359818908e72be
2006-10-08 10:53:24 -07:00
Kevin Lim
8949d813ff Clean up configs.
configs/common/FSConfig.py:
configs/common/SysPaths.py:
configs/example/fs.py:
configs/example/se.py:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
    Clean up configs by removing FullO3Config and instead using default values.
src/python/m5/objects/FUPool.py:
    Add in default FUPool.
src/python/m5/objects/O3CPU.py:
    Use defaults better.  Also set checker parameters, and fix up a config bug.

--HG--
extra : convert_revision : 5fd0c000143f4881f10a9a575c3810dc97cb290b
2006-10-08 01:12:42 -04:00
Gabe Black
d9172c8f46 Partial reimplementation of the bus. The "clock" and "width" parameters have been added, and the HasData flag has been partially added to packets.
--HG--
extra : convert_revision : abb2a259fcf843457abbc0bd36f9504fbe6d7d39
2006-10-05 16:26:16 -04:00
Kevin Lim
51c8eab7b3 Oops, forgot to assign the option to the param context.
--HG--
extra : convert_revision : 022c3efaa3ade3fca3dfe554ececa4eeb396dc9c
2006-10-02 18:13:42 -04:00
Kevin Lim
e08aa72b3d Add in ability to start a trace at a specific cycle.
--HG--
extra : convert_revision : 54098f3974d2a05d60e57113f7ceb46cb7a26672
2006-10-02 12:04:24 -04:00
Kevin Lim
568fa11084 Updates to fix merge issues and bring almost everything up to working speed. Ozone CPU remains untested, but everything else compiles and runs.
src/arch/alpha/isa_traits.hh:
    This got changed to the wrong version by accident.
src/cpu/base.cc:
    Fix up progress event to not schedule itself if the interval is set to 0.
src/cpu/base.hh:
    Fix up the CPU Progress Event to not print itself if it's set to 0.  Also remove stats_reset_inst (something I added to m5 but isn't necessary here).
src/cpu/base_dyn_inst.hh:
src/cpu/checker/cpu.hh:
    Remove float variable of instResult; it's always held within the double part now.
src/cpu/checker/cpu_impl.hh:
    Use thread and not cpuXC.
src/cpu/o3/alpha/cpu_builder.cc:
src/cpu/o3/checker_builder.cc:
src/cpu/ozone/checker_builder.cc:
src/cpu/ozone/cpu_builder.cc:
src/python/m5/objects/BaseCPU.py:
    Remove stats_reset_inst.
src/cpu/o3/commit_impl.hh:
src/cpu/ozone/lw_back_end_impl.hh:
    Get TC, not XCProxy.
src/cpu/o3/cpu.cc:
    Switch out updates from the version of m5 I have.  Also remove serialize code that got added twice.
src/cpu/o3/iew_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/thread_state.hh:
    Remove code that was added twice.
src/cpu/o3/lsq_unit.hh:
    Add back in stats that got lost in the merge.
src/cpu/o3/lsq_unit_impl.hh:
    Use proper method to get flags.  Also wake CPU if we're coming back from a cache miss.
src/cpu/o3/thread_context_impl.hh:
src/cpu/o3/thread_state.hh:
    Support profiling.
src/cpu/ozone/cpu.hh:
    Update to use proper typename.
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/dyn_inst_impl.hh:
    Updates for newmem.
src/cpu/ozone/lw_lsq_impl.hh:
    Get flags correctly.
src/cpu/ozone/thread_state.hh:
    Reorder constructor initialization, use tc.
src/sim/pseudo_inst.cc:
    Allow for loading of symbol file.  Be sure to use ThreadContext and not ExecContext.

--HG--
extra : convert_revision : c5657f84155807475ab4a1e20d944bb6f0d79d94
2006-10-02 11:58:09 -04:00
Kevin Lim
4ed184eade Merge ktlim@zamp:./local/clean/o3-merge/m5
into  zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem

configs/boot/micro_memlat.rcS:
configs/boot/micro_tlblat.rcS:
src/arch/alpha/ev5.cc:
src/arch/alpha/isa/decoder.isa:
src/arch/alpha/isa_traits.hh:
src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/base_dyn_inst.hh:
src/cpu/checker/cpu.hh:
src/cpu/checker/cpu_impl.hh:
src/cpu/o3/alpha/cpu_impl.hh:
src/cpu/o3/alpha/params.hh:
src/cpu/o3/checker_builder.cc:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/lsq_unit_impl.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/checker_builder.cc:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_back_end.hh:
src/cpu/ozone/lw_back_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/simple/base.cc:
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
src/cpu/thread_state.hh:
src/dev/ide_disk.cc:
src/python/m5/objects/O3CPU.py:
src/python/m5/objects/Root.py:
src/python/m5/objects/System.py:
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
src/sim/system.hh:
util/m5/m5.c:
    Hand merge.

--HG--
rename : arch/alpha/ev5.cc => src/arch/alpha/ev5.cc
rename : arch/alpha/freebsd/system.cc => src/arch/alpha/freebsd/system.cc
rename : arch/alpha/isa/decoder.isa => src/arch/alpha/isa/decoder.isa
rename : arch/alpha/isa/mem.isa => src/arch/alpha/isa/mem.isa
rename : arch/alpha/isa_traits.hh => src/arch/alpha/isa_traits.hh
rename : arch/alpha/linux/system.cc => src/arch/alpha/linux/system.cc
rename : arch/alpha/system.cc => src/arch/alpha/system.cc
rename : arch/alpha/tru64/system.cc => src/arch/alpha/tru64/system.cc
rename : cpu/base.cc => src/cpu/base.cc
rename : cpu/base.hh => src/cpu/base.hh
rename : cpu/base_dyn_inst.hh => src/cpu/base_dyn_inst.hh
rename : cpu/checker/cpu.hh => src/cpu/checker/cpu.hh
rename : cpu/checker/cpu.cc => src/cpu/checker/cpu_impl.hh
rename : cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc
rename : cpu/checker/o3_cpu_builder.cc => src/cpu/o3/checker_builder.cc
rename : cpu/o3/commit_impl.hh => src/cpu/o3/commit_impl.hh
rename : cpu/o3/cpu.cc => src/cpu/o3/cpu.cc
rename : cpu/o3/fetch_impl.hh => src/cpu/o3/fetch_impl.hh
rename : cpu/o3/iew.hh => src/cpu/o3/iew.hh
rename : cpu/o3/iew_impl.hh => src/cpu/o3/iew_impl.hh
rename : cpu/o3/inst_queue.hh => src/cpu/o3/inst_queue.hh
rename : cpu/o3/inst_queue_impl.hh => src/cpu/o3/inst_queue_impl.hh
rename : cpu/o3/lsq_impl.hh => src/cpu/o3/lsq_impl.hh
rename : cpu/o3/lsq_unit.hh => src/cpu/o3/lsq_unit.hh
rename : cpu/o3/lsq_unit_impl.hh => src/cpu/o3/lsq_unit_impl.hh
rename : cpu/o3/mem_dep_unit_impl.hh => src/cpu/o3/mem_dep_unit_impl.hh
rename : cpu/o3/rename.hh => src/cpu/o3/rename.hh
rename : cpu/o3/rename_impl.hh => src/cpu/o3/rename_impl.hh
rename : cpu/o3/thread_state.hh => src/cpu/o3/thread_state.hh
rename : cpu/o3/tournament_pred.cc => src/cpu/o3/tournament_pred.cc
rename : cpu/o3/tournament_pred.hh => src/cpu/o3/tournament_pred.hh
rename : cpu/checker/cpu_builder.cc => src/cpu/ozone/checker_builder.cc
rename : cpu/ozone/cpu.hh => src/cpu/ozone/cpu.hh
rename : cpu/ozone/cpu_builder.cc => src/cpu/ozone/cpu_builder.cc
rename : cpu/ozone/cpu_impl.hh => src/cpu/ozone/cpu_impl.hh
rename : cpu/ozone/front_end.hh => src/cpu/ozone/front_end.hh
rename : cpu/ozone/front_end_impl.hh => src/cpu/ozone/front_end_impl.hh
rename : cpu/ozone/inorder_back_end_impl.hh => src/cpu/ozone/inorder_back_end_impl.hh
rename : cpu/ozone/inst_queue_impl.hh => src/cpu/ozone/inst_queue_impl.hh
rename : cpu/ozone/lw_back_end.hh => src/cpu/ozone/lw_back_end.hh
rename : cpu/ozone/lw_back_end_impl.hh => src/cpu/ozone/lw_back_end_impl.hh
rename : cpu/ozone/lw_lsq.hh => src/cpu/ozone/lw_lsq.hh
rename : cpu/ozone/lw_lsq_impl.hh => src/cpu/ozone/lw_lsq_impl.hh
rename : cpu/ozone/simple_params.hh => src/cpu/ozone/simple_params.hh
rename : cpu/ozone/thread_state.hh => src/cpu/ozone/thread_state.hh
rename : cpu/simple/cpu.cc => src/cpu/simple/base.cc
rename : cpu/cpu_exec_context.cc => src/cpu/simple_thread.cc
rename : cpu/thread_state.hh => src/cpu/thread_state.hh
rename : dev/ide_disk.hh => src/dev/ide_disk.hh
rename : python/m5/objects/BaseCPU.py => src/python/m5/objects/BaseCPU.py
rename : python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/O3CPU.py
rename : python/m5/objects/OzoneCPU.py => src/python/m5/objects/OzoneCPU.py
rename : python/m5/objects/Root.py => src/python/m5/objects/Root.py
rename : python/m5/objects/System.py => src/python/m5/objects/System.py
rename : sim/eventq.hh => src/sim/eventq.hh
rename : sim/pseudo_inst.cc => src/sim/pseudo_inst.cc
rename : sim/pseudo_inst.hh => src/sim/pseudo_inst.hh
rename : sim/serialize.cc => src/sim/serialize.cc
rename : sim/stat_control.cc => src/sim/stat_control.cc
rename : sim/stat_control.hh => src/sim/stat_control.hh
rename : sim/system.hh => src/sim/system.hh
extra : convert_revision : 135d90e43f6cea89f9460ba4e23f4b0b85886e7d
2006-09-30 23:43:23 -04:00
Ali Saidi
17b0e9714d add boiler plate intel nic code
src/SConscript:
    add intel nic to sconscript
src/dev/pcidev.cc:
    fix bug with subsystemid value
src/python/m5/objects/Ethernet.py:
    add intel nic to ethernet.py
src/python/m5/objects/Ide.py:
src/python/m5/objects/Pci.py:
    Move config_latency into pci where it belogs

--HG--
extra : convert_revision : 7163aaf7b4098496518b0910cef62f2ce3dd574d
2006-09-18 20:12:45 -04:00
Gabe Black
8abab05c83 Merge zizzer.eecs.umich.edu:/bk/newmem
into  ewok.(none):/home/gblack/m5/newmem

--HG--
extra : convert_revision : 91aacb435c223e8c37f6ba0a458b0dee55edcaf2
2006-09-15 00:59:39 -04:00
Steve Reinhardt
a7e8a78958 Add support for assigning lists of ports or proxies to VectorPorts.
Includes support for printing readable VectorPort and Proxy names
(via __str__).

--HG--
extra : convert_revision : c48534a498b3036fe6ac45ff1606656546c79afb
2006-09-08 19:10:11 -04:00
Steve Reinhardt
c15e6d8e0a Try to make unproxy order more deterministic.
--HG--
extra : convert_revision : 0bc543014dced6dfed4122d4c1b8f22e6c8d7a13
2006-09-06 22:37:35 -07:00
Steve Reinhardt
545cbec5f7 Enable proxies (Self/Parent) for specifying ports.
Significant revamp of Port code.
Some cleanup of SimObject code too, particularly to
make the SimObject and MetaSimObject implementations of
__setattr__ more consistent.
Unproxy code split out of print_ini().

src/python/m5/multidict.py:
    Make get() return None by default, to match semantics
    of built-in dictionary objects.

--HG--
extra : convert_revision : db73b6cdd004a82a08b2402afd1e16544cb902a4
2006-09-05 22:04:34 -07:00
Steve Reinhardt
89f0bc9e4c Print ports in config.ini as well.
--HG--
extra : convert_revision : 703d3a57250613315735709de8f40a9956cee6e2
2006-09-05 12:22:47 -07:00
Steve Reinhardt
c39aea440c More Python hacking to deal with config.py split
and resulting recursive import trickiness.

--HG--
extra : convert_revision : 1ea93861eb8d260c9f3920dda0b8106db3e03705
2006-09-04 17:14:07 -07:00
Steve Reinhardt
1233dbb998 Split config.py into multiple files.
Some tweaking to deal with mutually recursive imports.

--HG--
rename : src/python/m5/config.py => src/python/m5/SimObject.py
extra : convert_revision : 166f7bfabfd20100e93d26a89382469465859988
2006-09-04 10:52:26 -07:00
Steve Reinhardt
a658d25d42 config.py:
Import of changes for auto-generation of C++ param structs
from my old m5 working directory.
This code is *broken* because pieces need to be shuffled around
to satisfy name dependencies, but that really messes up the
diff, so I want to make an intermediate commit here.

src/python/m5/config.py:
    Import of changes for auto-generation of C++ param structs
    from my old m5 working directory.
    This code is *broken* because pieces need to be shuffled around
    to satisfy name dependencies, but that really messes up the
    diff, so I want to make an intermediate commit here.

--HG--
extra : convert_revision : cb25ee1f4f77d1902511ee9aa766403733dd8841
2006-09-04 10:40:33 -07:00
Gabe Black
96dabdc9b0 Added uid, euid, gid, egid, pid and ppid parameters to a live process.
--HG--
extra : convert_revision : 2101be8000bcdaf683730cfc079b4b78e34365d0
2006-09-03 02:04:25 -04:00
Steve Reinhardt
edeb8f39a7 Tweak proxy resolution error message.
--HG--
extra : convert_revision : 3b186209515975be0d8bc9acc214425adcaa16f2
2006-08-31 17:58:46 -07:00
Ron Dreslinski
689eb39d48 Merge zizzer:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/newmem

src/python/m5/objects/BaseCPU.py:
    Merge duplicate change

--HG--
extra : convert_revision : 214e57999ee78aadfc86e1f0b7198ff0d981ce16
2006-08-21 13:20:35 -04:00
Steve Reinhardt
a12dbc3074 Update reference outputs
--HG--
extra : convert_revision : 110a6c51cc1c562d115492b7360bfdbbded8eefd
2006-08-18 00:17:21 -04:00