Merge zizzer:/z/m5/Bitkeeper/newmem

into  zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/newmem

src/python/m5/objects/BaseCPU.py:
    Merge duplicate change

--HG--
extra : convert_revision : 214e57999ee78aadfc86e1f0b7198ff0d981ce16

src/mem/packet.hh

@@ -266,6 +266,7 @@ class Packet
            result(Unknown)
     {
         flags = 0;
+        time = curTick;
     }
 
     /** Alternate constructor if you are trying to create a packet with
@@ -280,6 +281,7 @@ class Packet
            result(Unknown)
     {
         flags = 0;
+        time = curTick;
     }
 
     /** Destructor. */
@@ -295,6 +297,7 @@ class Packet
         assert(req->validPaddr);
         addr = req->paddr;
         size = req->size;
+        time = req->time;
         addrSizeValid = true;
         result = Unknown;
         if (dynamicData) {

src/python/m5/objects/BaseCPU.py

@@ -43,6 +43,7 @@ class BaseCPU(SimObject):
         self.icache_port = ic.cpu_side
         self.dcache_port = dc.cpu_side
         self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
+#        self.mem = dc
 
     def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
         self.addPrivateSplitL1Caches(ic, dc)

tests/configs/simple-timing.py

@@ -40,7 +40,7 @@ cpu = TimingSimpleCPU()
 cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
                               MyCache(size = '2MB'))
 cpu.mem = cpu.dcache
-
+cpu.mem = cpu.dcache
 system = System(cpu = cpu,
                 physmem = PhysicalMemory(),
                 membus = Bus())