Commit graph

2363 commits

Author SHA1 Message Date
Kevin Lim
4ec5e90c8f Ozone updates.
cpu/ozone/front_end.hh:
cpu/ozone/front_end_impl.hh:
cpu/ozone/lw_back_end.hh:
    Support latency for Ozone FE and BE.
cpu/ozone/lw_back_end_impl.hh:
    Support latency for Ozone FE and BE.

    Also fixes for switching out, profiling.
cpu/ozone/lw_lsq.hh:
cpu/ozone/lw_lsq_impl.hh:
    Fixes for switching out.
cpu/ozone/simple_params.hh:
    Updated parameters.

--HG--
extra : convert_revision : 21d4846a59a2239bfdf8fe92e47fd0972debe4f5
2006-08-24 17:45:04 -04:00
Kevin Lim
ad2fa1e1c9 Support profiling.
--HG--
extra : convert_revision : eab02dea68442bd3f8c5d1d16b7f93f43cbda2a5
2006-08-24 17:43:08 -04:00
Kevin Lim
74e8abd37e Switch out fixups for the CPUs.
cpu/cpu_exec_context.cc:
    Be sure to switch over the kernel stats so things don't get messed up.  This may lead to weird stats files for sampling runs (detailed stats should be correct, regardless of which kernel stats this is defined on).
cpu/o3/cpu.cc:
    Updates for switching out.  Also include a bunch of debug info if needed.
cpu/o3/fetch_impl.hh:
    Switch out properly.
cpu/o3/inst_queue.hh:
cpu/o3/inst_queue_impl.hh:
    Comment out unused stats (they made the stats file huge).
cpu/o3/lsq_unit.hh:
cpu/o3/lsq_unit_impl.hh:
    Add in new stat.
cpu/o3/rename.hh:
    Fix up for switching out.
cpu/o3/rename_impl.hh:
    Fix up for switching out.  Be sure to mark any Misc regs as ready if their renamed inst got squashed from being switched out.
cpu/ozone/cpu_impl.hh:
cpu/simple/cpu.cc:
    Switch out fixup.
sim/eventq.hh:
    Make CPU switching more immediate.
    Also comment out the assertion, as it doesn't apply if we're putting it on an inst-based queue.

--HG--
extra : convert_revision : f40ed40604738993f061e0c628810ff37a920562
2006-08-24 17:29:34 -04:00
Kevin Lim
5da3f70560 Update checker.
cpu/checker/cpu.cc:
    Print better error messages.
cpu/checker/cpu.hh:
    Fix up small bug (similar to Ozone's DynInsts with FPs and float/doubles), output better messages.

--HG--
extra : convert_revision : 0e199b3dbbcdb5917cdfbebb4c5c18e4b9056c86
2006-08-24 17:22:31 -04:00
Kevin Lim
9fef4d4630 Stats reset, profiling stuff.
cpu/base.cc:
    Be sure to deschedule the profile event so it doesn't take profiles while the CPU is switched out.

    Also include the option to reset stats at a specific instruction.
cpu/base.hh:
    Include the option to reset stats at a specific instruction.
cpu/checker/cpu_builder.cc:
    Handle stats reset inst.
cpu/o3/alpha_cpu_builder.cc:
    Handle stats reset inst, allow for profiling.
cpu/ozone/cpu_builder.cc:
    Handle profiling, stats reset event, slightly different parameters.
python/m5/objects/BaseCPU.py:
    Add in stats reset.

--HG--
extra : convert_revision : e27a78f7fb8fd19c53d9f2c1e6edce4a98cbafdb
2006-08-24 16:06:45 -04:00
Kevin Lim
4a2c50bc8f Support loading in a symbol file.
arch/alpha/freebsd/system.cc:
arch/alpha/isa/decoder.isa:
arch/alpha/linux/system.cc:
arch/alpha/system.cc:
arch/alpha/tru64/system.cc:
    Let symbol files be read in so that profiling can happen on the binaries as well.
python/m5/objects/System.py:
    Add in symbol files.
sim/pseudo_inst.cc:
    Load in a specified symbol file.
sim/pseudo_inst.hh:
    Allow for symbols to be loaded.
sim/system.hh:
    Support symbol file.
util/m5/m5.c:
util/m5/m5op.S:
    Add support to m5 util for loading symbols (and readfile).

--HG--
extra : convert_revision : f10c1049bcd7b22b98c73052c0666b964aff222b
2006-08-23 16:57:07 -04:00
Kevin Lim
de321175f2 Add in a bunch more stuff.
configs/boot/micro_memlat.rcS:
    Update these scripts so they work (not sure why they broke)
configs/boot/micro_tlblat.rcS:
    Update this script to use a different test.

--HG--
extra : convert_revision : 6e8692540a9fac6ae8f2d9975c70d4135354b849
2006-08-11 17:48:41 -04:00
Kevin Lim
716ceb6c10 Code update for CPU models.
arch/alpha/isa_traits.hh:
    Add in clear functions.
cpu/base.cc:
cpu/base.hh:
    Add in CPU progress event.
cpu/base_dyn_inst.hh:
    Mimic normal registers in terms of writing/reading floats.
cpu/checker/cpu.cc:
cpu/checker/cpu.hh:
cpu/checker/cpu_builder.cc:
cpu/checker/o3_cpu_builder.cc:
    Fix up stuff.
cpu/cpu_exec_context.cc:
cpu/cpu_exec_context.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
    Bring up to speed with newmem.
cpu/o3/alpha_cpu_builder.cc:
    Allow for progress intervals.
cpu/o3/tournament_pred.cc:
    Fix up predictor.
cpu/o3/tournament_pred.hh:
cpu/ozone/cpu.hh:
cpu/ozone/cpu_impl.hh:
cpu/simple/cpu.cc:
    Fixes.
cpu/ozone/cpu_builder.cc:
    Allow progress interval.
cpu/ozone/front_end_impl.hh:
    Comment out this message.
cpu/ozone/lw_back_end_impl.hh:
    Remove this.
python/m5/objects/BaseCPU.py:
    Add progress interval.
python/m5/objects/Root.py:
    Allow for stat reset.
sim/serialize.cc:
sim/stat_control.cc:
    Add in stats reset.

--HG--
extra : convert_revision : fdb5ac5542099173cc30c40ea93372a065534b5e
2006-08-11 17:42:59 -04:00
Kevin Lim
5ec58c4bdc Fix up some ISA related stuff.
arch/alpha/isa/decoder.isa:
    Marked a few more instructions as unverifiable.
arch/alpha/isa/mem.isa:
    Warn instead of panic, otherwise this can cause the simulation to fail even if the instruction is never committed.

--HG--
extra : convert_revision : 12befc6fedd1a6883d0517e649ad01b91fb561ae
2006-08-02 12:07:44 -04:00
Kevin Lim
5be592f870 Make checker handle not executing the same instruction as the main CPU a little better.
Also add the option for the checker to update itself with the main CPU's state if it executes an instruction differently (so it will handle DMA timing errors properly).

--HG--
extra : convert_revision : 760d11ec1a249bc75e2807d320866b5d08c2b6f2
2006-08-02 12:06:59 -04:00
Kevin Lim
cbfbb7bc56 Updates to bring CPU portion of m5 up-to-date with newmem.
--HG--
extra : convert_revision : 00e6eefb24e6ffd9c7c5d8165db26fbf6199fdc4
2006-08-02 12:05:34 -04:00
Kevin Lim
8d220c5c10 Updates for registers and stuff.
arch/alpha/ev5.cc:
    Update for copying IPRs.
arch/alpha/isa_traits.hh:
    Allow for misc register file to serialize.  Also add some register copying code.
cpu/cpu_exec_context.cc:
    Use ISA's function to copy registers.

--HG--
extra : convert_revision : 09fa3b2b1b229cbf3a34f69354953da2607c2a8f
2006-08-02 12:04:18 -04:00
Kevin Lim
db6c908e0f Minor configuration updates.
--HG--
extra : convert_revision : d638d440edd91caa31977eb6d2325c899962936f
2006-08-02 11:56:06 -04:00
Kevin Lim
8671d927d8 Add in comments for checker.
--HG--
extra : convert_revision : 8921907af0f18313bc66ad2a584fc182526fe1a2
2006-06-01 15:40:06 -04:00
Kevin Lim
51ed3c3fd9 Fix stat bug.
--HG--
extra : convert_revision : 3e4df934478de1ef6a84f193d9ef722157ac6baf
2006-06-01 15:39:45 -04:00
Kevin Lim
a514bf2150 Comments and code cleanup.
cpu/activity.cc:
cpu/activity.hh:
cpu/o3/alpha_cpu.hh:
    Updates to include comments.
cpu/base_dyn_inst.cc:
    Remove call to thread->misspeculating(), as it's never actually misspeculating.

--HG--
extra : convert_revision : 86574d684770fac9b480475acca048ea418cdac3
2006-05-31 11:45:02 -04:00
Kevin Lim
94eff2f485 Merge ktlim@zamp:/z/ktlim2/clean/m5-merge
into  zamp.eecs.umich.edu:/z/ktlim2/clean/m5-o3

--HG--
extra : convert_revision : d3381ee4907c2b6f1747c4496c980e34913e81e7
2006-05-25 17:56:23 -04:00
Kevin Lim
f1fab2a446 Fix stat typo.
--HG--
extra : convert_revision : f23d8c50f586fb8f25d4ce992730213f0c301b0f
2006-05-25 17:56:01 -04:00
Kevin Lim
f5b5391cfb Missed this file in last check in.
--HG--
extra : convert_revision : 6c42350fc3cebb5cf4a6da8ea0c51cca15b3f99f
2006-05-25 17:13:00 -04:00
Kevin Lim
248bd2bb62 Various branch predictor fixes/cleanup. It works more correctly now and supports both local and tournament predictors.
cpu/o3/2bit_local_pred.cc:
    Branch predictor cleanup/fixup.  Rename this to LocalBP.
cpu/o3/2bit_local_pred.hh:
    Rename to LocalBP, update to support changes to BPredUnit, include comments.
cpu/o3/alpha_cpu_builder.cc:
    Support extra parameters to the branch predictor.  Now it takes in a parameter to tell it which branch predictor it is using, the local or the tournament predictor.
cpu/o3/alpha_params.hh:
    Add in extra parameter for the branch predictor type.
cpu/o3/bpred_unit.cc:
    Branch predictor fixup/cleanup.  Rename it to BPredUnit.
cpu/o3/bpred_unit.hh:
    Branch predictor fixup/cleanup.  Now supports both the local and tournament predictors, and stores the branch predictor update state.
cpu/o3/bpred_unit_impl.hh:
    Branch predictor overhaul.  Now supports both the local and tournament predictors.
cpu/o3/cpu_policy.hh:
cpu/ozone/ozone_impl.hh:
cpu/ozone/simple_impl.hh:
    Reflect the class name change.
cpu/o3/decode_impl.hh:
    Be sure to set the predicted target as well so we don't squash twice.
cpu/o3/tournament_pred.cc:
cpu/o3/tournament_pred.hh:
    Fixes to the tournament predictor.
cpu/ozone/simple_params.hh:
    Include parameter for the branch predictor type.
python/m5/objects/AlphaFullCPU.py:
python/m5/objects/OzoneCPU.py:
    Include the parameter for the branch predictor type.

--HG--
extra : convert_revision : 34afebb3b40b47accb12558e439ee4cb03df5e64
2006-05-25 17:01:48 -04:00
Kevin Lim
02aa549c9b Fix minor memory leak.
--HG--
extra : convert_revision : aa222dd95d833b16b0f474ec156bd6955c2c54c6
2006-05-25 14:41:36 -04:00
Kevin Lim
32509d8387 Fix up kernel stats, allow them to not be used as well.
arch/alpha/ev5.cc:
    Fix up some stuff I missed in the last kernel stats checkin.
cpu/checker/cpu.cc:
    Allow the checker to disable its kernel stats.
cpu/cpu_exec_context.cc:
    Allow CPUExecContext to be created without kernelStats.
cpu/cpu_exec_context.hh:
    Allow CPUExecContext to be created without kernelStats.  Default usage leaves kernelStats on.

--HG--
extra : convert_revision : 8ed5bffd3a5b6275baa07fb4ea385eeab1a0456a
2006-05-25 11:50:42 -04:00
Kevin Lim
3fe3523232 Support new flags now used instead of flags in decoder.isa.
cpu/ozone/front_end_impl.hh:
cpu/ozone/lw_back_end_impl.hh:
cpu/ozone/lw_lsq_impl.hh:
    Support new flags added in.

--HG--
extra : convert_revision : 2e756fd1913cf600650afc39dd715d59b9b89c42
2006-05-24 14:31:06 -04:00
Kevin Lim
16df8221ff Merge ktlim@zizzer:/bk/m5
into  zamp.eecs.umich.edu:/z/ktlim2/clean/m5-o3

--HG--
extra : convert_revision : 804302a5edb9d908808861f7f54a4f3cbb22830c
2006-05-23 18:19:04 -04:00
Kevin Lim
5d3a1e8f65 Updates to isa parser to make it see dependencies properly with the new scanner.
arch/alpha/isa/main.isa:
    Use automatic path includes thanks to updates to isa parser.
arch/isa_parser.py:
    Pull changes to isa parser from newmem into m5.  This fixes a bug where the files include in main.isa were not being included as dependencies properly.

--HG--
extra : convert_revision : 8ef1e2e1a64e7a5762baf7a09abc8665d7c2f688
2006-05-23 18:18:16 -04:00
Kevin Lim
b414c9e736 Merge ktlim@zizzer:/bk/m5
into  zamp.eecs.umich.edu:/z/ktlim2/clean/m5-o3

--HG--
extra : convert_revision : 0a6140f3f5e7c454981c5aa2b221224f076e50eb
2006-05-23 17:04:25 -04:00
Kevin Lim
358cf1b117 Rework how instructions are scheduled and executed.
The "execute" portion of IEW is really just the last cycle of execution, at which point execute() gets called.  Execution begins inside the IQ, when it schedules FUs for specific instructions.  As a result, the Execute stage should just pull all completing instructions out of the IQ stage and execute them.
Limiting the number of writebacks outstanding must still be done.

cpu/o3/iew_impl.hh:
    Rework how instructions are scheduled and executed.  There shouldn't be a specific "width" from issue to execute because issue does the scheduling of the functional units (really the beginning of the execution).
cpu/o3/inst_queue.hh:
cpu/o3/inst_queue_impl.hh:
    Rework how instructions are scheduled and executed.

--HG--
extra : convert_revision : bbf1a8a4c0a2f2a938bdd78d74493048fd3b4b55
2006-05-23 17:03:43 -04:00
Kevin Lim
c9ad4a15d6 Cleanup checker.
cpu/checker/cpu.cc:
    Cleanup checker, give more useful warning messages.
    Also fix bug
cpu/checker/cpu.hh:
    Cleanup checker, use forward declaration instead of include.

--HG--
extra : convert_revision : 8f231199a0a75788218320cdbcc7f70441e5d574
2006-05-23 16:59:13 -04:00
Kevin Lim
6c386396fa Code cleanup.
cpu/base_dyn_inst.hh:
    Code cleanup

--HG--
extra : convert_revision : 501c03f8e4346ffbcb545ddeee30c1f8ded9baa7
2006-05-23 16:57:14 -04:00
Kevin Lim
ff3d16ca1f Move kernel stats out of CPU and into XC.
arch/alpha/ev5.cc:
    Move kernel stats out of CPU and into XC.  Also be sure to check if the kernel stats exist prior to using them.

--HG--
extra : convert_revision : 565cd7026410fd7d8586f953d9b328c2e67a9473
2006-05-23 16:51:16 -04:00
Kevin Lim
eeeee7c58f Add extra flags to help new CPU handle various instructions.
IsIprAccess flag may go away in the future (op class can be used to tell this), and the CPU still needs a specific way to identify/deal with syscalls.

arch/alpha/isa/decoder.isa:
    Added a few extra flags to help the new CPU identify various classes of instructions without having to force certain behaviors for all CPUs.
cpu/base_dyn_inst.hh:
cpu/static_inst.hh:
    Added extra flags.
cpu/o3/iew_impl.hh:
cpu/o3/inst_queue_impl.hh:
    Handle store conditionals specially.
cpu/o3/lsq_unit_impl.hh:
    Extra flags tells if the instruction is a store conditional.
cpu/o3/rename_impl.hh:
    Handle IPR accesses and store conditionals specially.

--HG--
extra : convert_revision : 39debec4fa5341ae8a8ab5650bd12730aeb6c04f
2006-05-23 14:38:16 -04:00
Kevin Lim
7df1412ccd Undo changes to instruction flags that has caused statistics to change in regressions.
This temporarily will break the O3 and Ozone CPU models.  Updates to fix them will be coming soon.

arch/alpha/isa/decoder.isa:
    Undo changes to instruction flags that has caused statistics to change in regressions.

--HG--
extra : convert_revision : c0fa9d55a22cae7c4f02d388870565b205d6fba3
2006-05-22 16:01:25 -04:00
Kevin Lim
5a7db55e9a Threads start off in suspended status now (Korey's changes for SMT).
--HG--
extra : convert_revision : ad726f9f258e1983d2af5057ff6e5f9d2a5dd072
2006-05-21 01:55:58 -04:00
Kevin Lim
e3d5588ca7 O3 code update/cleanup.
cpu/o3/commit_impl.hh:
    O3 code update/cleanup.  Fetch fault code no longer needed (see previous checkin).

--HG--
extra : convert_revision : f602e7f978e19b8900dce482f38f9c7a195e94da
2006-05-19 15:53:17 -04:00
Kevin Lim
1a6f21b8d2 Remove sat_counter.cc and put its code into sat_counter.hh.
cpu/SConscript:
    Remove sat_counter.cc and push its functions into the .hh file (all functions were 3 or less lines).
cpu/o3/sat_counter.hh:
    Incorporate .cc code into this file.

--HG--
extra : convert_revision : d75b1319292b00b00af1ce377cc0215fd06e6916
2006-05-19 15:47:55 -04:00
Kevin Lim
fda6ddbffd Rename function to be more expressive.
--HG--
extra : convert_revision : 0c01b6d5309e2d09f03631740c9b0c8619ea26c4
2006-05-19 15:45:06 -04:00
Kevin Lim
5df3e61f16 IEW/IQ code cleanup and reorganization.
Dependecy graph code moved into its own class.
This requires the changes to the functional units, which is in the next check in.

cpu/o3/iew.hh:
cpu/o3/iew_impl.hh:
    IEW and IQ code cleanup and reorganization.
cpu/o3/inst_queue.cc:
    Dependency graph code moved into its own class now.
cpu/o3/inst_queue.hh:
    IEW/IQ code cleanup and reorganization.
    Dependecy graph code moved into its own class.
cpu/o3/inst_queue_impl.hh:
    IEW/IQ code cleanup and reorganization.
    Dependecy graph code moved into its own class.
    Issue loop cleaned up, with completion events for functional units now used more correctly (before they weren't used for multi-cycle ops with pipelined FU's).

--HG--
extra : convert_revision : 35e50192df6f71dc81d46a73fdd65f7ec07c10e4
2006-05-19 15:44:03 -04:00
Kevin Lim
c4a87f874a Move activity tracking code into its own class. Now the CPU no longer has to keep track of the activity tracking internals; it just calls advance() on the class and uses it to tell if it should deschedule itself.
SConscript:
    Split off activity/idling code into its own class to do the processing separately.
cpu/o3/alpha_cpu_builder.cc:
cpu/o3/alpha_params.hh:
    Activity stuff.  This is mostly for debugging and may be removed later on (or changed to enable/disable activity idling).
cpu/o3/cpu.cc:
    Move activity idling stuff mostly into its own class, so it no longer clutters this file.
cpu/o3/cpu.hh:
    Move activity idling stuff into its own class.
python/m5/objects/AlphaFullCPU.py:
    Add parameter for initial activity value.

--HG--
extra : convert_revision : f32f7cc03895dc07ab57ddba78c5402a1a8b0f1a
2006-05-19 15:37:52 -04:00
Kevin Lim
c7e7d07ec3 Fixes for regression build errors.
--HG--
extra : convert_revision : 1f59c853cb0e327d7cf586021b5139f1242e4f28
2006-05-19 14:27:46 -04:00
Kevin Lim
36581a5342 Faults generated at fetch are passed to the backend by creating a dummy nop instruction and giving it the fault. This unifies front end faults and normal instruction faults.
cpu/checker/cpu.cc:
    Fixups for fetch fault being sent with the instruction.
cpu/o3/fetch_impl.hh:
cpu/ozone/front_end_impl.hh:
    Send any faults generated at fetch along with a fake nop instruction to the back end.  This avoids having to use direct communication to check if the entire front end has drained; it is naturally handled through the nop's fault being handled when it reaches the head of commit.
cpu/ozone/front_end.hh:
    Add extra status TrapPending.
cpu/ozone/lw_back_end_impl.hh:
    Fetch fault handled through a dummy nop carrying the fetch fault.

    Avoid putting Nops on the exeList.

--HG--
extra : convert_revision : 8d9899748b34c204763a49c48a9b5113864f5789
2006-05-17 14:25:10 -04:00
Steve Reinhardt
343bff3b7d Backport ISA scanner fix from newmem to work with
scons 0.96.9* versions.

arch/SConscript:
    Backport ISA scanner fix from newmem.

--HG--
extra : convert_revision : 96be75660f85900fd26badef36fb4109b36d8394
2006-05-17 07:05:27 -04:00
Kevin Lim
aaf1969c78 Merge ktlim@zamp:/z/ktlim2/clean/m5-o3
into  zamp.eecs.umich.edu:/z/ktlim2/clean/m5-merge

--HG--
extra : convert_revision : 077a04edf0e3e4d735e88c9741d6742666e97de6
2006-05-16 15:30:36 -04:00
Kevin Lim
578777d48e Update configuration files.
--HG--
extra : convert_revision : f733bc68758d95987dfc481d48a4623c23b16ede
2006-05-16 15:25:46 -04:00
Kevin Lim
044f3998d0 Merge ktlim@zizzer:/bk/m5
into  zamp.eecs.umich.edu:/z/ktlim2/clean/m5-merge

--HG--
extra : convert_revision : 182df443376e5561d46f323d36089a2a49dc2024
2006-05-16 15:09:06 -04:00
Kevin Lim
abe14c253b Include checker and trap latency parameters.
--HG--
extra : convert_revision : 148c59f430874e8425952db6960ca4f5e57e2a42
2006-05-16 14:47:09 -04:00
Kevin Lim
52383ca7cc Sampler updates.
cpu/ozone/cpu.hh:
    Updates for sampler.
cpu/ozone/cpu_impl.hh:
    Updates for sampler, checker.
cpu/ozone/inorder_back_end.hh:
    Sampler updates.  Also support old memory system.

--HG--
extra : convert_revision : 33ebe38e4c08d49c6af84032b819533b784b4fe8
2006-05-16 14:09:04 -04:00
Kevin Lim
ef6e2eb3c4 Updates for sampler, checker, and general correctness.
cpu/o3/alpha_cpu.hh:
    Update for sampler to work properly.  Also code cleanup.
cpu/o3/alpha_cpu_builder.cc:
cpu/o3/alpha_dyn_inst.hh:
    Updates to support the checker.
cpu/o3/alpha_cpu_impl.hh:
    Updates to support the checker.  Also general code cleanup.
cpu/o3/alpha_dyn_inst_impl.hh:
    Code cleanup.
cpu/o3/alpha_params.hh:
    Updates to support the checker.  Also supports trap latencies set through the parameters.
cpu/o3/commit.hh:
    Supports sampler, checker.  Code cleanup.
cpu/o3/commit_impl.hh:
    Updates to support the sampler and checker, as well as general code cleanup.
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
    Support sampler and checker.
cpu/o3/decode_impl.hh:
    Supports sampler.
cpu/o3/fetch.hh:
    Supports sampler.  Also update to hold the youngest valid SN fetch has seen to ensure that the entire pipeline has been drained.
cpu/o3/fetch_impl.hh:
    Sampler updates.  Also be sure to not fetches to uncached space (bad path).
cpu/o3/iew.hh:
cpu/o3/iew_impl.hh:
    Sampler updates.
cpu/o3/lsq_unit_impl.hh:
    Supports checker.
cpu/o3/regfile.hh:
    No need for accessing xcProxies directly.
cpu/o3/rename.hh:
cpu/o3/rename_impl.hh:
    Sampler support.

--HG--
extra : convert_revision : 03881885dd50ebbca13ef31f31492fd4ef59121c
2006-05-16 14:06:35 -04:00
Kevin Lim
c23b23f4e7 Add in checker. Supports dynamically verifying the execution of instructions, as well as limited amount of control path verification. It will verify anything within the program, but anything external (traps, interrupts, XC) it assumes is redirected properly by the CPU. Similarly it assumes the results of store conditionals, uncached loads, and instructions marked as "unverifiable" are correct from the CPU.
base/traceflags.py:
build/SConstruct:
cpu/SConscript:
cpu/cpu_models.py:
    Add in Checker.
cpu/base.cc:
    Add in checker support.  Also XC status starts off as suspended.
cpu/base.hh:
    Add in checker.

--HG--
extra : convert_revision : 091b5cc83e837858adb681ef0137a0beb30bd1b2
2006-05-16 13:59:29 -04:00
Kevin Lim
bd88385034 Sampler updates.
--HG--
extra : convert_revision : 9f88846d3e91ba725e1c2e0107568ba0f21f4638
2006-05-16 13:52:03 -04:00
Kevin Lim
989cc1735e Sampling fixes related to the quiesce event.
cpu/cpu_exec_context.cc:
cpu/cpu_exec_context.hh:
    Sampling fixes.  The CPU models may switch during a quiesce period, so it needs to be sure to wake up the right XC.
cpu/exec_context.hh:
    Return the EndQuiesceEvent specifically.
sim/pseudo_inst.cc:
    Return the EndQuiesceEvent specifically for sampling.

--HG--
extra : convert_revision : f9aa1fc8d4db8058f05319cb6a3d4605ce93b4c8
2006-05-16 13:51:18 -04:00