sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity

Stats reset, profiling stuff.

Browse source 
cpu/base.cc:
    Be sure to deschedule the profile event so it doesn't take profiles while the CPU is switched out.

    Also include the option to reset stats at a specific instruction.
cpu/base.hh:
    Include the option to reset stats at a specific instruction.
cpu/checker/cpu_builder.cc:
    Handle stats reset inst.
cpu/o3/alpha_cpu_builder.cc:
    Handle stats reset inst, allow for profiling.
cpu/ozone/cpu_builder.cc:
    Handle profiling, stats reset event, slightly different parameters.
python/m5/objects/BaseCPU.py:
    Add in stats reset.

--HG--
extra : convert_revision : e27a78f7fb8fd19c53d9f2c1e6edce4a98cbafdb
This commit is contained in:
Kevin Lim 2006-08-24 16:06:45 -04:00
parent 4a2c50bc8f
commit 9fef4d4630
6 changed files with 58 additions and 7 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

29
cpu/base.cc
View file

@ -45,6 +45,9 @@
#include "base/trace.hh"
// Hack
#include "sim/stat_control.hh"
using namespace std;
vector<BaseCPU *> BaseCPU::cpuList;
@ -84,6 +87,7 @@ BaseCPU::BaseCPU(Params *p)
number_of_threads(p->numberOfThreads)
#endif
{
// currentTick = curTick;
DPRINTF(FullCPU, "BaseCPU: Creating object, mem address %#x.\n", this);
// add self to global list of CPUs
@ -145,6 +149,12 @@ BaseCPU::BaseCPU(Params *p)
p->max_loads_all_threads, *counter);
}
if (p->stats_reset_inst != 0) {
Stats::SetupEvent(Stats::Reset, p->stats_reset_inst, 0, comInstEventQueue[0]);
cprintf("Stats reset event scheduled for %lli insts\n",
p->stats_reset_inst);
}
#if FULL_SYSTEM
memset(interrupts, 0, sizeof(interrupts));
intstatus = 0;
@ -261,12 +271,17 @@ BaseCPU::registerExecContexts()
void
BaseCPU::switchOut(Sampler *sampler)
{
panic("This CPU doesn't support sampling!");
// panic("This CPU doesn't support sampling!");
#if FULL_SYSTEM
if (profileEvent && profileEvent->scheduled())
profileEvent->deschedule();
#endif
}
void
BaseCPU::takeOverFrom(BaseCPU *oldCPU)
{
// currentTick = oldCPU->currentTick;
assert(execContexts.size() == oldCPU->execContexts.size());
for (int i = 0; i < execContexts.size(); ++i) {
@ -281,18 +296,22 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
assert(newXC->getProcessPtr() == oldXC->getProcessPtr());
newXC->getProcessPtr()->replaceExecContext(newXC, newXC->readCpuId());
#endif
// TheISA::compareXCs(oldXC, newXC);
}
#if FULL_SYSTEM
for (int i = 0; i < TheISA::NumInterruptLevels; ++i)
interrupts[i] = oldCPU->interrupts[i];
intstatus = oldCPU->intstatus;
checkInterrupts = oldCPU->checkInterrupts;
for (int i = 0; i < execContexts.size(); ++i)
execContexts[i]->profileClear();
// for (int i = 0; i < execContexts.size(); ++i)
// execContexts[i]->profileClear();
if (profileEvent)
profileEvent->schedule(curTick);
// The Sampler must take care of this!
// if (profileEvent)
// profileEvent->schedule(curTick);
#endif
}

3
cpu/base.hh
View file

@ -67,9 +67,11 @@ class BaseCPU : public SimObject
Tick clock;
public:
// Tick currentTick;
inline Tick frequency() const { return Clock::Frequency / clock; }
inline Tick cycles(int numCycles) const { return clock * numCycles; }
inline Tick curCycle() const { return curTick / clock; }
// inline Tick curCycle() { currentTick+=10000; return currentTick; }
#if FULL_SYSTEM
protected:
@ -134,6 +136,7 @@ class BaseCPU : public SimObject
Counter max_insts_all_threads;
Counter max_loads_any_thread;
Counter max_loads_all_threads;
Counter stats_reset_inst;
Tick clock;
bool functionTrace;
Tick functionTraceStart;

5
cpu/checker/cpu_builder.cc
View file

@ -58,6 +58,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(OzoneChecker)
Param<Counter> max_insts_all_threads;
Param<Counter> max_loads_any_thread;
Param<Counter> max_loads_all_threads;
Param<Counter> stats_reset_inst;
Param<Tick> progress_interval;
#if FULL_SYSTEM
@ -92,6 +93,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(OzoneChecker)
"terminate when any thread reaches this load count"),
INIT_PARAM(max_loads_all_threads,
"terminate when all threads have reached this load count"),
INIT_PARAM(stats_reset_inst,
"blah"),
INIT_PARAM_DFLT(progress_interval, "CPU Progress Interval", 0),
#if FULL_SYSTEM
@ -127,6 +130,7 @@ CREATE_SIM_OBJECT(OzoneChecker)
params->max_insts_all_threads = 0;
params->max_loads_any_thread = 0;
params->max_loads_all_threads = 0;
params->stats_reset_inst = 0;
params->exitOnError = exitOnError;
params->updateOnError = updateOnError;
params->deferRegistration = defer_registration;
@ -142,6 +146,7 @@ CREATE_SIM_OBJECT(OzoneChecker)
temp = max_loads_all_threads;
Tick temp2 = progress_interval;
temp2++;
params->progress_interval = 0;
BaseMem *cache = icache;
cache = dcache;

8
cpu/o3/alpha_cpu_builder.cc
View file

@ -55,6 +55,7 @@ SimObjectParam<System *> system;
Param<int> cpu_id;
SimObjectParam<AlphaITB *> itb;
SimObjectParam<AlphaDTB *> dtb;
Param<Tick> profile;
#else
SimObjectVectorParam<Process *> workload;
//SimObjectParam<PageTable *> page_table;
@ -68,6 +69,7 @@ Param<Counter> max_insts_any_thread;
Param<Counter> max_insts_all_threads;
Param<Counter> max_loads_any_thread;
Param<Counter> max_loads_all_threads;
Param<Counter> stats_reset_inst;
Param<Tick> progress_interval;
SimObjectParam<BaseCache *> icache;
@ -167,6 +169,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivAlphaFullCPU)
INIT_PARAM(cpu_id, "processor ID"),
INIT_PARAM(itb, "Instruction translation buffer"),
INIT_PARAM(dtb, "Data translation buffer"),
INIT_PARAM(profile, ""),
#else
INIT_PARAM(workload, "Processes to run"),
// INIT_PARAM(page_table, "Page table"),
@ -190,6 +193,9 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivAlphaFullCPU)
"Terminate when all threads have reached this load"
"count",
0),
INIT_PARAM_DFLT(stats_reset_inst,
"blah",
0),
INIT_PARAM_DFLT(progress_interval, "Progress interval", 0),
INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL),
@ -316,6 +322,7 @@ CREATE_SIM_OBJECT(DerivAlphaFullCPU)
params->cpu_id = cpu_id;
params->itb = itb;
params->dtb = dtb;
params->profile = profile;
#else
params->workload = workload;
// params->pTable = page_table;
@ -329,6 +336,7 @@ CREATE_SIM_OBJECT(DerivAlphaFullCPU)
params->max_insts_all_threads = max_insts_all_threads;
params->max_loads_any_thread = max_loads_any_thread;
params->max_loads_all_threads = max_loads_all_threads;
params->stats_reset_inst = stats_reset_inst;
params->progress_interval = progress_interval;
//

18
cpu/ozone/cpu_builder.cc
View file

@ -71,6 +71,7 @@ SimObjectParam<System *> system;
Param<int> cpu_id;
SimObjectParam<AlphaITB *> itb;
SimObjectParam<AlphaDTB *> dtb;
Param<Tick> profile;
#else
SimObjectVectorParam<Process *> workload;
//SimObjectParam<PageTable *> page_table;
@ -84,6 +85,7 @@ Param<Counter> max_insts_any_thread;
Param<Counter> max_insts_all_threads;
Param<Counter> max_loads_any_thread;
Param<Counter> max_loads_all_threads;
Param<Counter> stats_reset_inst;
Param<Tick> progress_interval;
SimObjectParam<BaseCache *> icache;
@ -91,10 +93,11 @@ SimObjectParam<BaseCache *> dcache;
Param<unsigned> cachePorts;
Param<unsigned> width;
Param<unsigned> frontEndLatency;
Param<unsigned> frontEndWidth;
Param<unsigned> backEndLatency;
Param<unsigned> backEndWidth;
Param<unsigned> backEndSquashLatency;
Param<unsigned> backEndLatency;
Param<unsigned> maxInstBufferSize;
Param<unsigned> numPhysicalRegs;
Param<unsigned> maxOutstandingMemOps;
@ -149,6 +152,7 @@ Param<unsigned> RASSize;
Param<unsigned> LQEntries;
Param<unsigned> SQEntries;
Param<bool> lsqLimits;
Param<unsigned> LFSTSize;
Param<unsigned> SSITSize;
@ -190,6 +194,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU)
INIT_PARAM(cpu_id, "processor ID"),
INIT_PARAM(itb, "Instruction translation buffer"),
INIT_PARAM(dtb, "Data translation buffer"),
INIT_PARAM(profile, ""),
#else
INIT_PARAM(workload, "Processes to run"),
// INIT_PARAM(page_table, "Page table"),
@ -213,6 +218,9 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU)
"Terminate when all threads have reached this load"
"count",
0),
INIT_PARAM_DFLT(stats_reset_inst,
"blah",
0),
INIT_PARAM_DFLT(progress_interval, "Progress interval", 0),
INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL),
@ -220,10 +228,11 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU)
INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
INIT_PARAM_DFLT(width, "Width", 1),
INIT_PARAM_DFLT(frontEndLatency, "Front end latency", 1),
INIT_PARAM_DFLT(frontEndWidth, "Front end width", 1),
INIT_PARAM_DFLT(backEndLatency, "Back end latency", 1),
INIT_PARAM_DFLT(backEndWidth, "Back end width", 1),
INIT_PARAM_DFLT(backEndSquashLatency, "Back end squash latency", 1),
INIT_PARAM_DFLT(backEndLatency, "Back end latency", 1),
INIT_PARAM_DFLT(maxInstBufferSize, "Maximum instruction buffer size", 16),
INIT_PARAM(numPhysicalRegs, "Number of physical registers"),
INIT_PARAM_DFLT(maxOutstandingMemOps, "Maximum outstanding memory operations", 4),
@ -284,6 +293,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU)
INIT_PARAM(LQEntries, "Number of load queue entries"),
INIT_PARAM(SQEntries, "Number of store queue entries"),
INIT_PARAM_DFLT(lsqLimits, "LSQ size limits dispatch", true),
INIT_PARAM(LFSTSize, "Last fetched store table size"),
INIT_PARAM(SSITSize, "Store set ID table size"),
@ -346,6 +356,7 @@ CREATE_SIM_OBJECT(DerivOzoneCPU)
params->cpu_id = cpu_id;
params->itb = itb;
params->dtb = dtb;
params->profile = profile;
#else
params->workload = workload;
// params->pTable = page_table;
@ -357,6 +368,7 @@ CREATE_SIM_OBJECT(DerivOzoneCPU)
params->max_insts_all_threads = max_insts_all_threads;
params->max_loads_any_thread = max_loads_any_thread;
params->max_loads_all_threads = max_loads_all_threads;
params->stats_reset_inst = stats_reset_inst;
params->progress_interval = progress_interval;
//
@ -368,6 +380,7 @@ CREATE_SIM_OBJECT(DerivOzoneCPU)
params->width = width;
params->frontEndWidth = frontEndWidth;
params->frontEndLatency = frontEndLatency;
params->backEndWidth = backEndWidth;
params->backEndSquashLatency = backEndSquashLatency;
params->backEndLatency = backEndLatency;
@ -425,6 +438,7 @@ CREATE_SIM_OBJECT(DerivOzoneCPU)
params->LQEntries = LQEntries;
params->SQEntries = SQEntries;
params->lsqLimits = lsqLimits;
params->SSITSize = SSITSize;
params->LFSTSize = LFSTSize;

2
python/m5/objects/BaseCPU.py
View file

@ -22,6 +22,8 @@ class BaseCPU(SimObject):
"terminate when all threads have reached this load count")
max_loads_any_thread = Param.Counter(0,
"terminate when any thread reaches this load count")
stats_reset_inst = Param.Counter(0,
"reset stats once this many instructions are committed")
progress_interval = Param.Tick(0, "interval to print out the progress message")
defer_registration = Param.Bool(False,