Update checker.

cpu/checker/cpu.cc:
    Print better error messages.
cpu/checker/cpu.hh:
    Fix up small bug (similar to Ozone's DynInsts with FPs and float/doubles), output better messages.

--HG--
extra : convert_revision : 0e199b3dbbcdb5917cdfbebb4c5c18e4b9056c86

cpu/checker/cpu.cc

@@ -410,6 +410,14 @@ CheckerCPU::checkFlags(MemReqPtr &req)
     }
 }
 
+void
+CheckerCPU::dumpAndExit()
+{
+    warn("%lli: Checker PC:%#x, next PC:%#x",
+         curTick, cpuXC->readPC(), cpuXC->readNextPC());
+    panic("Checker found an error!");
+}
+
 template <class DynInstPtr>
 void
 Checker<DynInstPtr>::tick(DynInstPtr &completed_inst)
@@ -487,7 +495,7 @@ Checker<DynInstPtr>::tick(DynInstPtr &completed_inst)
                     warn("%lli: Changed PC does not match expected PC, "
                          "changed: %#x, expected: %#x",
                          curTick, cpuXC->readPC(), newPC);
-                    handleError();
+                    CheckerCPU::handleError();
                 }
                 willChangePC = false;
             }
@@ -523,7 +531,7 @@ Checker<DynInstPtr>::tick(DynInstPtr &completed_inst)
                 // possible that its ITB entry was kicked out.
                 warn("%lli: Instruction PC %#x was not found in the ITB!",
                      curTick, cpuXC->readPC());
-                handleError();
+                handleError(inst);
 
                 // go to the next instruction
                 cpuXC->setPC(cpuXC->readNextPC());
@@ -661,7 +669,7 @@ Checker<DynInstPtr>::validateInst(DynInstPtr &inst)
             warn("%lli: Changed PCs recently, may not be an error",
                  curTick);
         } else {
-            handleError();
+            handleError(inst);
         }
     }
 
@@ -671,7 +679,7 @@ Checker<DynInstPtr>::validateInst(DynInstPtr &inst)
         warn("%lli: Binary instructions do not match! Inst: %#x, "
              "checker: %#x",
              curTick, mi, machInst);
-        handleError();
+        handleError(inst);
     }
 }
 
@@ -697,7 +705,7 @@ Checker<DynInstPtr>::validateExecution(DynInstPtr &inst)
             warn("%lli: Instruction results do not match! (Results may not "
                  "actually be integers) Inst: %#x, checker: %#x",
                  curTick, inst->readIntResult(), result.integer);
-            handleError();
+            handleError(inst);
         }
     }
 
@@ -705,7 +713,7 @@ Checker<DynInstPtr>::validateExecution(DynInstPtr &inst)
         warn("%lli: Instruction next PCs do not match! Inst: %#x, "
              "checker: %#x",
              curTick, inst->readNextPC(), cpuXC->readNextPC());
-        handleError();
+        handleError(inst);
     }
 
     // Checking side effect registers can be difficult if they are not
@@ -724,7 +732,7 @@ Checker<DynInstPtr>::validateExecution(DynInstPtr &inst)
                  curTick, misc_reg_idx,
                  inst->xcBase()->readMiscReg(misc_reg_idx),
                  cpuXC->readMiscReg(misc_reg_idx));
-            handleError();
+            handleError(inst);
         }
     }
 }
@@ -753,6 +761,22 @@ Checker<DynInstPtr>::validateState()
     }
 }
 
+template <class DynInstPtr>
+void
+Checker<DynInstPtr>::dumpAndExit(DynInstPtr &inst)
+{
+    cprintf("Error detected, instruction information:\n");
+    cprintf("PC:%#x, nextPC:%#x\n[sn:%lli]\n[tid:%i]\n"
+            "Completed:%i\n",
+            inst->readPC(),
+            inst->readNextPC(),
+            inst->seqNum,
+            inst->threadNumber,
+            inst->isCompleted());
+    inst->dump();
+    CheckerCPU::dumpAndExit();
+}
+
 template <class DynInstPtr>
 void
 Checker<DynInstPtr>::dumpInsts()

cpu/checker/cpu.hh

@@ -129,7 +129,7 @@ class CheckerCPU : public BaseCPU
 
     union Result {
         uint64_t integer;
-        float fp;
+//        float fp;
         double dbl;
     };
 
@@ -230,7 +230,7 @@ class CheckerCPU : public BaseCPU
     {
         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
         cpuXC->setFloatRegSingle(reg_idx, val);
-        result.fp = val;
+        result.dbl = (double)val;
     }
 
     void setFloatRegDouble(const StaticInst *si, int idx, double val)
@@ -275,7 +275,7 @@ class CheckerCPU : public BaseCPU
         return cpuXC->setMiscRegWithEffect(misc_reg, val);
     }
 
-    void recordPCChange(uint64_t val) { changedPC = true; }
+    void recordPCChange(uint64_t val) { changedPC = true; newPC = val; }
     void recordNextPCChange(uint64_t val) { changedNextPC = true; }
 
     bool translateInstReq(MemReqPtr &req);
@@ -295,10 +295,16 @@ class CheckerCPU : public BaseCPU
     void syscall() { }
 #endif
 
-    virtual void handleError() = 0;
+    void handleError()
+    {
+        if (exitOnError)
+            dumpAndExit();
+    }
 
     bool checkFlags(MemReqPtr &req);
 
+    void dumpAndExit();
+
     ExecContext *xcBase() { return xcProxy; }
     CPUExecContext *cpuXCBase() { return cpuXC; }
 
@@ -338,14 +344,17 @@ class Checker : public CheckerCPU
     void validateExecution(DynInstPtr &inst);
     void validateState();
 
-    virtual void handleError()
+    void handleError(DynInstPtr &inst)
     {
-        if (exitOnError)
-            panic("Checker found error!");
-        else if (updateOnError)
+        if (exitOnError) {
+            dumpAndExit(inst);
+        } else if (updateOnError) {
             updateThisCycle = true;
+        }
     }
 
+    void dumpAndExit(DynInstPtr &inst);
+
     bool updateThisCycle;
 
     DynInstPtr unverifiedInst;