arch/alpha/isa/decoder.isa:
Mark store conditionals as serializing. This is slightly higher over head than they truly have in the 264, but it's close. Normally they block any other instructions from entering the IQ until the IQ is empty. This is higher overhead because it waits until the ROB is empty.
Also mark RPCC as unverifiable. The checker will just grab the value from the instruction and assume it's correct.
cpu/static_inst.hh:
Add unverifiable flag, specifically for the CheckerCPU.
--HG--
extra : convert_revision : cbc34d1f2f5b07105d31d4bd8f19edae2cf8158e
cpu/base_dyn_inst.hh:
Remove snoop function (did not mean to commit it).
cpu/ozone/back_end_impl.hh:
Set instruction as having its result ready, not completed.
cpu/ozone/cpu.hh:
Fixes for store conditionals. Use an additional lock addr list to make sure that the access is valid. I don't know if this is fully necessary, but it gives me a peace of mind (at some performance cost).
Make sure to schedule for cycles(1) and not just 1 cycle in the future as tick = 1ps.
Also support the new Checker.
cpu/ozone/cpu_builder.cc:
Add parameter for maxOutstandingMemOps so it can be set through the config.
Also add in the checker. Right now it's a BaseCPU simobject, but that may change in the future.
cpu/ozone/cpu_impl.hh:
Add support for the checker. For now there's a dynamic cast to convert the simobject passed back from the builder to the proper Checker type. It's ugly, but only happens at startup, and is probably a justified use of dynamic cast.
Support switching out/taking over from other CPUs.
Correct indexing problem for float registers.
cpu/ozone/dyn_inst.hh:
Add ability for instructions to wait on memory instructions in addition to source register instructions. This is needed for memory dependence predictors and memory barriers.
cpu/ozone/dyn_inst_impl.hh:
Support waiting on memory operations.
Use "resultReady" to differentiate an instruction having its registers produced vs being totally completed.
cpu/ozone/front_end.hh:
Support switching out.
Also record if an interrupt is pending.
cpu/ozone/front_end_impl.hh:
Support switching out. Also support stalling the front end if an interrupt is pending.
cpu/ozone/lw_back_end.hh:
Add checker in.
Support switching out.
Support memory barriers.
cpu/ozone/lw_back_end_impl.hh:
Lots of changes to get things to work right.
Faults, traps, interrupts all wait until all stores have written back (important).
Memory barriers are supported, as is the general ability for instructions to be dependent on other memory instructions.
cpu/ozone/lw_lsq.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
cpu/ozone/lw_lsq_impl.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
Support the checker CPU. Marks instructions as completed once the functional access is done (which has to be done for the checker to be able to verify results).
cpu/ozone/simple_params.hh:
Add max outstanding mem ops parameter.
python/m5/objects/OzoneCPU.py:
Add max outstanding mem ops, checker.
--HG--
extra : convert_revision : f4d408e1bb1f25836a097b6abe3856111e950c59
cpu/o3/alpha_dyn_inst.hh:
Set the instResult using a function on the base dyn inst.
cpu/o3/bpred_unit_impl.hh:
Don't need to reset the state.
cpu/o3/commit_impl.hh:
Mark instructions as completed.
Wait until all stores are written back to handle a fault.
cpu/o3/cpu.cc:
Clear instruction lists when switching out.
cpu/o3/lsq_unit.hh:
Allow wbEvent to be set externally.
cpu/o3/lsq_unit_impl.hh:
Mark instructions as completed properly. Also use events for writing back stores even if there is a hit in the dcache.
--HG--
extra : convert_revision : 172ad088b75ac31e848a5040633152b5c051444c
cpu/simple/cpu.cc:
Sampler fixes. The status may be switched out when calling activate or suspend if there is a switchover during a quiesce.
--HG--
extra : convert_revision : da026e75dfb86289484cf01c5b1ecd9b03a72bd3
util/stats/barchart.py:
- there is no self.inner_axes
- don't append an empty value to self.xsubticks, otherwise
subsequent calls will get extra empty ticks
- rotate labels 30 degrees instead of 90 so it looks better
--HG--
extra : convert_revision : 1cbac6d1f92bfc6b2c1e886ad5f9d4c78a2b3820
dev/sinic.cc:
- Size the virtualRegs array based on the configured value
- Add debugging stuff for uniquely identifying vnic usage
- Only count totally unprocessed packets when notifying via RxDone
- Add initial virtual address support
- Fix some bugs in accessing packets out of order to make sure that
busy packets are processed first
- Add fifo watermark stuff
- Make number of vnics, zero/delay copy and watermarks parameters
dev/sinic.hh:
add rxUnique and txUnique to uniquely identify tx and rx VNICs
Create a separate list of Busy VNICs since more than one might
be busy and we want to service those first
Add more watermark stuff and new parameters
dev/sinicreg.hh:
Make the number of virtual nics a read-only parameter
add bits for ZeroCopy/DelayCopy
rename Virtual to Vaddr so it's not ambiguous
Add a flag for TxData/RxData to indicate a virtual address
Report rxfifo status in RxDone
python/m5/objects/Ethernet.py:
add more options for the fifo thresholds
add number of vnics as a parameter
add copy type as a parameter
add virtual addressing as a parameter
--HG--
extra : convert_revision : 850e2433b585d65469d4c5d85ad7ca820db10f4a
cpu/ozone/cpu.hh:
Add quiesce stat (not clear how it should be used yet).
cpu/ozone/cpu_impl.hh:
Fix for quiesce.
--HG--
extra : convert_revision : a1998818e241374ae3f4c3cabbef885dda55c884
cpu/o3/alpha_cpu.hh:
Store conditionals should not write their data to memory if they failed.
cpu/o3/lsq_unit.hh:
Setup request parameters when they're needed.
--HG--
extra : convert_revision : d75cd7deda03584b7e25cb567e4d79032cac7118
cpu/static_inst.hh:
Updates for new CPU, also include a classification of quiesce instructions.
--HG--
extra : convert_revision : a34cd56da88fe57d7de24674fbb375bbf13f887f
cpu/exec_context.hh:
Remove functions that shouldn't be accessible to anything outside of the CPU.
--HG--
extra : convert_revision : 9793c3ceb6d5404484bafc7a75d75ed71815d9eb
build/SConstruct:
Include Ozone CPU models.
cpu/cpu_models.py:
Include OzoneCPU models.
--HG--
extra : convert_revision : 51a016c216cacd2cc613eed79653026c2edda4b3
arch/alpha/isa/decoder.isa:
Make IPR accessing instructions serializing so they are not issued incorrectly in the O3 model.
arch/alpha/isa/pal.isa:
Allow IPR instructions to have flags.
base/traceflags.py:
Include new trace flags from the two new CPU models.
cpu/SConscript:
Create the templates for the split mem accessor methods. Also include the new files from the new models (the Ozone model will be checked in next).
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
Update to the BaseDynInst for the new models.
--HG--
extra : convert_revision : cc82db9c72ec3e29cea4c3fdff74a3843e287a35
To run it use
-ETEST=POVRAY_BENCH to run the built in povray benchmark program (more CPU intensive, small fileset ~11MB)
-ETEST=POVRAY_AUTUMN to run the first part of a rendering of a autumn leaves/tree scene, less cpu intensive ~500MB working set.
For now I have been running with -ESYSTEM=Simple in order to drop checkpoints (built into binary at the point the render begins) and create memory traces.
I will check in a SYSTEM=3D_DRAM and SYSTEM=3D_CACHE configuration as soon as those are ready.
--HG--
extra : convert_revision : fb55834a02317d5e9961a5145c932965c8bc6a0e
Add some forward declerations.
Fix ordering problem of variables in constructor (see sourceforge)
Factor out code from header into _impl file to speed building process (keep cache_builder smaller in size)
--HG--
extra : convert_revision : 20087f88f95628af716094e09c2287e09580149e
an obsolete function that doesn't exist.
arch/alpha/tru64/process.cc:
sim/process.cc:
Don't include useless header.
--HG--
extra : convert_revision : 1dd5edeb0703e2190b89ea5ff563df4c95b7cf59
arch/alpha/isa_traits.hh:
arch/sparc/linux/process.cc:
fix merging problem
sim/syscall_emul.cc:
use setIntReg
--HG--
extra : convert_revision : e88d72e415493cd17d7b88c22c7e995f3199e396
