Updates to Ozone model for quiesce, store conditionals.
--HG-- extra : convert_revision : 72ddd75ad0b5783aca9484e7d178c2915ee8e355
This commit is contained in:
parent
676afbe2c7
commit
e704960c80
9 changed files with 272 additions and 116 deletions
122
cpu/ozone/cpu.hh
122
cpu/ozone/cpu.hh
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@ -42,7 +42,6 @@
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#include "cpu/pc_event.hh"
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#include "cpu/static_inst.hh"
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#include "mem/mem_interface.hh"
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#include "mem/page_table.hh"
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#include "sim/eventq.hh"
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// forward declarations
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@ -59,7 +58,6 @@ class GDBListener;
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#else
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class PageTable;
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class Process;
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#endif // FULL_SYSTEM
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@ -349,9 +347,8 @@ class OzoneCPU : public BaseCPU
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// L1 data cache
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MemInterface *dcacheInterface;
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#if !FULL_SYSTEM
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PageTable *pTable;
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#endif
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/** Pointer to memory. */
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FunctionalMemory *mem;
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FrontEnd *frontEnd;
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@ -428,24 +425,62 @@ class OzoneCPU : public BaseCPU
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int getInstAsid() { return thread.asid; }
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int getDataAsid() { return thread.asid; }
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Fault dummyTranslation(MemReqPtr &req)
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{
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#if 0
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assert((req->vaddr >> 48 & 0xffff) == 0);
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#endif
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// put the asid in the upper 16 bits of the paddr
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req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
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req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
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return NoFault;
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}
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/** Translates instruction requestion in syscall emulation mode. */
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Fault translateInstReq(MemReqPtr &req)
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{
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return this->pTable->translate(req);
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return dummyTranslation(req);
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}
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/** Translates data read request in syscall emulation mode. */
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Fault translateDataReadReq(MemReqPtr &req)
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{
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return this->pTable->translate(req);
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return dummyTranslation(req);
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}
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/** Translates data write request in syscall emulation mode. */
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Fault translateDataWriteReq(MemReqPtr &req)
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{
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return this->pTable->translate(req);
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return dummyTranslation(req);
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}
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#endif
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/** Old CPU read from memory function. No longer used. */
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template <class T>
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Fault read(MemReqPtr &req, T &data)
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{
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// panic("CPU READ NOT IMPLEMENTED W/NEW MEMORY\n");
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#if 0
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#if FULL_SYSTEM && defined(TARGET_ALPHA)
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if (req->flags & LOCKED) {
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req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
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req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
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}
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#endif
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#endif
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Fault error;
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if (req->flags & LOCKED) {
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// lockAddr = req->paddr;
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lockFlag = true;
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}
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error = this->mem->read(req, data);
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data = gtoh(data);
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return error;
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}
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/** CPU read function, forwards read to LSQ. */
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template <class T>
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Fault read(MemReqPtr &req, T &data, int load_idx)
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@ -453,6 +488,75 @@ class OzoneCPU : public BaseCPU
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return backEnd->read(req, data, load_idx);
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}
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/** Old CPU write to memory function. No longer used. */
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template <class T>
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Fault write(MemReqPtr &req, T &data)
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{
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#if 0
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#if FULL_SYSTEM && defined(TARGET_ALPHA)
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ExecContext *xc;
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// If this is a store conditional, act appropriately
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if (req->flags & LOCKED) {
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xc = req->xc;
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if (req->flags & UNCACHEABLE) {
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// Don't update result register (see stq_c in isa_desc)
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req->result = 2;
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xc->setStCondFailures(0);//Needed? [RGD]
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} else {
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bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
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Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
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req->result = lock_flag;
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if (!lock_flag ||
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((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
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xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
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xc->setStCondFailures(xc->readStCondFailures() + 1);
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if (((xc->readStCondFailures()) % 100000) == 0) {
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std::cerr << "Warning: "
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<< xc->readStCondFailures()
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<< " consecutive store conditional failures "
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<< "on cpu " << req->xc->readCpuId()
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<< std::endl;
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}
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return NoFault;
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}
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else xc->setStCondFailures(0);
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}
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}
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// Need to clear any locked flags on other proccessors for
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// this address. Only do this for succsful Store Conditionals
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// and all other stores (WH64?). Unsuccessful Store
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// Conditionals would have returned above, and wouldn't fall
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// through.
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for (int i = 0; i < this->system->execContexts.size(); i++){
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xc = this->system->execContexts[i];
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if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
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(req->paddr & ~0xf)) {
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xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
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}
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}
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#endif
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#endif
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if (req->flags & LOCKED) {
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if (req->flags & UNCACHEABLE) {
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req->result = 2;
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} else {
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if (this->lockFlag/* && this->lockAddr == req->paddr*/) {
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req->result = 1;
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} else {
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req->result = 0;
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return NoFault;
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}
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}
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}
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return this->mem->write(req, (T)htog(data));
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}
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/** CPU write function, forwards write to LSQ. */
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template <class T>
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Fault write(MemReqPtr &req, T &data, int store_idx)
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@ -507,6 +611,8 @@ class OzoneCPU : public BaseCPU
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bool stall;
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};
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TimeBuffer<CommStruct> comm;
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bool lockFlag;
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};
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#endif // __CPU_OZONE_CPU_HH__
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@ -149,12 +149,14 @@ OzoneCPU<Impl>::DCacheCompletionEvent::description()
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template <class Impl>
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OzoneCPU<Impl>::OzoneCPU(Params *p)
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#if FULL_SYSTEM
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: BaseCPU(p), thread(this, 0, p->mem), tickEvent(this, p->width),
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: BaseCPU(p), thread(this, 0, p->mem), tickEvent(this, p->width), mem(p->mem),
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#else
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: BaseCPU(p), thread(this, 0, p->workload[0], 0), tickEvent(this, p->width),
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mem(p->workload[0]->getMemory()),
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#endif
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comm(5, 5)
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{
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frontEnd = new FrontEnd(p);
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backEnd = new BackEnd(p);
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@ -245,51 +247,7 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
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globalSeqNum = 1;
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checkInterrupts = false;
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/*
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fetchRedirBranch = true;
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fetchRedirExcp = true;
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// Need to initialize the rename maps, and the head and tail pointers.
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robHeadPtr = new DynInst(this);
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robTailPtr = new DynInst(this);
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robHeadPtr->setNextInst(robTailPtr);
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// robHeadPtr->setPrevInst(NULL);
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// robTailPtr->setNextInst(NULL);
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robTailPtr->setPrevInst(robHeadPtr);
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robHeadPtr->setCompleted();
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robTailPtr->setCompleted();
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for (int i = 0; i < ISA::TotalNumRegs; ++i) {
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renameTable[i] = new DynInst(this);
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commitTable[i] = new DynInst(this);
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renameTable[i]->setCompleted();
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commitTable[i]->setCompleted();
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}
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#if FULL_SYSTEM
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for (int i = 0; i < ISA::NumIntRegs; ++i) {
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palShadowTable[i] = new DynInst(this);
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palShadowTable[i]->setCompleted();
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}
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#endif
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// Size of cache block.
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cacheBlkSize = icacheInterface ? icacheInterface->getBlockSize() : 64;
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// Create mask to get rid of offset bits.
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cacheBlkMask = (cacheBlkSize - 1);
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// Get the size of an instruction.
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instSize = sizeof(MachInst);
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// Create space to store a cache line.
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cacheData = new uint8_t[cacheBlkSize];
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cacheBlkValid = false;
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*/
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for (int i = 0; i < TheISA::TotalNumRegs; ++i) {
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thread.renameTable[i] = new DynInst(this);
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thread.renameTable[i]->setCompleted();
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@ -299,9 +257,11 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
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backEnd->renameTable.copyFrom(thread.renameTable);
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#if !FULL_SYSTEM
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pTable = p->pTable;
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// pTable = p->pTable;
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#endif
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lockFlag = 0;
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DPRINTF(OzoneCPU, "OzoneCPU: Created Ozone cpu object.\n");
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}
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@ -392,6 +352,7 @@ OzoneCPU<Impl>::activateContext(int thread_num, int delay)
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scheduleTickEvent(delay);
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_status = Running;
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thread._status = ExecContext::Active;
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frontEnd->wakeFromQuiesce();
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}
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template <class Impl>
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@ -401,8 +362,8 @@ OzoneCPU<Impl>::suspendContext(int thread_num)
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// Eventually change this in SMT.
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assert(thread_num == 0);
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// assert(xcProxy);
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assert(_status == Running);
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// @todo: Figure out how to initially set the status properly so this is running.
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// assert(_status == Running);
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notIdleFraction--;
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unscheduleTickEvent();
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_status = Idle;
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@ -665,6 +626,7 @@ OzoneCPU<Impl>::tick()
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{
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DPRINTF(OzoneCPU, "\n\nOzoneCPU: Ticking cpu.\n");
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_status = Running;
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thread.renameTable[ZeroReg]->setIntResult(0);
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thread.renameTable[ZeroReg+TheISA::FP_Base_DepTag]->
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setDoubleResult(0.0);
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@ -756,7 +718,7 @@ OzoneCPU<Impl>::tick()
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// check for instruction-count-based events
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comInstEventQueue[0]->serviceEvents(numInst);
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if (!tickEvent.scheduled())
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if (!tickEvent.scheduled() && _status == Running)
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tickEvent.schedule(curTick + 1);
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}
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@ -821,6 +783,8 @@ OzoneCPU<Impl>::hwrei()
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thread.setNextPC(thread.readMiscReg(AlphaISA::IPR_EXC_ADDR));
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lockFlag = false;
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// Not sure how to make a similar check in the Ozone model
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// if (!misspeculating()) {
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kernelStats->hwrei();
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@ -237,6 +237,7 @@ OzoneDynInst<Impl>::hwrei()
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this->cpu->kernelStats->hwrei();
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this->cpu->checkInterrupts = true;
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this->cpu->lockFlag = false;
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// FIXME: XXX check for interrupts? XXX
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return NoFault;
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@ -60,7 +60,7 @@ class FrontEnd
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const bool is_branch = false, const bool branch_taken = false);
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DynInstPtr getInst();
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void processCacheCompletion();
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void processCacheCompletion(MemReqPtr &req);
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void addFreeRegs(int num_freed);
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@ -109,6 +109,7 @@ class FrontEnd
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SerializeBlocked,
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SerializeComplete,
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RenameBlocked,
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QuiescePending,
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BEBlocked
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};
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@ -130,17 +131,16 @@ class FrontEnd
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class ICacheCompletionEvent : public Event
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{
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private:
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MemReqPtr req;
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FrontEnd *frontEnd;
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public:
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ICacheCompletionEvent(FrontEnd *_fe);
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ICacheCompletionEvent(MemReqPtr &_req, FrontEnd *_fe);
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virtual void process();
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virtual const char *description();
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};
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ICacheCompletionEvent cacheCompletionEvent;
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MemInterface *icacheInterface;
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#if !FULL_SYSTEM
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@ -174,6 +174,8 @@ class FrontEnd
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void setPC(Addr val) { PC = val; }
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void setNextPC(Addr val) { nextPC = val; }
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void wakeFromQuiesce();
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void dumpInsts();
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private:
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@ -1,4 +1,5 @@
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#include "arch/faults.hh"
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#include "arch/isa_traits.hh"
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#include "base/statistics.hh"
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#include "cpu/exec_context.hh"
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@ -12,7 +13,6 @@ using namespace TheISA;
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template <class Impl>
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FrontEnd<Impl>::FrontEnd(Params *params)
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: branchPred(params),
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cacheCompletionEvent(this),
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icacheInterface(params->icacheInterface),
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instBufferSize(0),
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maxInstBufferSize(params->maxInstBufferSize),
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@ -26,10 +26,12 @@ FrontEnd<Impl>::FrontEnd(Params *params)
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// Setup branch predictor.
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// Setup Memory Request
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/*
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memReq = new MemReq();
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memReq->asid = 0;
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memReq->data = new uint8_t[64];
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*/
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memReq = NULL;
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// Size of cache block.
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cacheBlkSize = icacheInterface ? icacheInterface->getBlockSize() : 64;
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cacheBlkValid = false;
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#if !FULL_SYSTEM
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pTable = params->pTable;
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// pTable = params->pTable;
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#endif
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fetchFault = NoFault;
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}
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@ -72,7 +74,7 @@ void
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FrontEnd<Impl>::setXC(ExecContext *xc_ptr)
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{
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xc = xc_ptr;
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memReq->xc = xc;
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// memReq->xc = xc;
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}
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template <class Impl>
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@ -269,6 +271,9 @@ FrontEnd<Impl>::tick()
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}
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updateStatus();
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return;
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} else if (status == QuiescePending) {
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DPRINTF(FE, "Waiting for quiesce to execute or get squashed.\n");
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return;
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} else if (status != IcacheMissComplete) {
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if (fetchCacheLineNextCycle) {
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Fault fault = fetchCacheLine();
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@ -325,6 +330,14 @@ FrontEnd<Impl>::tick()
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// rename(num_inst);
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// }
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#if FULL_SYSTEM
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if (inst->isQuiesce()) {
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warn("%lli: Quiesce instruction encountered, halting fetch!", curTick);
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status = QuiescePending;
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break;
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}
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#endif
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if (inst->predTaken()) {
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// Start over with tick?
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break;
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@ -364,6 +377,12 @@ FrontEnd<Impl>::fetchCacheLine()
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// Setup the memReq to do a read of the first isntruction's address.
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// Set the appropriate read size and flags as well.
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memReq = new MemReq();
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memReq->asid = 0;
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memReq->thread_num = 0;
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memReq->data = new uint8_t[64];
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memReq->xc = xc;
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memReq->cmd = Read;
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memReq->reset(fetch_PC, cacheBlkSize, flags);
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@ -377,16 +396,26 @@ FrontEnd<Impl>::fetchCacheLine()
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// Now do the timing access to see whether or not the instruction
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// exists within the cache.
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if (icacheInterface && fault == NoFault) {
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#if FULL_SYSTEM
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if (cpu->system->memctrl->badaddr(memReq->paddr)) {
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DPRINTF(FE, "Fetch: Bad address %#x (hopefully on a "
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"misspeculating path!",
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memReq->paddr);
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return TheISA::genMachineCheckFault();
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}
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#endif
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memReq->completionEvent = NULL;
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memReq->time = curTick;
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fault = cpu->mem->read(memReq, cacheData);
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MemAccessResult res = icacheInterface->access(memReq);
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// If the cache missed then schedule an event to wake
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// up this stage once the cache miss completes.
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if (icacheInterface->doEvents() && res != MA_HIT) {
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memReq->completionEvent = new ICacheCompletionEvent(this);
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memReq->completionEvent = new ICacheCompletionEvent(memReq, this);
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status = IcacheMissStall;
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@ -398,7 +427,7 @@ FrontEnd<Impl>::fetchCacheLine()
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cacheBlkValid = true;
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memcpy(cacheData, memReq->data, memReq->size);
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// memcpy(cacheData, memReq->data, memReq->size);
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}
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}
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@ -541,7 +570,8 @@ FrontEnd<Impl>::squash(const InstSeqNum &squash_num, const Addr &next_PC,
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// Clear the icache miss if it's outstanding.
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if (status == IcacheMissStall && icacheInterface) {
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||||
DPRINTF(FE, "Squashing outstanding Icache miss.\n");
|
||||
icacheInterface->squash(0);
|
||||
// icacheInterface->squash(0);
|
||||
memReq = NULL;
|
||||
}
|
||||
|
||||
if (status == SerializeBlocked) {
|
||||
|
@ -577,12 +607,13 @@ FrontEnd<Impl>::getInst()
|
|||
|
||||
template <class Impl>
|
||||
void
|
||||
FrontEnd<Impl>::processCacheCompletion()
|
||||
FrontEnd<Impl>::processCacheCompletion(MemReqPtr &req)
|
||||
{
|
||||
DPRINTF(FE, "Processing cache completion\n");
|
||||
|
||||
// Do something here.
|
||||
if (status != IcacheMissStall) {
|
||||
if (status != IcacheMissStall ||
|
||||
req != memReq) {
|
||||
DPRINTF(FE, "Previous fetch was squashed.\n");
|
||||
return;
|
||||
}
|
||||
|
@ -595,10 +626,11 @@ FrontEnd<Impl>::processCacheCompletion()
|
|||
fetchStatus[tid] = IcacheMissComplete;
|
||||
}
|
||||
*/
|
||||
memcpy(cacheData, memReq->data, memReq->size);
|
||||
// memcpy(cacheData, memReq->data, memReq->size);
|
||||
|
||||
// Reset the completion event to NULL.
|
||||
memReq->completionEvent = NULL;
|
||||
// memReq->completionEvent = NULL;
|
||||
memReq = NULL;
|
||||
}
|
||||
|
||||
template <class Impl>
|
||||
|
@ -766,6 +798,15 @@ FrontEnd<Impl>::renameInst(DynInstPtr &inst)
|
|||
}
|
||||
}
|
||||
|
||||
template <class Impl>
|
||||
void
|
||||
FrontEnd<Impl>::wakeFromQuiesce()
|
||||
{
|
||||
DPRINTF(FE, "Waking up from quiesce\n");
|
||||
// Hopefully this is safe
|
||||
status = Running;
|
||||
}
|
||||
|
||||
template <class Impl>
|
||||
void
|
||||
FrontEnd<Impl>::dumpInsts()
|
||||
|
@ -786,8 +827,8 @@ FrontEnd<Impl>::dumpInsts()
|
|||
}
|
||||
|
||||
template <class Impl>
|
||||
FrontEnd<Impl>::ICacheCompletionEvent::ICacheCompletionEvent(FrontEnd *fe)
|
||||
: Event(&mainEventQueue, Delayed_Writeback_Pri), frontEnd(fe)
|
||||
FrontEnd<Impl>::ICacheCompletionEvent::ICacheCompletionEvent(MemReqPtr &_req, FrontEnd *fe)
|
||||
: Event(&mainEventQueue, Delayed_Writeback_Pri), req(_req), frontEnd(fe)
|
||||
{
|
||||
this->setFlags(Event::AutoDelete);
|
||||
}
|
||||
|
@ -796,7 +837,7 @@ template <class Impl>
|
|||
void
|
||||
FrontEnd<Impl>::ICacheCompletionEvent::process()
|
||||
{
|
||||
frontEnd->processCacheCompletion();
|
||||
frontEnd->processCacheCompletion(req);
|
||||
}
|
||||
|
||||
template <class Impl>
|
||||
|
|
|
@ -94,8 +94,7 @@ class LWBackEnd
|
|||
|
||||
void regStats();
|
||||
|
||||
void setCPU(FullCPU *cpu_ptr)
|
||||
{ cpu = cpu_ptr; }
|
||||
void setCPU(FullCPU *cpu_ptr);
|
||||
|
||||
void setFrontEnd(FrontEnd *front_end_ptr)
|
||||
{ frontEnd = front_end_ptr; }
|
||||
|
@ -404,6 +403,9 @@ class LWBackEnd
|
|||
Stats::Scalar<> commit_eligible_samples;
|
||||
Stats::Vector<> commit_eligible;
|
||||
|
||||
Stats::Vector<> squashedInsts;
|
||||
Stats::Vector<> ROBSquashedInsts;
|
||||
|
||||
Stats::Scalar<> ROB_fcount;
|
||||
Stats::Formula ROB_full_rate;
|
||||
|
||||
|
|
|
@ -480,6 +480,18 @@ LWBackEnd<Impl>::regStats()
|
|||
.desc("number cycles where commit BW limit reached")
|
||||
;
|
||||
|
||||
squashedInsts
|
||||
.init(cpu->number_of_threads)
|
||||
.name(name() + ".COM:squashed_insts")
|
||||
.desc("Number of instructions removed from inst list")
|
||||
;
|
||||
|
||||
ROBSquashedInsts
|
||||
.init(cpu->number_of_threads)
|
||||
.name(name() + ".COM:rob_squashed_insts")
|
||||
.desc("Number of instructions removed from inst list when they reached the head of the ROB")
|
||||
;
|
||||
|
||||
ROB_fcount
|
||||
.name(name() + ".ROB:full_count")
|
||||
.desc("number of cycles where ROB was full")
|
||||
|
@ -515,6 +527,14 @@ LWBackEnd<Impl>::regStats()
|
|||
// IQ.regStats();
|
||||
}
|
||||
|
||||
template <class Impl>
|
||||
void
|
||||
LWBackEnd<Impl>::setCPU(FullCPU *cpu_ptr)
|
||||
{
|
||||
cpu = cpu_ptr;
|
||||
LSQ.setCPU(cpu_ptr);
|
||||
}
|
||||
|
||||
template <class Impl>
|
||||
void
|
||||
LWBackEnd<Impl>::setCommBuffer(TimeBuffer<CommStruct> *_comm)
|
||||
|
@ -1044,35 +1064,24 @@ LWBackEnd<Impl>::commitInst(int inst_num)
|
|||
}
|
||||
}
|
||||
|
||||
// Now check if it's one of the special trap or barrier or
|
||||
// serializing instructions.
|
||||
if (inst->isThreadSync())
|
||||
{
|
||||
// Not handled for now.
|
||||
panic("Thread sync instructions are not handled yet.\n");
|
||||
}
|
||||
// Not handled for now.
|
||||
assert(!inst->isThreadSync());
|
||||
|
||||
// Check if the instruction caused a fault. If so, trap.
|
||||
Fault inst_fault = inst->getFault();
|
||||
|
||||
if (inst_fault != NoFault) {
|
||||
if (!inst->isNop()) {
|
||||
DPRINTF(BE, "Inst [sn:%lli] PC %#x has a fault\n",
|
||||
inst->seqNum, inst->readPC());
|
||||
thread->setInst(
|
||||
static_cast<TheISA::MachInst>(inst->staticInst->machInst));
|
||||
DPRINTF(BE, "Inst [sn:%lli] PC %#x has a fault\n",
|
||||
inst->seqNum, inst->readPC());
|
||||
thread->setInst(
|
||||
static_cast<TheISA::MachInst>(inst->staticInst->machInst));
|
||||
#if FULL_SYSTEM
|
||||
handleFault(inst_fault);
|
||||
return false;
|
||||
handleFault(inst_fault);
|
||||
return false;
|
||||
#else // !FULL_SYSTEM
|
||||
panic("fault (%d) detected @ PC %08p", inst_fault,
|
||||
inst->PC);
|
||||
panic("fault (%d) detected @ PC %08p", inst_fault,
|
||||
inst->PC);
|
||||
#endif // FULL_SYSTEM
|
||||
}
|
||||
}
|
||||
|
||||
if (inst->isControl()) {
|
||||
// ++commitCommittedBranches;
|
||||
}
|
||||
|
||||
int freed_regs = 0;
|
||||
|
@ -1096,7 +1105,6 @@ LWBackEnd<Impl>::commitInst(int inst_num)
|
|||
instList.pop_back();
|
||||
|
||||
--numInsts;
|
||||
cpu->numInst++;
|
||||
thread->numInsts++;
|
||||
++thread->funcExeInst;
|
||||
// Maybe move this to where teh fault is handled; if the fault is handled,
|
||||
|
@ -1134,15 +1142,14 @@ template <class Impl>
|
|||
void
|
||||
LWBackEnd<Impl>::commitInsts()
|
||||
{
|
||||
int commit_width = commitWidth ? commitWidth : width;
|
||||
|
||||
// Not sure this should be a loop or not.
|
||||
int inst_num = 0;
|
||||
while (!instList.empty() && inst_num < commit_width) {
|
||||
while (!instList.empty() && inst_num < commitWidth) {
|
||||
if (instList.back()->isSquashed()) {
|
||||
instList.back()->clearDependents();
|
||||
instList.pop_back();
|
||||
--numInsts;
|
||||
ROBSquashedInsts[instList.back()->threadNumber]++;
|
||||
continue;
|
||||
}
|
||||
|
||||
|
@ -1150,6 +1157,7 @@ LWBackEnd<Impl>::commitInsts()
|
|||
DPRINTF(BE, "Can't commit, Instruction [sn:%lli] PC "
|
||||
"%#x is head of ROB and not ready\n",
|
||||
instList.back()->seqNum, instList.back()->readPC());
|
||||
--inst_num;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
@ -1217,6 +1225,8 @@ LWBackEnd<Impl>::squash(const InstSeqNum &sn)
|
|||
|
||||
(*insts_it)->clearDependents();
|
||||
|
||||
squashedInsts[(*insts_it)->threadNumber]++;
|
||||
|
||||
instList.erase(insts_it++);
|
||||
--numInsts;
|
||||
}
|
||||
|
@ -1350,6 +1360,7 @@ LWBackEnd<Impl>::updateComInstStats(DynInstPtr &inst)
|
|||
{
|
||||
unsigned thread = inst->threadNumber;
|
||||
|
||||
cpu->numInst++;
|
||||
//
|
||||
// Pick off the software prefetches
|
||||
//
|
||||
|
|
|
@ -43,7 +43,7 @@
|
|||
//#include "mem/page_table.hh"
|
||||
#include "sim/sim_object.hh"
|
||||
|
||||
class PageTable;
|
||||
//class PageTable;
|
||||
|
||||
/**
|
||||
* Class that implements the actual LQ and SQ for each specific thread.
|
||||
|
@ -115,7 +115,7 @@ class OzoneLWLSQ {
|
|||
{ be = be_ptr; }
|
||||
|
||||
/** Sets the page table pointer. */
|
||||
void setPageTable(PageTable *pt_ptr);
|
||||
// void setPageTable(PageTable *pt_ptr);
|
||||
|
||||
/** Ticks the LSQ unit, which in this case only resets the number of
|
||||
* used cache ports.
|
||||
|
@ -243,7 +243,7 @@ class OzoneLWLSQ {
|
|||
MemInterface *dcacheInterface;
|
||||
|
||||
/** Pointer to the page table. */
|
||||
PageTable *pTable;
|
||||
// PageTable *pTable;
|
||||
|
||||
public:
|
||||
struct SQEntry {
|
||||
|
@ -562,6 +562,19 @@ OzoneLWLSQ<Impl>::read(MemReqPtr &req, T &data, int load_idx)
|
|||
|
||||
|
||||
// If there's no forwarding case, then go access memory
|
||||
DPRINTF(OzoneLSQ, "Doing functional access for inst PC %#x\n",
|
||||
inst->readPC());
|
||||
|
||||
|
||||
// Setup MemReq pointer
|
||||
req->cmd = Read;
|
||||
req->completionEvent = NULL;
|
||||
req->time = curTick;
|
||||
assert(!req->data);
|
||||
req->data = new uint8_t[64];
|
||||
Fault fault = cpu->read(req, data);
|
||||
memcpy(req->data, &data, sizeof(T));
|
||||
|
||||
++usedPorts;
|
||||
|
||||
// if we have a cache, do cache access too
|
||||
|
@ -582,12 +595,6 @@ OzoneLWLSQ<Impl>::read(MemReqPtr &req, T &data, int load_idx)
|
|||
"vaddr:%#x flags:%i\n",
|
||||
inst->readPC(), req->paddr, req->vaddr, req->flags);
|
||||
|
||||
// Setup MemReq pointer
|
||||
req->cmd = Read;
|
||||
req->completionEvent = NULL;
|
||||
req->time = curTick;
|
||||
assert(!req->data);
|
||||
req->data = new uint8_t[64];
|
||||
|
||||
assert(!req->completionEvent);
|
||||
req->completionEvent =
|
||||
|
|
|
@ -131,7 +131,7 @@ OzoneLWLSQ<Impl>::clearSQ()
|
|||
{
|
||||
storeQueue.clear();
|
||||
}
|
||||
|
||||
/*
|
||||
template<class Impl>
|
||||
void
|
||||
OzoneLWLSQ<Impl>::setPageTable(PageTable *pt_ptr)
|
||||
|
@ -139,7 +139,7 @@ OzoneLWLSQ<Impl>::setPageTable(PageTable *pt_ptr)
|
|||
DPRINTF(OzoneLSQ, "Setting the page table pointer.\n");
|
||||
pTable = pt_ptr;
|
||||
}
|
||||
|
||||
*/
|
||||
template<class Impl>
|
||||
void
|
||||
OzoneLWLSQ<Impl>::resizeLQ(unsigned size)
|
||||
|
@ -519,6 +519,23 @@ OzoneLWLSQ<Impl>::writebackStores()
|
|||
req->paddr, *(req->data),
|
||||
inst->seqNum);
|
||||
|
||||
switch((*sq_it).size) {
|
||||
case 1:
|
||||
cpu->write(req, (uint8_t &)(*sq_it).data);
|
||||
break;
|
||||
case 2:
|
||||
cpu->write(req, (uint16_t &)(*sq_it).data);
|
||||
break;
|
||||
case 4:
|
||||
cpu->write(req, (uint32_t &)(*sq_it).data);
|
||||
break;
|
||||
case 8:
|
||||
cpu->write(req, (uint64_t &)(*sq_it).data);
|
||||
break;
|
||||
default:
|
||||
panic("Unexpected store size!\n");
|
||||
}
|
||||
|
||||
if (dcacheInterface) {
|
||||
MemAccessResult result = dcacheInterface->access(req);
|
||||
|
||||
|
@ -538,7 +555,7 @@ OzoneLWLSQ<Impl>::writebackStores()
|
|||
typename BackEnd::LdWritebackEvent *wb = NULL;
|
||||
if (req->flags & LOCKED) {
|
||||
// Stx_C does not generate a system port transaction.
|
||||
req->result=1;
|
||||
// req->result=1;
|
||||
wb = new typename BackEnd::LdWritebackEvent(inst,
|
||||
be);
|
||||
}
|
||||
|
@ -571,12 +588,12 @@ OzoneLWLSQ<Impl>::writebackStores()
|
|||
|
||||
if (req->flags & LOCKED) {
|
||||
// Stx_C does not generate a system port transaction.
|
||||
if (req->flags & UNCACHEABLE) {
|
||||
/* if (req->flags & UNCACHEABLE) {
|
||||
req->result = 2;
|
||||
} else {
|
||||
req->result = 1;
|
||||
}
|
||||
|
||||
*/
|
||||
typename BackEnd::LdWritebackEvent *wb =
|
||||
new typename BackEnd::LdWritebackEvent(inst,
|
||||
be);
|
||||
|
@ -642,6 +659,11 @@ OzoneLWLSQ<Impl>::squash(const InstSeqNum &squashed_num)
|
|||
|
||||
while (stores != 0 && (*sq_it).inst->seqNum > squashed_num) {
|
||||
assert(!storeQueue.empty());
|
||||
|
||||
if ((*sq_it).canWB) {
|
||||
break;
|
||||
}
|
||||
|
||||
// Clear the smart pointer to make sure it is decremented.
|
||||
DPRINTF(OzoneLSQ,"Store Instruction PC %#x idx:%i squashed [sn:%lli]\n",
|
||||
(*sq_it).inst->readPC(), (*sq_it).inst->sqIdx,
|
||||
|
|
Loading…
Reference in a new issue