Commit graph

3018 commits

Author SHA1 Message Date
Kevin Lim
6ee38f143e Merge ktlim@zizzer:/bk/newmem
into  zizzer.eecs.umich.edu:/.automount/zamp/z/ktlim2/clean/newmem-merge

--HG--
extra : convert_revision : 349dbc2a39eba7fa5019c811123a643a41fdc6ff
2006-06-12 19:15:14 -04:00
Kevin Lim
b5cf61efad Fixes for checker. The RC/RS instructions check the interrupt flag, which isn't verifiable by the checker.
src/arch/alpha/isa/decoder.isa:
src/cpu/checker/cpu.cc:
    Fixes for checker.

--HG--
extra : convert_revision : b0ec8f3c4a10453a567cd6691283fc498403795e
2006-06-12 19:11:38 -04:00
Kevin Lim
6152e8abc3 Fix output messages.
src/cpu/o3/decode_impl.hh:
src/cpu/o3/rename_impl.hh:
    Fix output message.

--HG--
extra : convert_revision : f226b84d0e15f275286b1ed078d341831370322b
2006-06-12 19:05:48 -04:00
Kevin Lim
4acb283496 Clean up/shift some code around.
src/cpu/base_dyn_inst.cc:
    Clean up some code and update.
src/cpu/base_dyn_inst.hh:
    Clean up some code and update with more descriptive function names.
src/cpu/o3/alpha_cpu_builder.cc:
src/cpu/o3/alpha_params.hh:
src/cpu/o3/commit.hh:
    Remove unused parameters.
src/cpu/o3/commit_impl.hh:
    Remove unused parameters, also set squashCounter directly to the counted number of squashes.
src/cpu/o3/fetch_impl.hh:
    Update for function name changes.
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
    Remove unused parameter, move some code into a function.

--HG--
extra : convert_revision : 45abd77ad43dde2e93c2e53c4738c90ba8352a1d
2006-06-12 19:04:42 -04:00
Kevin Lim
fbf3a82c5c Fix compile error.
--HG--
extra : convert_revision : 334f5033f5a3a303bfaec3a3acfbd36f205efe86
2006-06-12 18:59:24 -04:00
Kevin Lim
5639fb2c43 Fix memory leak.
src/arch/alpha/ev5.cc:
    Fix memory leak.  The faults are refcounted, but that only works if you're actually assigning them to a RefCountingPtr.

--HG--
extra : convert_revision : 9a57963eb5d5d86c16023bfedb0fb5ccdbe7efaa
2006-06-12 18:58:29 -04:00
Korey Sewell
07f21ce913 Merge zizzer:/bk/newmem
into  zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-release

--HG--
extra : convert_revision : 7ac7b9c9288e4940899766cd2dd55ef793d48d4d
2006-06-12 18:16:05 -04:00
Kevin Lim
841d0b9d40 Merge fixes to make full system compile and run.
src/arch/alpha/linux/system.cc:
src/cpu/o3/alpha_cpu_impl.hh:
src/sim/system.cc:
    Merge fixes.

--HG--
extra : convert_revision : aa3326c0ebf54da9ab1dbd2d9877da41ca487082
2006-06-12 17:53:57 -04:00
Kevin Lim
3e1537cf8b Removed syscall function from thread_context.hh. ThreadContext is the interface for external, non-CPU objects to access the thread, so they probably shouldn't be able to call syscall(). The case it was being used for was already handled by the ISA code.
src/arch/sparc/faults.cc:
src/cpu/thread_context.hh:
    Fix for merge problems.

--HG--
extra : convert_revision : 05a7a2d6e45099fcf36d113da2e52450d892a72c
2006-06-12 16:42:56 -04:00
Korey Sewell
b0fc2c02af Merge zizzer:/bk/newmem
into  zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-release

--HG--
extra : convert_revision : 18a381fa230f2ef6d027359ffd619e3ae75cd446
2006-06-12 16:19:18 -04:00
Steve Reinhardt
babb22eea4 Fix python binary name in arch/SConscript.
Also delete no-longer-needed SPARC test.py files (should
have gone with my last chnageset where LiveProcess
became ISA-independent).

src/arch/SConscript:
    Mistakenly committed hard-coded python binary name.
    Should use same python to run isa_parser that was
    used to run scons.

--HG--
extra : convert_revision : a3acd5496f3b930d57bb59ae164b8a4a8065bbf8
2006-06-12 06:19:13 -04:00
Gabe Black
15a8f05060 Merge m5.eecs.umich.edu:/bk/newmem
into  ewok.(none):/home/gblack/m5/newmem

src/arch/sparc/regfile.hh:
    Hand Merge

--HG--
extra : convert_revision : c47202689202069892524a7d71962082469996ee
2006-06-12 00:49:24 -04:00
Gabe Black
60a734e175 Made isHyperPriv and isPriv protected member variables.
--HG--
extra : convert_revision : af0c2bd46cdea31e5b7e6a75434bbd27b8e6b427
2006-06-12 00:44:24 -04:00
Nathan Binkert
df4b4f001e Merge zizzer.eecs.umich.edu:/bk/newmem
into  iceaxe.:/Volumes/work/research/m5/newmem

--HG--
extra : convert_revision : e457e807b29d8ff88ac335cd50acd596e7e31eee
2006-06-11 23:02:50 -04:00
Nathan Binkert
3c95f5958f Merge iceaxe.:/Volumes/work/research/m5/head
into  iceaxe.:/Volumes/work/research/m5/merge

src/cpu/simple/base.cc:
src/kern/kernel_stats.cc:
src/kern/kernel_stats.hh:
src/kern/system_events.cc:
src/kern/system_events.hh:
src/python/m5/objects/System.py:
src/sim/system.cc:
src/sim/system.hh:
    hand merge

--HG--
rename : build/SConstruct => SConstruct
rename : SConscript => src/SConscript
rename : arch/alpha/freebsd/system.cc => src/arch/alpha/freebsd/system.cc
rename : arch/alpha/linux/system.cc => src/arch/alpha/linux/system.cc
rename : arch/alpha/linux/system.hh => src/arch/alpha/linux/system.hh
rename : arch/alpha/system.cc => src/arch/alpha/system.cc
rename : arch/alpha/tru64/system.cc => src/arch/alpha/tru64/system.cc
rename : base/statistics.cc => src/base/statistics.cc
rename : base/statistics.hh => src/base/statistics.hh
rename : base/stats/mysql.cc => src/base/stats/mysql.cc
rename : base/stats/mysql.hh => src/base/stats/mysql.hh
rename : base/stats/statdb.cc => src/base/stats/statdb.cc
rename : base/stats/statdb.hh => src/base/stats/statdb.hh
rename : base/stats/text.cc => src/base/stats/text.cc
rename : base/stats/text.hh => src/base/stats/text.hh
rename : cpu/simple/cpu.cc => src/cpu/simple/base.cc
rename : kern/kernel_stats.cc => src/kern/kernel_stats.cc
rename : kern/kernel_stats.hh => src/kern/kernel_stats.hh
rename : kern/system_events.cc => src/kern/system_events.cc
rename : kern/system_events.hh => src/kern/system_events.hh
rename : python/m5/objects/System.py => src/python/m5/objects/System.py
rename : sim/system.cc => src/sim/system.cc
rename : sim/system.hh => src/sim/system.hh
rename : test/stattest.cc => src/unittest/stattest.cc
extra : convert_revision : 4bb576a2bf5e32784efc48030bd776c6c7c29a7c
2006-06-11 22:01:34 -04:00
Steve Reinhardt
e0140202bd Move LiveProcess::create() from arch-specific files
bcak to main LiveProcess, then automatically select
ISA based on object file type.  Now simulation scripts
no longer need to care about the ISA, as they can just
call LiveProcess().

configs/test/test.py:
    Script no longer cares about ISA.
src/arch/alpha/process.cc:
src/arch/alpha/process.hh:
src/arch/mips/process.cc:
src/arch/mips/process.hh:
src/arch/sparc/process.cc:
src/arch/sparc/process.hh:
src/sim/process.cc:
src/sim/process.hh:
    Move create() from arch-specific files back to
    main LiveProcess, then automatically select ISA
    based on object file type.

--HG--
extra : convert_revision : ef33ffdc79623b77000f5d68edd2026760b76ab6
2006-06-11 21:49:46 -04:00
Steve Reinhardt
d3a5783523 Add some utility functions to ease handling
SimObjects and sequences of SimObjects in a
uniform manner.

--HG--
extra : convert_revision : 5db28b778c6b1ca63ad0a112ad7e92cd610f64d3
2006-06-11 20:37:56 -04:00
Korey Sewell
13d46e2075 Remove Full System Files
src/arch/mips/SConscript:
    remove full-system
src/arch/mips/stacktrace.hh:
    alpha to mips

--HG--
extra : convert_revision : 5aa7ba6a4af4884e911708608dfc5a552f70654d
2006-06-11 19:04:22 -04:00
Ali Saidi
4ab8e881ed Fix compiling for SPARC_SE:
- change include from exec_context.hh -> threadcontext.hh
- g++ 4.0.3 complaint about broken code (which it was).
- bad merge thread_context -> exec_context

src/arch/sparc/isa/includes.isa:
    Fix SPARC_SE for exec_context->thread_context switch
src/arch/sparc/regfile.hh:
    fix g++ 4.0.3 complaint about broken code (which it was).
src/cpu/thread_context.hh:
    fix bad merge

--HG--
extra : convert_revision : f5bab822d5c25177756e9890e143b0ad8d704201
2006-06-11 17:21:02 -04:00
Korey Sewell
167fb86a69 Merge zizzer:/bk/newmem
into  zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-release

--HG--
extra : convert_revision : b73eeb1f73a5886a008919acd9e1971a79fd6bfb
2006-06-11 17:11:36 -04:00
Korey Sewell
6b5a8390c7 Remove MIPS tests
--HG--
extra : convert_revision : 03cd1c26b49422feb3ea1de5947063c7048dfa67
2006-06-11 16:25:31 -04:00
Korey Sewell
804a7efa3c next round of MIPS ISA changes
src/arch/mips/isa/decoder.isa:
    div,divu,ext,seb,seh, fp conditonal moves, fp indexed memory...
src/arch/mips/isa/formats/mem.isa:
    MemoryNoDisp class .. use sext<> function instead of doing it manually
src/arch/mips/regfile/float_regfile.hh:
    use bits function

--HG--
extra : convert_revision : cbbda9499185b91bdb2a6198fe1b961be04f9265
2006-06-11 15:38:40 -04:00
Korey Sewell
6a0c5b9fad Edit Fetch DPRINT in simple CPU
src/arch/mips/isa/formats/mt.isa:
    change copyright to 2006
src/cpu/simple/base.cc:
    Only DPRINT NNPC if we are not using ALPHA
src/cpu/static_inst.hh:
    Take Out MIPS Specific functions ...

--HG--
extra : convert_revision : 7a69e80cd1564fa3b778b9dade0e9fe3cef94e64
2006-06-11 14:38:14 -04:00
Steve Reinhardt
bb58e4b851 Don't allow SimObject-valued class params to be set
after the class has been instantiated or subclassed.
This is one of the main situations that leads to
confusing results.

configs/test/fs.py:
    Clean up to avoid modifying BaseCPU after it's been subclassed.

--HG--
extra : convert_revision : 335cb87bc3b211ecc8969cfb99ffc28f62f1f877
2006-06-10 21:13:36 -04:00
Steve Reinhardt
39f85a1de4 Only allow SimObject classes to be instantiated (no cloning!).
Provide a makeClass() method to generate a new class using
a SimObject instance as a template.
All instantiation, subclassing, and class generation is done
recursively using "deep copy"-style memoization to maintain
object relationships in the face of multiple references to
shared objects/classes.

src/python/m5/multidict.py:
    Rename local dict attribute from 'dict' to 'local'
    for clarity.

--HG--
extra : convert_revision : 73ed6836216308709d7bb68d09f8131acd5f1822
2006-06-10 19:58:36 -04:00
Nathan Binkert
7af93dbdf6 Remove all binning stuff
--HG--
extra : convert_revision : 6da2b3b0b6c2824f2064d42670fd8383edb7c718
2006-06-10 13:08:43 -04:00
Steve Reinhardt
cd65504739 Update scripts for testing ALPHA_FS and MIPS_SE.
Minor fixes to ALPHA_FS and SPARC_SE.
SPARC_SE still does not compile... looks like there
are unresolved issues with ExecContext -> ThreadContext
rename/reorg.

configs/test/fs.py:
    Port to new script interface/model.
configs/test/test.py:
    Add support for running MIPS test(s) too via
    command-line option.
src/arch/alpha/ev5.cc:
    Fix include file.
src/arch/sparc/regfile.hh:
    Make Bit64 a ULL constant to avoid compiler error.

--HG--
extra : convert_revision : c46c179758271c4f00171faaa579915846bf4624
2006-06-10 00:22:42 -04:00
Steve Reinhardt
f693b451a5 Fix up imports in Ozone objects/*.py files.
src/python/m5/objects/FUPool.py:
src/python/m5/objects/OzoneCPU.py:
src/python/m5/objects/SimpleOzoneCPU.py:
    Fix up imports (m5 namespace no longer includes m5.config).

--HG--
extra : convert_revision : 8575ef7d19ef8dfe9524723d7c4f85234d1280d2
2006-06-09 23:33:15 -04:00
Steve Reinhardt
95019d0c6f Merge vm1.(none):/home/stever/bk/newmem
into  vm1.(none):/home/stever/bk/newmem-py

src/python/m5/__init__.py:
src/sim/syscall_emul.cc:
    Hand merge.

--HG--
extra : convert_revision : e2542735323e648383c89382421d98a7d1d761bf
2006-06-09 23:18:46 -04:00
Steve Reinhardt
29e34a739b Move main control from C++ into Python.
User script now invokes initialization and
simulation loop after building configuration.
These functions are exported from C++ to Python
using SWIG.

SConstruct:
    Set up SWIG builder & scanner.
    Set up symlinking of source files into build directory
    (by not disabling the default behavior).
configs/test/test.py:
    Rewrite to use new script-driven interface.
    Include a sample option.
src/SConscript:
    Set up symlinking of source files into build directory
    (by not disabling the default behavior).
    Add SWIG-generated main_wrap.cc to source list.
src/arch/SConscript:
    Set up symlinking of source files into build directory
    (by not disabling the default behavior).
src/arch/alpha/ev5.cc:
src/arch/alpha/isa/decoder.isa:
src/cpu/o3/alpha_cpu_impl.hh:
src/cpu/trace/opt_cpu.cc:
src/cpu/trace/trace_cpu.cc:
src/sim/pseudo_inst.cc:
src/sim/root.cc:
src/sim/serialize.cc:
src/sim/syscall_emul.cc:
    SimExit() is now exitSimLoop().
src/cpu/base.cc:
    SimExitEvent is now SimLoopExitEvent
src/python/SConscript:
    Add SWIG build command for main.i.
    Use python/m5 in build dir as source for zip archive...
    easy now with file duplication enabled.
src/python/m5/__init__.py:
    - Move copyright notice back to C++ so we can print
    it right away, even for interactive sessions.
    - Get rid of argument parsing code; just provide default
    option descriptors for user script to call optparse with.
    - Don't clutter m5 namespace by sucking in all of m5.config
    and m5.objects.
    - Move instantiate() function here from config.py.
src/python/m5/config.py:
    - Move instantiate() function to __init__.py.
    - Param.Foo deferred type lookups must use m5.objects
    namespace now (not m5).
src/python/m5/objects/AlphaConsole.py:
src/python/m5/objects/AlphaFullCPU.py:
src/python/m5/objects/AlphaTLB.py:
src/python/m5/objects/BadDevice.py:
src/python/m5/objects/BaseCPU.py:
src/python/m5/objects/BaseCache.py:
src/python/m5/objects/Bridge.py:
src/python/m5/objects/Bus.py:
src/python/m5/objects/CoherenceProtocol.py:
src/python/m5/objects/Device.py:
src/python/m5/objects/DiskImage.py:
src/python/m5/objects/Ethernet.py:
src/python/m5/objects/Ide.py:
src/python/m5/objects/IntrControl.py:
src/python/m5/objects/MemObject.py:
src/python/m5/objects/MemTest.py:
src/python/m5/objects/Pci.py:
src/python/m5/objects/PhysicalMemory.py:
src/python/m5/objects/Platform.py:
src/python/m5/objects/Process.py:
src/python/m5/objects/Repl.py:
src/python/m5/objects/Root.py:
src/python/m5/objects/SimConsole.py:
src/python/m5/objects/SimpleDisk.py:
src/python/m5/objects/System.py:
src/python/m5/objects/Tsunami.py:
src/python/m5/objects/Uart.py:
    Fix up imports (m5 namespace no longer includes m5.config).
src/sim/eventq.cc:
src/sim/eventq.hh:
    Support for Python-called simulate() function:
    - Use IsExitEvent flag to signal events that want
    to exit the simulation loop gracefully (instead of
    calling exit() to terminate the process).
    - Modify interface to hand exit event object back to
    caller so it can be inspected for cause.
src/sim/host.hh:
    Add MaxTick constant.
src/sim/main.cc:
    Move copyright notice back to C++ so we can print
    it right away, even for interactive sessions.
    Use PYTHONPATH environment var to set module path
    (instead of clunky code injection method).
    Move main control from here into Python:
    - Separate initialization code and simulation loop
    into separate functions callable from Python.
    - Make Python interpreter invocation more pure (more
    like directly invoking interpreter).
    Add -i and -p flags (only options on binary itself;
    other options processed by Python).
    Import readline package when using interactive mode.
src/sim/sim_events.cc:
    SimExitEvent is now SimLoopExitEvent, and uses
    IsSimExit flag to terminate loop (instead of
    exiting simulator process).
src/sim/sim_events.hh:
    SimExitEvent is now SimLoopExitEvent, and uses
    IsSimExit flag to terminate loop (instead of
    exiting simulator process).
    Get rid of a few unused constructors.
src/sim/sim_exit.hh:
    SimExit() is now exitSimLoop().
    Get rid of unused functions.
    Add comments.

--HG--
extra : convert_revision : 280b0d671516b25545a6f24cefa64a68319ff3d4
2006-06-09 23:01:31 -04:00
Korey Sewell
6de5d73a99 Authorship stuff
src/sim/syscall_emul.cc:
    Authorship Stuff

--HG--
extra : convert_revision : 0770ce292bf590926d10c1bef537a543c01f0b95
2006-06-09 18:39:56 -04:00
Korey Sewell
8e8f1d51cd Authorship stuff
--HG--
extra : convert_revision : 10c894365fa93eeb44528c29358ad73342f86902
2006-06-09 18:19:08 -04:00
Korey Sewell
f8df550db8 Merge zizzer:/bk/newmem
into  zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-release

--HG--
extra : convert_revision : 82b83199a36059d4b402f89f7db2de299ea59c1e
2006-06-09 17:47:23 -04:00
Korey Sewell
b94fecfa10 change SimpleCPU to Atomic
--HG--
extra : convert_revision : ead4a39cd12665e9b0842fe22541034d9010bb78
2006-06-09 17:46:07 -04:00
Kevin Lim
caca57421b Two minor fixes.
src/cpu/o3/lsq_unit_impl.hh:
    Missed this name change.
src/cpu/thread_state.cc:
    Fix for stats.

--HG--
extra : convert_revision : 50ea862f97f2fbc75c1c03d5700df1e8f2c0d122
2006-06-09 17:21:37 -04:00
Korey Sewell
4cc31e1aef add fcntl64Func
use ThreadContext rename

src/arch/mips/isa/formats/branch.isa:
src/arch/mips/isa/formats/fp.isa:
src/arch/mips/isa/includes.isa:
    Use ThreadContext
src/sim/syscall_emul.cc:
    fcntl64 function using TC
src/sim/syscall_emul.hh:
    Add fcntl64func

--HG--
extra : convert_revision : b5e2348530473704388b1c5a2b59bf78360260a9
2006-06-09 17:07:13 -04:00
Kevin Lim
c14c78fa3e Removing of old code and adding in new comments.
src/cpu/base_dyn_inst.cc:
    Clean up old functions, comments.
src/cpu/o3/alpha_cpu_builder.cc:
src/cpu/o3/alpha_params.hh:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/ozone/lsq_unit.hh:
src/cpu/ozone/lsq_unit_impl.hh:
    Remove old commented code.
src/cpu/o3/fetch.hh:
    Remove old commented code, add in comments.
src/cpu/o3/inst_queue_impl.hh:
    Move comment to better place.
src/cpu/o3/lsq_unit.hh:
    Remove old commented code, add in new comments.
src/cpu/o3/lsq_unit_impl.hh:
    Remove old commented code, rename variable.

--HG--
extra : convert_revision : 8e79af9b4d3b3bdd0f55e4747c6ab64c9ad2f571
2006-06-09 16:28:17 -04:00
Kevin Lim
4b732e43a6 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

--HG--
extra : convert_revision : 184b6ff6c11de8f9c9083dcb93754cb451d9cfce
2006-06-09 12:29:40 -04:00
Kevin Lim
a7f5f54ff8 Allow for fetch to retry access if the sendTiming call fails.
--HG--
extra : convert_revision : ddbcf82e0a3160c93c4e51f5d60b0a7b5983d3ba
2006-06-09 12:29:31 -04:00
Kevin Lim
02606ebb26 Fix allocating requests twice on retries.
--HG--
extra : convert_revision : 7b3324ed41e24b69b3e793005ebc07a7d72a3763
2006-06-09 12:28:11 -04:00
Kevin Lim
e6a6204b17 Remove obsolete stuff.
src/cpu/o3/alpha_cpu.hh:
    Remove functions no longer used for reading and writing.

--HG--
extra : convert_revision : aa2fde86ebad06a9a3a9628016b885ff546c0189
2006-06-09 12:25:55 -04:00
Kevin Lim
068379a9ed Fixes for some outstanding issues in the LSQ. It should now be able to retry. It should also be able to handle LL/SC (through hacks) for the UP case.
src/cpu/o3/lsq_unit.hh:
    Handle being able to retry (untested but hopefully very close to working).

    Handle lock flag for LL/SC hack.  Hopefully the memory system will add in LL/SC soon.

    Better output message.
src/cpu/o3/lsq_unit_impl.hh:
    Handle being able to retry (untested but should be very close to working).

    Make SC's work (hopefully) while the memory system doesn't have a LL/SC implementation.

--HG--
extra : convert_revision : bffa721b21405c88a9c6b3d9b9080957f8a2638f
2006-06-09 11:46:35 -04:00
Korey Sewell
68e470f78a Merging in a month of changes
src/arch/isa_parser.py:
    Sign extend bit if you read int reg that is greater than default size
src/arch/mips/SConscript:
src/arch/mips/faults.cc:
src/arch/mips/faults.hh:
src/arch/mips/isa/base.isa:
src/arch/mips/isa/bitfields.isa:
src/arch/mips/isa/decoder.isa:
src/arch/mips/isa/formats/basic.isa:
src/arch/mips/isa/formats/branch.isa:
src/arch/mips/isa/formats/formats.isa:
src/arch/mips/isa/formats/fp.isa:
src/arch/mips/isa/formats/int.isa:
src/arch/mips/isa/formats/mem.isa:
src/arch/mips/isa/formats/noop.isa:
src/arch/mips/isa/formats/tlbop.isa:
src/arch/mips/isa/formats/trap.isa:
src/arch/mips/isa/formats/unimp.isa:
src/arch/mips/isa/formats/unknown.isa:
src/arch/mips/isa/formats/util.isa:
src/arch/mips/isa/includes.isa:
src/arch/mips/isa/main.isa:
src/arch/mips/isa/operands.isa:
src/arch/mips/isa_traits.cc:
src/arch/mips/linux/process.cc:
src/arch/mips/linux/process.hh:
src/arch/mips/process.cc:
src/arch/mips/process.hh:
src/arch/mips/regfile/float_regfile.hh:
src/arch/mips/utility.hh:
    1 month of changes!
src/arch/mips/isa/formats/control.isa:
    control formats
src/arch/mips/isa/formats/mt.isa:
    mips mt format
src/arch/mips/utility.cc:
    utility functions

--HG--
extra : convert_revision : c1332cb5ce08b464b99fbf04f4a5cac312898784
2006-06-09 03:57:25 -04:00
Ali Saidi
6875e8d839 add nacked result and a function to swizzle nacked packet into something that can be sent out again
implement ability for i/o devices to handle

src/dev/io_device.cc:
src/dev/io_device.hh:
    implement ability for i/o devices to handle
src/mem/packet.hh:
    add nacked result and a function to swizzle nacked packet into something that can be sent out again

--HG--
extra : convert_revision : fa42b01f4ab21562d37bd6bf6f4d7f69a94f0e86
2006-06-08 19:43:50 -04:00
Ali Saidi
8ee856f1d5 add write/read functions that have endian conversions in them
when we get a virtual port delete it (even though delete does nothing in these cases)

src/arch/alpha/linux/system.cc:
src/arch/alpha/stacktrace.cc:
src/base/remote_gdb.cc:
src/cpu/simple_thread.cc:
    when we get a virtual port delete it (even though delete does nothing in this case)
src/mem/port.hh:
src/mem/vport.hh:
    add write/read functions that have endian conversions in them

--HG--
extra : convert_revision : 163e05cc038c461f95c92f8ce55422033f9ea513
2006-06-08 19:03:58 -04:00
Kevin Lim
f5b6aef154 Tell checker that an instruction is completed prior once it does the access to memory. As long as the checker does not access memory to verify the store's data (currently impossible in the O3 model), this will work fine.
src/cpu/o3/lsq_unit_impl.hh:
    Tell checker that an instruction is completed prior once it does the access to memory.

--HG--
extra : convert_revision : 1d4bbac4b35fbd355f300eab76f29b38b5bc88cb
2006-06-08 17:04:41 -04:00
Kevin Lim
1ef5585fee Creation of translating port pushed off to CPU.
--HG--
extra : convert_revision : 842556970ff6f0660e8bef13819a3ddfc048d8c8
2006-06-08 17:02:48 -04:00
Kevin Lim
cf79dba504 Get O3 CPU mostly working in full system, and fix an FP bug that showed up.
It still does not yet handle retries.

src/cpu/base_dyn_inst.hh:
    Get working in full-system mode and fix some FP bugs.
src/cpu/checker/cpu.cc:
src/cpu/checker/cpu.hh:
src/cpu/checker/thread_context.hh:
src/cpu/o3/alpha_cpu.hh:
src/cpu/o3/alpha_cpu_impl.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/thread_state.hh:
    Get working in full system.
src/cpu/checker/o3_cpu_builder.cc:
    Checker does not take a MemObject as a simobj parameter.
src/cpu/o3/alpha_dyn_inst.hh:
    Fix up float regs.
src/cpu/o3/regfile.hh:
    Fix up an fp error, print out more useful output messages.

--HG--
extra : convert_revision : d7cc152a051c697f18b7ee9e14050fbf3ffa5966
2006-06-08 16:58:50 -04:00
Kevin Lim
bf6e176554 Update copyright.
--HG--
extra : convert_revision : 8ad012b1acfe046e6a8a5fb064891d91dadeb2e0
2006-06-07 16:02:55 -04:00
Kevin Lim
54d4220b00 Reorganization/renaming of CPUExecContext. Now it is called SimpleThread in order to clear up the confusion due to the many ExecContexts. It also derives from a common ThreadState object, which holds various state common to threads across CPU models.
Following with the previous check-in, ExecContext now refers only to the interface provided to the ISA in order to access CPU state.  ThreadContext refers to the interface provided to all objects outside the CPU in order to access thread state.  SimpleThread provides all thread state and the interface to access it, and is suitable for simple execution models such as the SimpleCPU.

src/SConscript:
    Include thread state file.
src/arch/alpha/ev5.cc:
src/cpu/checker/cpu.cc:
src/cpu/checker/cpu.hh:
src/cpu/checker/thread_context.hh:
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/cpu/o3/cpu.cc:
src/cpu/ozone/cpu_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
    Rename CPUExecContext to SimpleThread.
src/cpu/base_dyn_inst.hh:
    Make thread member variables protected..
src/cpu/o3/alpha_cpu.hh:
src/cpu/o3/cpu.hh:
    Make various members of ThreadState protected.
src/cpu/o3/alpha_cpu_impl.hh:
    Push generation of TranslatingPort into the CPU itself.
    Make various members of ThreadState protected.
src/cpu/o3/thread_state.hh:
    Pull a lot of common code into the base ThreadState class.
src/cpu/ozone/thread_state.hh:
    Rename CPUExecContext to SimpleThread, move a lot of common code into base ThreadState class.
src/cpu/thread_state.hh:
    Push a lot of common code into base ThreadState class.  This goes along with renaming CPUExecContext to SimpleThread, and making it derive from ThreadState.
src/cpu/simple_thread.cc:
    Rename CPUExecContext to SimpleThread, make it derive from ThreadState.  This helps push a lot of common code/state into a single class that can be used by all CPUs.
src/cpu/simple_thread.hh:
    Rename CPUExecContext to SimpleThread, make it derive from ThreadState.
src/kern/system_events.cc:
    Rename cpu_exec_context to thread_context.
src/sim/process.hh:
    Remove unused forward declaration.

--HG--
rename : src/cpu/cpu_exec_context.cc => src/cpu/simple_thread.cc
rename : src/cpu/cpu_exec_context.hh => src/cpu/simple_thread.hh
extra : convert_revision : 2ed617aa80b64016cb9270f75352607cca032733
2006-06-07 15:29:53 -04:00