sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity

Clean up/shift some code around.

Browse source 
src/cpu/base_dyn_inst.cc:
    Clean up some code and update.
src/cpu/base_dyn_inst.hh:
    Clean up some code and update with more descriptive function names.
src/cpu/o3/alpha_cpu_builder.cc:
src/cpu/o3/alpha_params.hh:
src/cpu/o3/commit.hh:
    Remove unused parameters.
src/cpu/o3/commit_impl.hh:
    Remove unused parameters, also set squashCounter directly to the counted number of squashes.
src/cpu/o3/fetch_impl.hh:
    Update for function name changes.
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
    Remove unused parameter, move some code into a function.

--HG--
extra : convert_revision : 45abd77ad43dde2e93c2e53c4738c90ba8352a1d
This commit is contained in:
Kevin Lim 2006-06-12 19:04:42 -04:00
parent fbf3a82c5c
commit 4acb283496
9 changed files with 49 additions and 167 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

68
src/cpu/base_dyn_inst.cc
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2004-2005 The Regents of The University of Michigan
* Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -103,6 +103,8 @@ BaseDynInst<Impl>::initVars()
readyRegs = 0;
instResult.integer = 0;
// May want to turn this into a bit vector or something.
completed = false;
resultReady = false;
@ -242,31 +244,7 @@ template <class Impl>
void
BaseDynInst<Impl>::writeHint(Addr addr, int size, unsigned flags)
{
// Need to create a MemReq here so we can do a translation. This
// will casue a TLB miss trap if necessary... not sure whether
// that's the best thing to do or not. We don't really need the
// MemReq otherwise, since wh64 has no functional effect.
/*
MemReqPtr req = new MemReq(addr, thread->getXCProxy(), size, flags);
req->asid = asid;
fault = cpu->translateDataWriteReq(req);
if (fault == NoFault && !(req->flags & UNCACHEABLE)) {
// Record key MemReq parameters so we can generate another one
// just like it for the timing access without calling translate()
// again (which might mess up the TLB).
effAddr = req->vaddr;
physEffAddr = req->paddr;
memReqFlags = req->flags;
} else {
// ignore faults & accesses to uncacheable space... treat as no-op
effAddr = physEffAddr = MemReq::inval_addr;
}
storeSize = size;
storeData = 0;
*/
// Not currently supported.
}
/**
@ -276,22 +254,7 @@ template <class Impl>
Fault
BaseDynInst<Impl>::copySrcTranslate(Addr src)
{
/*
MemReqPtr req = new MemReq(src, thread->getXCProxy(), 64);
req->asid = asid;
// translate to physical address
Fault fault = cpu->translateDataReadReq(req);
if (fault == NoFault) {
thread->copySrcAddr = src;
thread->copySrcPhysAddr = req->paddr;
} else {
thread->copySrcAddr = 0;
thread->copySrcPhysAddr = 0;
}
return fault;
*/
// Not currently supported.
return NoFault;
}
@ -302,26 +265,7 @@ template <class Impl>
Fault
BaseDynInst<Impl>::copy(Addr dest)
{
/*
uint8_t data[64];
FunctionalMemory *mem = thread->mem;
assert(thread->copySrcPhysAddr);
MemReqPtr req = new MemReq(dest, thread->getXCProxy(), 64);
req->asid = asid;
// translate to physical address
Fault fault = cpu->translateDataWriteReq(req);
if (fault == NoFault) {
Addr dest_addr = req->paddr;
// Need to read straight from memory since we have more than 8 bytes.
req->paddr = thread->copySrcPhysAddr;
mem->read(req, data);
req->paddr = dest_addr;
mem->write(req, data);
}
return fault;
*/
// Not currently supported.
return NoFault;
}

38
src/cpu/base_dyn_inst.hh
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2004-2005 The Regents of The University of Michigan
* Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -44,12 +44,6 @@
#include "cpu/static_inst.hh"
#include "mem/packet.hh"
#include "sim/system.hh"
/*
#include "encumbered/cpu/full/bpred_update.hh"
#include "encumbered/cpu/full/spec_memory.hh"
#include "encumbered/cpu/full/spec_state.hh"
#include "encumbered/mem/functional/main.hh"
*/
/**
* @file
@ -202,10 +196,9 @@ class BaseDynInst : public FastAlloc, public RefCounted
Fault fault;
/** The memory request. */
// MemReqPtr req;
Request *req;
// Packet pkt;
/** Pointer to the data for the memory access. */
uint8_t *memData;
/** The effective virtual address (lds & stores only). */
@ -288,21 +281,6 @@ class BaseDynInst : public FastAlloc, public RefCounted
void initVars();
public:
/**
* @todo: Make this function work; currently it is a dummy function.
* @param fault Last fault.
* @param cmd Last command.
* @param addr Virtual address of access.
* @param p Memory accessed.
* @param nbytes Access size.
*/
// void
// trace_mem(Fault fault,
// MemCmd cmd,
// Addr addr,
// void *p,
// int nbytes);
/** Dumps out contents of this BaseDynInst. */
void dump();
@ -439,11 +417,13 @@ class BaseDynInst : public FastAlloc, public RefCounted
/** Returns the result of a floating point (double) instruction. */
double readDoubleResult() { return instResult.dbl; }
/** Records an integer register being set to a value. */
void setIntReg(const StaticInst *si, int idx, uint64_t val)
{
instResult.integer = val;
}
/** Records an fp register being set to a value. */
void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
{
if (width == 32)
@ -454,16 +434,19 @@ class BaseDynInst : public FastAlloc, public RefCounted
panic("Unsupported width!");
}
/** Records an fp register being set to a value. */
void setFloatReg(const StaticInst *si, int idx, FloatReg val)
{
instResult.fp = val;
}
/** Records an fp register being set to an integer value. */
void setFloatRegBits(const StaticInst *si, int idx, uint64_t val, int width)
{
instResult.integer = val;
}
/** Records an fp register being set to an integer value. */
void setFloatRegBits(const StaticInst *si, int idx, uint64_t val)
{
instResult.integer = val;
@ -590,14 +573,15 @@ class BaseDynInst : public FastAlloc, public RefCounted
void setNextPC(uint64_t val)
{
nextPC = val;
// instResult.integer = val;
}
/** Sets the ASID. */
void setASID(short addr_space_id) { asid = addr_space_id; }
void setThread(unsigned tid) { threadNumber = tid; }
/** Sets the thread id. */
void setTid(unsigned tid) { threadNumber = tid; }
void setState(ImplState *state) { thread = state; }
void setThreadState(ImplState *state) { thread = state; }
/** Returns the thread context.
*/

15
src/cpu/o3/alpha_cpu_builder.cc
View file

@ -92,11 +92,6 @@ Param<unsigned> commitToIEWDelay;
Param<unsigned> renameToIEWDelay;
Param<unsigned> issueToExecuteDelay;
Param<unsigned> issueWidth;
Param<unsigned> executeWidth;
Param<unsigned> executeIntWidth;
Param<unsigned> executeFloatWidth;
Param<unsigned> executeBranchWidth;
Param<unsigned> executeMemoryWidth;
SimObjectParam<FUPool *> fuPool;
Param<unsigned> iewToCommitDelay;
@ -213,11 +208,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivAlphaFullCPU)
INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
"to the IEW stage)"),
INIT_PARAM(issueWidth, "Issue width"),
INIT_PARAM(executeWidth, "Execute width"),
INIT_PARAM(executeIntWidth, "Integer execute width"),
INIT_PARAM(executeFloatWidth, "Floating point execute width"),
INIT_PARAM(executeBranchWidth, "Branch execute width"),
INIT_PARAM(executeMemoryWidth, "Memory execute width"),
INIT_PARAM_DFLT(fuPool, "Functional unit pool", NULL),
INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
@ -344,11 +334,6 @@ CREATE_SIM_OBJECT(DerivAlphaFullCPU)
params->renameToIEWDelay = renameToIEWDelay;
params->issueToExecuteDelay = issueToExecuteDelay;
params->issueWidth = issueWidth;
params->executeWidth = executeWidth;
params->executeIntWidth = executeIntWidth;
params->executeFloatWidth = executeFloatWidth;
params->executeBranchWidth = executeBranchWidth;
params->executeMemoryWidth = executeMemoryWidth;
params->fuPool = fuPool;
params->iewToCommitDelay = iewToCommitDelay;

5
src/cpu/o3/alpha_params.hh
View file

@ -105,11 +105,6 @@ class AlphaSimpleParams : public BaseFullCPU::Params
unsigned renameToIEWDelay;
unsigned issueToExecuteDelay;
unsigned issueWidth;
unsigned executeWidth;
unsigned executeIntWidth;
unsigned executeFloatWidth;
unsigned executeBranchWidth;
unsigned executeMemoryWidth;
FUPool *fuPool;
//

5
src/cpu/o3/commit.hh
View file

@ -365,11 +365,6 @@ class DefaultCommit
*/
unsigned renameWidth;
/** IEW width, in instructions. Used so ROB knows how many
* instructions to get from the IEW instruction queue.
*/
unsigned iewWidth;
/** Commit width, in instructions. */
unsigned commitWidth;

35
src/cpu/o3/commit_impl.hh
View file

@ -72,7 +72,6 @@ DefaultCommit<Impl>::DefaultCommit(Params *params)
renameToROBDelay(params->renameToROBDelay),
fetchToCommitDelay(params->commitToFetchDelay),
renameWidth(params->renameWidth),
iewWidth(params->executeWidth),
commitWidth(params->commitWidth),
numThreads(params->numberOfThreads),
switchPending(false),
@ -434,7 +433,7 @@ DefaultCommit<Impl>::setNextStatus()
}
}
assert(squashes == squashCounter);
squashCounter = squashes;
// If commit is currently squashing, then it will have activity for the
// next cycle. Set its next status as active.
@ -539,8 +538,6 @@ DefaultCommit<Impl>::squashFromTrap(unsigned tid)
commitStatus[tid] = ROBSquashing;
cpu->activityThisCycle();
++squashCounter;
}
template <class Impl>
@ -558,8 +555,6 @@ DefaultCommit<Impl>::squashFromTC(unsigned tid)
cpu->activityThisCycle();
tcSquash[tid] = false;
++squashCounter;
}
template <class Impl>
@ -585,10 +580,12 @@ DefaultCommit<Impl>::tick()
if (rob->isDoneSquashing(tid)) {
commitStatus[tid] = Running;
--squashCounter;
} else {
DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
"insts this cycle.\n", tid);
rob->doSquash(tid);
toIEW->commitInfo[tid].robSquashing = true;
wroteToTimeBuffer = true;
}
}
}
@ -694,29 +691,7 @@ DefaultCommit<Impl>::commit()
while (threads != (*activeThreads).end()) {
unsigned tid = *threads++;
/*
if (fromFetch->fetchFault && commitStatus[0] != TrapPending) {
// Record the fault. Wait until it's empty in the ROB.
// Then handle the trap. Ignore it if there's already a
// trap pending as fetch will be redirected.
fetchFault = fromFetch->fetchFault;
fetchFaultTick = curTick + fetchTrapLatency;
commitStatus[0] = FetchTrapPending;
DPRINTF(Commit, "Fault from fetch recorded. Will trap if the "
"ROB empties without squashing the fault.\n");
fetchTrapWait = 0;
}
// Fetch may tell commit to clear the trap if it's been squashed.
if (fromFetch->clearFetchFault) {
DPRINTF(Commit, "Received clear fetch fault signal\n");
fetchTrapWait = 0;
if (commitStatus[0] == FetchTrapPending) {
DPRINTF(Commit, "Clearing fault from fetch\n");
commitStatus[0] = Running;
}
}
*/
// Not sure which one takes priority. I think if we have
// both, that's a bad sign.
if (trapSquash[tid] == true) {
@ -744,8 +719,6 @@ DefaultCommit<Impl>::commit()
commitStatus[tid] = ROBSquashing;
++squashCounter;
// If we want to include the squashing instruction in the squash,
// then use one older sequence number.
InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];

10
src/cpu/o3/fetch_impl.hh
View file

@ -817,7 +817,7 @@ DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid)
// Check ROB squash signals from commit.
if (fromCommit->commitInfo[tid].robSquashing) {
DPRINTF(Fetch, "[tid:%u]: ROB is still squashing Thread %u.\n", tid);
DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
// Continue to squash.
fetchStatus[tid] = Squashing;
@ -984,11 +984,11 @@ DefaultFetch<Impl>::fetch(bool &status_change)
DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
next_PC,
inst_seq, cpu);
instruction->setThread(tid);
instruction->setTid(tid);
instruction->setASID(tid);
instruction->setState(cpu->thread[tid]);
instruction->setThreadState(cpu->thread[tid]);
DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created "
"[sn:%lli]\n",
@ -1065,11 +1065,11 @@ DefaultFetch<Impl>::fetch(bool &status_change)
next_PC,
inst_seq, cpu);
instruction->setPredTarg(next_PC + instSize);
instruction->setThread(tid);
instruction->setTid(tid);
instruction->setASID(tid);
instruction->setState(cpu->thread[tid]);
instruction->setThreadState(cpu->thread[tid]);
instruction->traceData = NULL;

8
src/cpu/o3/iew.hh
View file

@ -261,6 +261,9 @@ class DefaultIEW
/** Processes inputs and changes state accordingly. */
void checkSignalsAndUpdate(unsigned tid);
/** Removes instructions from rename from a thread's instruction list. */
void emptyRenameInsts(unsigned tid);
/** Sorts instructions coming from rename into lists separated by thread. */
void sortInsts();
@ -390,11 +393,6 @@ class DefaultIEW
/** Width of issue, in instructions. */
unsigned issueWidth;
/** Width of execute, in instructions. Might make more sense to break
* down into FP vs int.
*/
unsigned executeWidth;
/** Index into queue of instructions being written back. */
unsigned wbNumInst;

32
src/cpu/o3/iew_impl.hh
View file

@ -52,7 +52,6 @@ DefaultIEW<Impl>::DefaultIEW(Params *params)
issueToExecuteDelay(params->issueToExecuteDelay),
issueReadWidth(params->issueWidth),
issueWidth(params->issueWidth),
executeWidth(params->executeWidth),
numThreads(params->numberOfThreads),
switchedOut(false)
{
@ -456,16 +455,7 @@ DefaultIEW<Impl>::squash(unsigned tid)
skidBuffer[tid].pop();
}
while (!insts[tid].empty()) {
if (insts[tid].front()->isLoad() ||
insts[tid].front()->isStore() ) {
toRename->iewInfo[tid].dispatchedToLSQ++;
}
toRename->iewInfo[tid].dispatched++;
insts[tid].pop();
}
emptyRenameInsts(tid);
}
template<class Impl>
@ -799,10 +789,12 @@ DefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid)
}
if (fromCommit->commitInfo[tid].robSquashing) {
DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n");
DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
dispatchStatus[tid] = Squashing;
emptyRenameInsts(tid);
wroteToTimeBuffer = true;
return;
}
@ -851,6 +843,22 @@ DefaultIEW<Impl>::sortInsts()
}
}
template <class Impl>
void
DefaultIEW<Impl>::emptyRenameInsts(unsigned tid)
{
while (!insts[tid].empty()) {
if (insts[tid].front()->isLoad() ||
insts[tid].front()->isStore() ) {
toRename->iewInfo[tid].dispatchedToLSQ++;
}
toRename->iewInfo[tid].dispatched++;
insts[tid].pop();
}
}
template <class Impl>
void
DefaultIEW<Impl>::wakeCPU()