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Removing of old code and adding in new comments.

Browse source 
src/cpu/base_dyn_inst.cc:
    Clean up old functions, comments.
src/cpu/o3/alpha_cpu_builder.cc:
src/cpu/o3/alpha_params.hh:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/ozone/lsq_unit.hh:
src/cpu/ozone/lsq_unit_impl.hh:
    Remove old commented code.
src/cpu/o3/fetch.hh:
    Remove old commented code, add in comments.
src/cpu/o3/inst_queue_impl.hh:
    Move comment to better place.
src/cpu/o3/lsq_unit.hh:
    Remove old commented code, add in new comments.
src/cpu/o3/lsq_unit_impl.hh:
    Remove old commented code, rename variable.

--HG--
extra : convert_revision : 8e79af9b4d3b3bdd0f55e4747c6ab64c9ad2f571
This commit is contained in:
Kevin Lim 2006-06-09 16:28:17 -04:00
parent 4b732e43a6
commit c14c78fa3e
16 changed files with 60 additions and 185 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

64
src/cpu/base_dyn_inst.cc
View file

@ -137,8 +137,7 @@ BaseDynInst<Impl>::initVars()
// Also make this a parameter, or perhaps get it from xc or cpu.
asid = 0;
// Initialize the fault to be unimplemented opcode.
// fault = new UnimplementedOpcodeFault;
// Initialize the fault to be NoFault.
fault = NoFault;
++instcount;
@ -346,67 +345,6 @@ BaseDynInst<Impl>::dump(std::string &outstring)
outstring = s.str();
}
#if 0
template <class Impl>
Fault
BaseDynInst<Impl>::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes)
{
Fault fault;
// check alignments, even speculative this test should always pass
if ((nbytes & nbytes - 1) != 0 || (addr & nbytes - 1) != 0) {
for (int i = 0; i < nbytes; i++)
((char *) p)[i] = 0;
// I added the following because according to the comment above,
// we should never get here. The comment lies
#if 0
panic("unaligned access. Cycle = %n", curTick);
#endif
return NoFault;
}
MemReqPtr req = new MemReq(addr, thread, nbytes);
switch(cmd) {
case Read:
fault = spec_mem->read(req, (uint8_t *)p);
break;
case Write:
fault = spec_mem->write(req, (uint8_t *)p);
if (fault != NoFault)
break;
specMemWrite = true;
storeSize = nbytes;
switch(nbytes) {
case sizeof(uint8_t):
*(uint8_t)&storeData = (uint8_t *)p;
break;
case sizeof(uint16_t):
*(uint16_t)&storeData = (uint16_t *)p;
break;
case sizeof(uint32_t):
*(uint32_t)&storeData = (uint32_t *)p;
break;
case sizeof(uint64_t):
*(uint64_t)&storeData = (uint64_t *)p;
break;
}
break;
default:
fault = genMachineCheckFault();
break;
}
trace_mem(fault, cmd, addr, p, nbytes);
return fault;
}
#endif
template <class Impl>
void
BaseDynInst<Impl>::markSrcRegReady()

3
src/cpu/o3/alpha_cpu_builder.cc
View file

@ -58,7 +58,6 @@ SimObjectParam<AlphaITB *> itb;
SimObjectParam<AlphaDTB *> dtb;
#else
SimObjectVectorParam<Process *> workload;
//SimObjectParam<PageTable *> page_table;
#endif // FULL_SYSTEM
SimObjectParam<MemObject *> mem;
@ -165,7 +164,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivAlphaFullCPU)
INIT_PARAM(dtb, "Data translation buffer"),
#else
INIT_PARAM(workload, "Processes to run"),
// INIT_PARAM(page_table, "Page table"),
#endif // FULL_SYSTEM
INIT_PARAM(mem, "Memory"),
@ -309,7 +307,6 @@ CREATE_SIM_OBJECT(DerivAlphaFullCPU)
params->dtb = dtb;
#else
params->workload = workload;
// params->pTable = page_table;
#endif // FULL_SYSTEM
params->mem = mem;

3
src/cpu/o3/alpha_params.hh
View file

@ -58,9 +58,6 @@ class AlphaSimpleParams : public BaseFullCPU::Params
Process *process;
#endif // FULL_SYSTEM
//Page Table
// PageTable *pTable;
MemObject *mem;
BaseCPU *checker;

5
src/cpu/o3/cpu.hh
View file

@ -490,11 +490,6 @@ class FullO3CPU : public BaseFullCPU
/** Pointers to all of the threads in the CPU. */
std::vector<Thread *> thread;
#if 0
/** Page table pointer. */
PageTable *pTable;
#endif
/** Pointer to the icache interface. */
MemInterface *icacheInterface;
/** Pointer to the dcache interface. */

21
src/cpu/o3/fetch.hh
View file

@ -69,29 +69,41 @@ class DefaultFetch
typedef TheISA::MachInst MachInst;
typedef TheISA::ExtMachInst ExtMachInst;
/** IcachePort class for DefaultFetch. Handles doing the
* communication with the cache/memory.
*/
class IcachePort : public Port
{
protected:
/** Pointer to fetch. */
DefaultFetch<Impl> *fetch;
public:
/** Default constructor. */
IcachePort(DefaultFetch<Impl> *_fetch)
: Port(_fetch->name() + "-iport"), fetch(_fetch)
{ }
protected:
/** Atomic version of receive. Panics. */
virtual Tick recvAtomic(PacketPtr pkt);
/** Functional version of receive. Panics. */
virtual void recvFunctional(PacketPtr pkt);
/** Receives status change. Other than range changing, panics. */
virtual void recvStatusChange(Status status);
/** Returns the address ranges of this device. */
virtual void getDeviceAddressRanges(AddrRangeList &resp,
AddrRangeList &snoop)
{ resp.clear(); snoop.clear(); }
/** Timing version of receive. Handles setting fetch to the
* proper status to start fetching. */
virtual bool recvTiming(PacketPtr pkt);
/** Handles doing a retry of a failed fetch. */
virtual void recvRetry();
};
@ -163,9 +175,6 @@ class DefaultFetch
/** Sets pointer to time buffer used to communicate to the next stage. */
void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
/** Sets pointer to page table. */
// void setPageTable(PageTable *pt_ptr);
/** Initialize stage. */
void initStage();
@ -268,6 +277,7 @@ class DefaultFetch
}
private:
/** Handles retrying the fetch access. */
void recvRetry();
/** Returns the appropriate thread to fetch, given the fetch policy. */
@ -406,11 +416,6 @@ class DefaultFetch
/** Records if fetch is switched out. */
bool switchedOut;
#if !FULL_SYSTEM
/** Page table pointer. */
// PageTable *pTable;
#endif
// @todo: Consider making these vectors and tracking on a per thread basis.
/** Stat for total number of cycles stalled due to an icache miss. */
Stats::Scalar<> icacheStallCycles;

16
src/cpu/o3/fetch_impl.hh
View file

@ -322,18 +322,6 @@ DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
toDecode = fetchQueue->getWire(0);
}
#if 0
template<class Impl>
void
DefaultFetch<Impl>::setPageTable(PageTable *pt_ptr)
{
DPRINTF(Fetch, "Setting the page table pointer.\n");
#if !FULL_SYSTEM
pTable = pt_ptr;
#endif
}
#endif
template<class Impl>
void
DefaultFetch<Impl>::initStage()
@ -381,8 +369,6 @@ DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
fetchStatus[tid] = IcacheAccessComplete;
}
// memcpy(cacheData[tid], memReq[tid]->data, memReq[tid]->size);
// Reset the mem req to NULL.
delete pkt->req;
delete pkt;
@ -594,8 +580,6 @@ DefaultFetch<Impl>::doSquash(const Addr &new_PC, unsigned tid)
if (fetchStatus[tid] == IcacheWaitResponse) {
DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
tid);
// Should I delete this here or when it comes back from the cache?
// delete memReq[tid];
memReq[tid] = NULL;
}

3
src/cpu/o3/iew.hh
View file

@ -155,9 +155,6 @@ class DefaultIEW
/** Returns if IEW is switched out. */
bool isSwitchedOut() { return switchedOut; }
/** Sets page table pointer within LSQ. */
// void setPageTable(PageTable *pt_ptr);
/** Squashes instructions in IEW for a specific thread. */
void squash(unsigned tid);

18
src/cpu/o3/iew_impl.hh
View file

@ -370,15 +370,6 @@ DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
scoreboard = sb_ptr;
}
#if 0
template<class Impl>
void
DefaultIEW<Impl>::setPageTable(PageTable *pt_ptr)
{
ldstQueue.setPageTable(pt_ptr);
}
#endif
template <class Impl>
void
DefaultIEW<Impl>::switchOut()
@ -1182,9 +1173,8 @@ DefaultIEW<Impl>::executeInsts()
fetchRedirect[tid] = false;
}
#if 0
printAvailableInsts();
#endif
// Uncomment this if you want to see all available instructions.
// printAvailableInsts();
// Execute/writeback any instructions that are available.
int insts_to_execute = fromIssue->size;
@ -1349,8 +1339,8 @@ DefaultIEW<Impl>::writebackInsts()
DynInstPtr inst = toCommit->insts[inst_num];
int tid = inst->threadNumber;
DPRINTF(IEW, "Sending instructions to commit, PC %#x.\n",
inst->readPC());
DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n",
inst->seqNum, inst->readPC());
iewInstsToCommit[tid]++;

4
src/cpu/o3/inst_queue_impl.hh
View file

@ -1240,11 +1240,11 @@ template <class Impl>
int
InstructionQueue<Impl>::countInsts()
{
#if 0
//ksewell:This works but definitely could use a cleaner write
//with a more intuitive way of counting. Right now it's
//just brute force ....
#if 0
// Change the #if if you want to use this method.
int total_insts = 0;
for (int i = 0; i < numThreads; ++i) {

7
src/cpu/o3/lsq.hh
View file

@ -36,10 +36,8 @@
#include "config/full_system.hh"
#include "cpu/inst_seq.hh"
//#include "cpu/o3/cpu_policy.hh"
#include "cpu/o3/lsq_unit.hh"
#include "mem/port.hh"
//#include "mem/page_table.hh"
#include "sim/sim_object.hh"
template <class Impl>
@ -70,8 +68,6 @@ class LSQ {
void setCPU(FullCPU *cpu_ptr);
/** Sets the IEW stage pointer. */
void setIEW(IEW *iew_ptr);
/** Sets the page table pointer. */
// void setPageTable(PageTable *pt_ptr);
/** Switches out the LSQ. */
void switchOut();
/** Takes over execution from another CPU's thread. */
@ -281,9 +277,6 @@ class LSQ {
/** The IEW stage pointer. */
IEW *iewStage;
/** The pointer to the page table. */
// PageTable *pTable;
/** List of Active Threads in System. */
std::list<unsigned> *activeThreads;

11
src/cpu/o3/lsq_impl.hh
View file

@ -136,17 +136,6 @@ LSQ<Impl>::setIEW(IEW *iew_ptr)
}
}
#if 0
template<class Impl>
void
LSQ<Impl>::setPageTable(PageTable *pt_ptr)
{
for (int tid=0; tid < numThreads; tid++) {
thread[tid].setPageTable(pt_ptr);
}
}
#endif
template <class Impl>
void
LSQ<Impl>::switchOut()

42
src/cpu/o3/lsq_unit.hh
View file

@ -42,9 +42,6 @@
#include "cpu/inst_seq.hh"
#include "mem/packet.hh"
#include "mem/port.hh"
//#include "mem/page_table.hh"
//#include "sim/debug.hh"
//#include "sim/sim_object.hh"
/**
* Class that implements the actual LQ and SQ for each specific
@ -87,9 +84,6 @@ class LSQUnit {
void setIEW(IEW *iew_ptr)
{ iewStage = iew_ptr; }
/** Sets the page table pointer. */
// void setPageTable(PageTable *pt_ptr);
/** Switches out LSQ unit. */
void switchOut();
@ -211,8 +205,10 @@ class LSQUnit {
!isStoreBlocked; }
private:
/** Writes back the instruction, sending it to IEW. */
void writeback(DynInstPtr &inst, PacketPtr pkt);
/** Handles completing the send of a store to memory. */
void storePostSend(Packet *pkt);
/** Completes the store at the specified index. */
@ -241,55 +237,75 @@ class LSQUnit {
/** Pointer to the IEW stage. */
IEW *iewStage;
/** Pointer to memory object. */
MemObject *mem;
/** DcachePort class for this LSQ Unit. Handles doing the
* communication with the cache/memory.
* @todo: Needs to be moved to the LSQ level and have some sort
* of arbitration.
*/
class DcachePort : public Port
{
protected:
/** Pointer to CPU. */
FullCPU *cpu;
/** Pointer to LSQ. */
LSQUnit *lsq;
public:
/** Default constructor. */
DcachePort(FullCPU *_cpu, LSQUnit *_lsq)
: Port(_lsq->name() + "-dport"), cpu(_cpu), lsq(_lsq)
{ }
protected:
/** Atomic version of receive. Panics. */
virtual Tick recvAtomic(PacketPtr pkt);
/** Functional version of receive. Panics. */
virtual void recvFunctional(PacketPtr pkt);
/** Receives status change. Other than range changing, panics. */
virtual void recvStatusChange(Status status);
/** Returns the address ranges of this device. */
virtual void getDeviceAddressRanges(AddrRangeList &resp,
AddrRangeList &snoop)
{ resp.clear(); snoop.clear(); }
/** Timing version of receive. Handles writing back and
* completing the load or store that has returned from
* memory. */
virtual bool recvTiming(PacketPtr pkt);
/** Handles doing a retry of the previous send. */
virtual void recvRetry();
};
/** Pointer to the D-cache. */
DcachePort *dcachePort;
/** Derived class to hold any sender state the LSQ needs. */
class LSQSenderState : public Packet::SenderState
{
public:
/** Default constructor. */
LSQSenderState()
: noWB(false)
{ }
// protected:
/** Instruction who initiated the access to memory. */
DynInstPtr inst;
/** Whether or not it is a load. */
bool isLoad;
/** The LQ/SQ index of the instruction. */
int idx;
/** Whether or not the instruction will need to writeback. */
bool noWB;
};
/** Pointer to the page table. */
// PageTable *pTable;
/** Writeback event, specifically for when stores forward data to loads. */
class WritebackEvent : public Event {
public:
/** Constructs a writeback event. */
@ -302,8 +318,10 @@ class LSQUnit {
const char *description();
private:
/** Instruction whose results are being written back. */
DynInstPtr inst;
/** The packet that would have been sent to memory. */
PacketPtr pkt;
/** The pointer to the LSQ unit that issued the store. */
@ -404,8 +422,10 @@ class LSQUnit {
/** The index of the above store. */
int stallingLoadIdx;
PacketPtr sendingPkt;
/** The packet that needs to be retried. */
PacketPtr retryPkt;
/** Whehter or not a store is blocked due to the memory system. */
bool isStoreBlocked;
/** Whether or not a load is blocked due to the memory system. */

24
src/cpu/o3/lsq_unit_impl.hh
View file

@ -66,7 +66,7 @@ LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
DynInstPtr inst = state->inst;
DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum);
// DPRINTF(Activity, "Activity: Ld Writeback event [sn:%lli]\n", inst->seqNum);
DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum);
//iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
@ -209,16 +209,6 @@ LSQUnit<Impl>::clearSQ()
storeQueue.clear();
}
#if 0
template<class Impl>
void
LSQUnit<Impl>::setPageTable(PageTable *pt_ptr)
{
DPRINTF(LSQUnit, "Setting the page table pointer.\n");
pTable = pt_ptr;
}
#endif
template<class Impl>
void
LSQUnit<Impl>::switchOut()
@ -628,8 +618,8 @@ LSQUnit<Impl>::writebackStores()
// Need to handle becoming blocked on a store.
isStoreBlocked = true;
assert(sendingPkt == NULL);
sendingPkt = data_pkt;
assert(retryPkt == NULL);
retryPkt = data_pkt;
} else {
storePostSend(data_pkt);
}
@ -858,11 +848,11 @@ template <class Impl>
void
LSQUnit<Impl>::recvRetry()
{
assert(sendingPkt != NULL);
if (isStoreBlocked) {
if (dcachePort->sendTiming(sendingPkt)) {
storePostSend(sendingPkt);
assert(retryPkt != NULL);
if (dcachePort->sendTiming(retryPkt)) {
storePostSend(retryPkt);
sendingPkt = NULL;
isStoreBlocked = false;
} else {

13
src/cpu/o3/rename_impl.hh
View file

@ -327,18 +327,9 @@ DefaultRename<Impl>::squash(unsigned tid)
if (renameStatus[tid] == Blocked ||
renameStatus[tid] == Unblocking ||
renameStatus[tid] == SerializeStall) {
#if 0
// In syscall emulation, we can have both a block and a squash due
// to a syscall in the same cycle. This would cause both signals to
// be high. This shouldn't happen in full system.
if (toDecode->renameBlock[tid]) {
toDecode->renameBlock[tid] = 0;
} else {
toDecode->renameUnblock[tid] = 1;
}
#else
toDecode->renameUnblock[tid] = 1;
#endif
serializeInst[tid] = NULL;
}

3
src/cpu/ozone/lsq_unit.hh
View file

@ -114,9 +114,6 @@ class OzoneLSQ {
void setBE(BackEnd *be_ptr)
{ be = be_ptr; }
/** Sets the page table pointer. */
void setPageTable(PageTable *pt_ptr);
/** Ticks the LSQ unit, which in this case only resets the number of
* used cache ports.
* @todo: Move the number of used ports up to the LSQ level so it can

8
src/cpu/ozone/lsq_unit_impl.hh
View file

@ -123,14 +123,6 @@ OzoneLSQ<Impl>::clearSQ()
storeQueue.clear();
}
template<class Impl>
void
OzoneLSQ<Impl>::setPageTable(PageTable *pt_ptr)
{
DPRINTF(OzoneLSQ, "Setting the page table pointer.\n");
pTable = pt_ptr;
}
template<class Impl>
void
OzoneLSQ<Impl>::resizeLQ(unsigned size)