Allow for fetch to retry access if the sendTiming call fails.
--HG-- extra : convert_revision : ddbcf82e0a3160c93c4e51f5d60b0a7b5983d3ba
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02606ebb26
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2 changed files with 59 additions and 21 deletions
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@ -115,7 +115,7 @@ class DefaultFetch
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QuiescePending,
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SwitchOut,
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IcacheWaitResponse,
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IcacheRetry,
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IcacheWaitRetry,
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IcacheAccessComplete
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};
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@ -268,6 +268,8 @@ class DefaultFetch
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}
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private:
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void recvRetry();
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/** Returns the appropriate thread to fetch, given the fetch policy. */
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int getFetchingThread(FetchPriority &fetch_priority);
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@ -360,6 +362,15 @@ class DefaultFetch
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/** The width of fetch in instructions. */
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unsigned fetchWidth;
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/** Is the cache blocked? If so no threads can access it. */
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bool cacheBlocked;
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/** The packet that is waiting to be retried. */
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PacketPtr retryPkt;
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/** The thread that is waiting on the cache to tell fetch to retry. */
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int retryTid;
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/** Cache block size. */
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int cacheBlkSize;
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@ -88,18 +88,7 @@ template<class Impl>
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void
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DefaultFetch<Impl>::IcachePort::recvRetry()
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{
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panic("DefaultFetch doesn't support retry yet.");
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// we shouldn't get a retry unless we have a packet that we're
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// waiting to transmit
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/*
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assert(cpu->dcache_pkt != NULL);
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assert(cpu->_status == DcacheRetry);
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Packet *tmp = cpu->dcache_pkt;
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if (sendTiming(tmp)) {
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cpu->_status = DcacheWaitResponse;
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cpu->dcache_pkt = NULL;
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}
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*/
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fetch->recvRetry();
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}
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template<class Impl>
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@ -111,6 +100,9 @@ DefaultFetch<Impl>::DefaultFetch(Params *params)
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iewToFetchDelay(params->iewToFetchDelay),
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commitToFetchDelay(params->commitToFetchDelay),
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fetchWidth(params->fetchWidth),
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cacheBlocked(false),
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retryPkt(NULL),
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retryTid(-1),
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numThreads(params->numberOfThreads),
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numFetchingThreads(params->smtNumFetchingThreads),
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interruptPending(false),
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@ -510,9 +502,11 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid
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unsigned flags = 0;
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#endif // FULL_SYSTEM
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if (interruptPending && flags == 0 || switchedOut) {
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// Hold off fetch from getting new instructions while an interrupt
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// is pending.
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if (cacheBlocked || (interruptPending && flags == 0) || switchedOut) {
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// Hold off fetch from getting new instructions when:
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// Cache is blocked, or
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// while an interrupt is pending and we're not in PAL mode, or
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// fetch is switched out.
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return false;
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}
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@ -528,11 +522,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid
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memReq[tid] = mem_req;
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// Translate the instruction request.
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//#if FULL_SYSTEM
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fault = cpu->translateInstReq(mem_req, cpu->thread[tid]);
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//#else
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// fault = pTable->translate(memReq[tid]);
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//#endif
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// In the case of faults, the fetch stage may need to stall and wait
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// for the ITB miss to be handled.
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@ -563,8 +553,13 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid
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// Now do the timing access to see whether or not the instruction
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// exists within the cache.
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if (!icachePort->sendTiming(data_pkt)) {
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assert(retryPkt == NULL);
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assert(retryTid == -1);
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DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
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ret_fault = NoFault;
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fetchStatus[tid] = IcacheWaitRetry;
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retryPkt = data_pkt;
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retryTid = tid;
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cacheBlocked = true;
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return false;
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}
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@ -604,6 +599,16 @@ DefaultFetch<Impl>::doSquash(const Addr &new_PC, unsigned tid)
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memReq[tid] = NULL;
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}
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// Get rid of the retrying packet if it was from this thread.
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if (retryTid == tid) {
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assert(cacheBlocked);
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cacheBlocked = false;
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retryTid = -1;
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retryPkt = NULL;
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delete retryPkt->req;
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delete retryPkt;
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}
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fetchStatus[tid] = Squashing;
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++fetchSquashCycles;
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@ -1103,6 +1108,28 @@ DefaultFetch<Impl>::fetch(bool &status_change)
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}
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}
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template<class Impl>
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void
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DefaultFetch<Impl>::recvRetry()
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{
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assert(cacheBlocked);
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if (retryPkt != NULL) {
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assert(retryTid != -1);
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assert(fetchStatus[retryTid] == IcacheWaitRetry);
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if (icachePort->sendTiming(retryPkt)) {
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fetchStatus[retryTid] = IcacheWaitResponse;
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retryPkt = NULL;
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retryTid = -1;
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cacheBlocked = false;
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}
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} else {
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assert(retryTid == -1);
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// Access has been squashed since it was sent out. Just clear
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// the cache being blocked.
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cacheBlocked = false;
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}
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}
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///////////////////////////////////////
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// //
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