Add checks for swig & libz, version check for swig.
Factor out version check code into function, use for mysql too.
SConstruct:
Add checks for swig & libz, version check for swig.
Factor out version check code into function, use for mysql too.
--HG--
extra : convert_revision : a077d961ae52011141fbf5021b167485f8638139
Added in the filename parameter which is provided for the user space linker.
Fix the ordering and alignment of stack elements.
Made mmap start with the address it has been seen starting with "in the wild"
--HG--
extra : convert_revision : 8734753145f59a6cb433e4f92f43cb28a44b56d4
1. alignaddr wrote it's address to a floating point register rather than a gpr.
2. sethi was sign extending it's immediate value.
--HG--
extra : convert_revision : 9aa30a6485bc4cba916367973b986d439b7c7588
Arg to m5.simulate() is a delta, not an absolute curTick value.
I didn't test this change, but I'm not convinced the previous
example was tested either, so I don't feel too badly about it.
configs/example/fs.py:
Arg to m5.simulate() is a delta, not an absolute curTick value.
I didn't test this change, but I'm not convinced the previous
example was tested either, so I don't feel too badly about it.
--HG--
extra : convert_revision : ef7df7b83b3e2b5da02408c674169ccbed75a441
rename build/*/test dir to build/*/tests for consistency
SConstruct:
rename build/*/test dir to build/*/tests for consistency
--HG--
extra : convert_revision : 6af3cf6b2d6582b2c4d2bc9211e44767e0fa494f
also, update all the rcS files so that they are in sync with the new linux-dist build system.
configs/boot/devtime.rcS:
configs/boot/iscsi-client.rcS:
configs/boot/iscsi-server.rcS:
configs/boot/micro_memlat.rcS:
configs/boot/micro_stream.rcS:
configs/boot/micro_tlblat.rcS:
configs/boot/nat-netperf-maerts-client.rcS:
configs/boot/nat-netperf-server.rcS:
configs/boot/nat-netperf-stream-client.rcS:
configs/boot/nat-spec-surge-client.rcS:
configs/boot/nat-spec-surge-server.rcS:
configs/boot/natbox-netperf.rcS:
configs/boot/natbox-spec-surge.rcS:
configs/boot/netperf-rr.rcS:
configs/boot/netperf-server.rcS:
configs/boot/netperf-stream-client.rcS:
configs/boot/netperf-stream-nt-client.rcS:
configs/boot/nfs-client-nhfsstone.rcS:
configs/boot/nfs-client-tcp-smallb.rcS:
configs/boot/nfs-client-tcp.rcS:
configs/boot/nfs-client.rcS:
configs/boot/nfs-server-nhfsstone.rcS:
configs/boot/nfs-server.rcS:
configs/boot/ping-client.rcS:
configs/boot/ping-server.rcS:
configs/boot/spec-surge-client.rcS:
configs/boot/spec-surge-server.rcS:
configs/boot/surge-client.rcS:
configs/boot/surge-server.rcS:
make tree rcS files reflect what we've been actually using in /dist.
--HG--
extra : convert_revision : 48fe4fe71938ef9d029e428028a271242c8d2faa
src/python/m5/objects/BaseCPU.py:
Make mem parameter a MemObject, not just a PhysicalMemory
Fix a reference not using self
tests/configs/simple-atomic.py:
Set the mem paramter
tests/configs/simple-timing.py:
Set the mem parameter
--HG--
extra : convert_revision : 6bd9df36831a1c5bafc9e88ab945c2ebe91db785
Kinda port DRAM to new memory system. The code is *really* ugly (not my fault) and right now something about the stats it uses
causes a simulator segfault.
src/SConscript:
Add dram.cc to sconscript
src/mem/physical.cc:
src/mem/physical.hh:
Add params struct to physical memory, use params, make latency function be virtual
src/python/m5/objects/PhysicalMemory.py:
Add DRAMMemory python class
--HG--
extra : convert_revision : 5bd9f2e071c62da89e8efa46fa016f342c01535d
Get rid of caches in simple-timing config for now.
tests/SConscript:
another line for diff to ignore
tests/configs/simple-timing.py:
turn off caches for now
tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt:
tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout:
tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt:
tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout:
update for inst/tick rate (old one was debug?)
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini:
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out:
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt:
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr:
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout:
works now (no caches)
--HG--
extra : convert_revision : 472030f63297346976db6274a78235c93d4eef8e
fix 'reorganization' typo and added o3cpu multiple isa support to list
AUTHORS:
fix 'reorganization' typo and added o3cpu multiple isa support to list
--HG--
extra : convert_revision : cd5d0ba69b37add0f10135e5772a57a7aacdf06e
src/cpu/o3/fetch_impl.hh:
Fix ordering so dereference works
src/cpu/o3/lsq_impl.hh:
Check to make sure we didn't squash already
src/cpu/o3/lsq_unit.hh:
Fix for counting squashed retrys in the WB count
src/cpu/o3/lsq_unit_impl.hh:
Make sure to set retryID for stores, and clear it appropriately
--HG--
extra : convert_revision : 689765a1baea7b36f13eb177d65e97b52b6da09f
src/mem/cache/base_cache.cc:
Add in retry path for blocking with multi-level caches
src/mem/cache/base_cache.hh:
Pull more of the blocking fixes into head
src/mem/packet.hh:
Fix typo
--HG--
extra : convert_revision : d4d149adfa414136ebd2c4789b739bb065710f7a
Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/tmp/m5.newmem
AUTHORS:
merge kevin's changes in
--HG--
extra : convert_revision : 86344b6d89d90ec7002584d48736e29a9a3c72e5
Feel free to change as you see fit
AUTHORS:
I threw together the authors file from looking at the Authors of files
--HG--
extra : convert_revision : c13b52c60bbc429b29c64b5bebf5bf4971274a8d
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3
--HG--
extra : convert_revision : 8b6f649623cecec0964cff6fce6f4e6a041ae9a1
