Update REFs for statistics patch in cache
--HG-- extra : convert_revision : 8987d3ab62ea4b2fa18ebd40fc980b30561d7e45
This commit is contained in:
Ron Dreslinski
parent
689eb39d48
commit
4ea3973387
7 changed files with 161 additions and 161 deletions
|
|
@ -1,67 +1,67 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 37119 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 158176 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
host_tick_rate 54058 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 73848 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 159612 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
host_tick_rate 107959 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 2578 # Number of instructions simulated
|
||||
sim_insts 5642 # Number of instructions simulated
|
||||
sim_seconds 0.000000 # Number of seconds simulated
|
||||
sim_ticks 3777 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 416 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 2918912699678311424 # average ReadReq miss latency
|
||||
sim_ticks 8312 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 981 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 361 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 160540198482307121152 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.132212 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 110 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.132212 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 4476343852030456320 # average WriteReq miss latency
|
||||
system.cpu.dcache.ReadReq_hits 891 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 270 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.091743 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 90 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 180 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.091743 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 90 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 2.737500 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 267 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 120861284004822319104 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.091837 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 27 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 54 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.091837 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 27 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_hits 741 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 219 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.097442 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 80 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 146 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.088916 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 7.658537 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 9.600000 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 710 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 3431725396184505344 # average overall miss latency
|
||||
system.cpu.dcache.demand_accesses 1802 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 2.876471 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 628 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 281401482487129440256 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.115493 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 82 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_hits 1632 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 489 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.094340 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 170 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 164 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.115493 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 82 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_miss_latency 326 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.090455 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 710 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 3431725396184505344 # average overall miss latency
|
||||
system.cpu.dcache.overall_accesses 1802 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 2.876471 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 628 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 281401482487129440256 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.115493 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 82 # number of overall misses
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 1632 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 489 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.094340 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 170 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 164 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.115493 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 82 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_miss_latency 326 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.090455 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 163 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -74,56 +74,56 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 170 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 53.009529 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 628 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 112.055094 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1632 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 2579 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 3447887748754160128 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 2416 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 562005703046928072704 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.063203 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 326 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.063203 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_accesses 5643 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 2.996390 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996390 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 5366 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 830 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.049087 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 277 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 553 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.049087 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 277 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 14.822086 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 19.371841 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 2579 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 3447887748754160128 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 2416 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 562005703046928072704 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.063203 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 163 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_accesses 5643 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 2.996390 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 1.996390 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 5366 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 830 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.049087 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 277 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 326 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.063203 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_miss_latency 553 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.049087 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 277 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 2579 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 3447887748754160128 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_accesses 5643 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 2.996390 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 1.996390 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 2416 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 562005703046928072704 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.063203 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 163 # number of overall misses
|
||||
system.cpu.icache.overall_hits 5366 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 830 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.049087 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 277 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 326 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.063203 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_miss_latency 553 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.049087 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 277 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -136,56 +136,57 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 277 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 93.126257 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 2416 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 133.267292 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 5366 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 245 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_accesses 447 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 1.968610 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_miss_latency 490 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 245 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 245 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 245 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 878 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.997763 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 446 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 439 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.982103 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 439 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.002242 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2 # average overall miss latency
|
||||
system.cpu.l2cache.demand_accesses 447 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 1.968610 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 490 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 245 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 878 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.997763 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 446 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 245 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 245 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 439 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.982103 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 439 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2 # average overall miss latency
|
||||
system.cpu.l2cache.overall_accesses 447 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 1.968610 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 0 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 490 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 245 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 1 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 878 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.997763 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 446 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 245 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 245 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 439 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.982103 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 439 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -198,16 +199,16 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 245 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 446 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 146.200635 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 245.259112 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 0 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 2578 # Number of instructions executed
|
||||
system.cpu.num_refs 710 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
|
||||
system.cpu.num_insts 5642 # Number of instructions executed
|
||||
system.cpu.num_refs 1792 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,3 +1,2 @@
|
|||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff8
|
||||
warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)
|
||||
warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
|
||||
|
|
|
|||
|
|
@ -6,8 +6,8 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 18 2006 00:06:43
|
||||
M5 started Sun Aug 20 01:42:05 2006
|
||||
M5 compiled Aug 21 2006 14:18:48
|
||||
M5 started Mon Aug 21 14:19:14 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing
|
||||
Exiting @ tick 3777 because target called exit()
|
||||
Exiting @ tick 8312 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,28 +1,28 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 67697 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 158936 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
host_tick_rate 102046 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 289509 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 158964 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
host_tick_rate 429531 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 5657 # Number of instructions simulated
|
||||
sim_seconds 0.000000 # Number of seconds simulated
|
||||
sim_ticks 8573 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 1131 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 1791574296802328064 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 1052 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 141534369447383908352 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 237 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.069850 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 79 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 158 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.069850 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 79 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 933 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 2766176443076198912 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 2.586207 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 875 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 160438233698419539968 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 150 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.062165 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 58 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 100 # number of WriteReq MSHR miss cycles
|
||||
|
|
@ -37,10 +37,10 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 2064 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 2204179585005864704 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 2.824818 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 1927 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 301972603145803464704 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 387 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.066376 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 137 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
|
|
@ -51,11 +51,11 @@ system.cpu.dcache.fast_writes 0 # nu
|
|||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 2064 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 2204179585005864704 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 2.824818 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 1927 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 301972603145803464704 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 387 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.066376 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 137 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
|
|
@ -81,17 +81,17 @@ system.cpu.dcache.total_refs 1927 # To
|
|||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 5658 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 1549898021785231104 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 2.993399 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.993399 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 5355 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 469619100600925028352 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 907 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.053552 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 604 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.053552 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 17.673267 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
|
|
@ -99,10 +99,10 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 5658 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 1549898021785231104 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 2.993399 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 1.993399 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 5355 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 469619100600925028352 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 907 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.053552 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 303 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
|
|
@ -113,11 +113,11 @@ system.cpu.icache.fast_writes 0 # nu
|
|||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 5658 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 1549898021785231104 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 2.993399 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 1.993399 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 5355 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 469619100600925028352 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 907 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.053552 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 303 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
|
|
|
|||
|
|
@ -6,8 +6,8 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 18 2006 00:09:15
|
||||
M5 started Fri Aug 18 00:12:56 2006
|
||||
M5 compiled Aug 21 2006 14:43:46
|
||||
M5 started Mon Aug 21 14:44:00 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing
|
||||
Exiting @ tick 8573 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,28 +1,28 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 619761 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 158236 # Number of bytes of host memory used
|
||||
host_seconds 0.81 # Real time elapsed on the host
|
||||
host_tick_rate 845354 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 310464 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 159200 # Number of bytes of host memory used
|
||||
host_seconds 1.61 # Real time elapsed on the host
|
||||
host_tick_rate 423570 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 500000 # Number of instructions simulated
|
||||
sim_seconds 0.000001 # Number of seconds simulated
|
||||
sim_ticks 682354 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 124564 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency -2174448991928520960 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 2.987952 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 124315 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency -541437798990201749504 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 744 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.001999 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 249 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 496 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001991 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 248 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 56744 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency -6113309131580347 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 1.256024 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 56412 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency -2029618631684675072 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 417 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.005851 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 332 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 278 # number of WriteReq MSHR miss cycles
|
||||
|
|
@ -37,10 +37,10 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 181308 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency -935400030330269184 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 1.998279 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 180727 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency -543467417621886402560 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 1161 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.003204 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 581 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
|
|
@ -51,11 +51,11 @@ system.cpu.dcache.fast_writes 0 # nu
|
|||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 181308 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency -935400030330269184 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 1.998279 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 180727 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency -543467417621886402560 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 1161 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.003204 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 581 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
|
|
@ -81,10 +81,10 @@ system.cpu.dcache.total_refs 180727 # To
|
|||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 500000 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency -561967136127090496 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 499597 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency -226472755859217481728 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 1209 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000806 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 403 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 806 # number of ReadReq MSHR miss cycles
|
||||
|
|
@ -99,10 +99,10 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 500000 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency -561967136127090496 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 3 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 499597 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency -226472755859217481728 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 1209 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000806 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 403 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
|
|
@ -113,11 +113,11 @@ system.cpu.icache.fast_writes 0 # nu
|
|||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 500000 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency -561967136127090496 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 3 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 499597 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency -226472755859217481728 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 1209 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000806 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 403 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
|
|
|
|||
|
|
@ -7,8 +7,8 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 18 2006 00:06:43
|
||||
M5 started Fri Aug 18 00:12:49 2006
|
||||
M5 compiled Aug 21 2006 14:18:48
|
||||
M5 started Mon Aug 21 14:19:29 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing
|
||||
Exiting @ tick 682354 because a thread reached the max instruction count
|
||||
|
|
|
|||
Loading…
Reference in a new issue