Add caches in, fix cpu.mem param

--HG--
extra : convert_revision : 486283d83786807c72bb4601e4b9613b55d8802c

tests/configs/simple-atomic.py

@@ -34,5 +34,6 @@ system = System(cpu = AtomicSimpleCPU(),
                 membus = Bus())
 system.physmem.port = system.membus.port
 system.cpu.connectMemPorts(system.membus)
+system.cpu.mem = system.physmem
 
 root = Root(system = system)

tests/configs/simple-timing.py

@@ -37,8 +37,9 @@ class MyCache(BaseCache):
     tgts_per_mshr = 5
 
 cpu = TimingSimpleCPU()
-#cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
-#                              MyCache(size = '2MB'))
+cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
+                              MyCache(size = '2MB'))
+cpu.mem = cpu.dcache
 
 system = System(cpu = cpu,
                 physmem = PhysicalMemory(),

tests/configs/tsunami-simple-atomic-dual.py

@@ -39,5 +39,6 @@ system = FSConfig.makeLinuxAlphaSystem('atomic')
 system.cpu = cpus
 for c in cpus:
     c.connectMemPorts(system.membus)
+    c.mem = system.physmem
 
 root = Root(clock = '2GHz', system = system)

tests/configs/tsunami-simple-atomic.py

@@ -35,5 +35,6 @@ cpu = AtomicSimpleCPU()
 system = FSConfig.makeLinuxAlphaSystem('atomic')
 system.cpu = cpu
 cpu.connectMemPorts(system.membus)
+cpu.mem = system.physmem
 
 root = Root(clock = '2GHz', system = system)

tests/configs/tsunami-simple-timing-dual.py

@@ -39,5 +39,6 @@ system = FSConfig.makeLinuxAlphaSystem('timing')
 system.cpu = cpus
 for c in cpus:
     c.connectMemPorts(system.membus)
+    c.mem = system.physmem
 
 root = Root(clock = '2GHz', system = system)

tests/configs/tsunami-simple-timing.py

@@ -35,5 +35,6 @@ cpu = TimingSimpleCPU()
 system = FSConfig.makeLinuxAlphaSystem('timing')
 system.cpu = cpu
 cpu.connectMemPorts(system.membus)
+cpu.mem = system.physmem
 
 root = Root(clock = '2GHz', system = system)