Commit graph

4047 commits

Author SHA1 Message Date
Gabe Black
3f4b098985 Added a stub initCPU function. This would be a good place to force in a PowerOnReset fault to kick start the CPU.
--HG--
extra : convert_revision : 79e1fa2ef40e326682069639e260db255fd29d93
2006-11-03 11:04:10 -05:00
Gabe Black
6b701a6d25 Compilation fixes.
--HG--
extra : convert_revision : 44d67a3bb95f875f17586499aa4a04268aa2fd46
2006-11-03 11:03:03 -05:00
Gabe Black
70c0ba22c4 Added this constant to get compilation to work. The value is bogus since I don't know what it actually represents.
--HG--
extra : convert_revision : ab579c1275bfcfb7ffe21633bd8c5b9bea24015e
2006-11-03 10:59:24 -05:00
Gabe Black
ab651344dd Add the syscall number as the second parameter for the trap fault. This could be improved and syscalls could be called from the trap's invoke method.
--HG--
extra : convert_revision : 127a3673a076110fb3605c0fbc93e8d7e9fec84b
2006-11-03 10:56:47 -05:00
Gabe Black
e6fed44625 Add an invoke function for PowerOnReset
--HG--
extra : convert_revision : a1cdd35c74f6e85f42a04061b466ec7617da8ac2
2006-11-03 10:55:29 -05:00
Gabe Black
694323b7c4 Move around misc reg code
src/arch/sparc/faults.cc:
    Moved some code here from miscregfile.cc
src/arch/sparc/miscregfile.cc:
    Moved code from here to faults.cc, and merged (read|set)MiscRegWithEffect and it's FS version from ua2005.cc
src/arch/sparc/miscregfile.hh:
    readFSRegWithEffect is no longer a seperate function, and is instead done in the main readRegWith Effect.

--HG--
extra : convert_revision : 0b45f0f78e83929b32ddd2f443c8b1dbf9bc04fb
2006-11-03 10:54:34 -05:00
Gabe Black
7c5a859243 removed ua2005.cc since it's been obsorbed into the miscregfile, and added system.cc
--HG--
extra : convert_revision : 2a124adcefe0d15860632a05e8788d3fd34008c2
2006-11-03 10:52:08 -05:00
Gabe Black
118b9dc1f9 Got rid of "inPalMode". Some places are still effectively checking if they are in PAL mode, however.
--HG--
extra : convert_revision : b52d9642efc474eaf97437fa2df879efefa0062b
2006-11-03 04:25:33 -05:00
Gabe Black
c8fc116c76 Add a new file which describes an ISA's interrupt handling mechanism. It records when interrupts are requested, and returns an interrupt to execute if the
--HG--
extra : convert_revision : c535000a6a170caefd441687b60f940513d29739
2006-11-03 02:25:39 -05:00
Gabe Black
fa91832900 Fixed a comment
--HG--
extra : convert_revision : bebc701508e1d38ee74a07377c634d5e46e89abe
2006-11-03 01:15:31 -05:00
Kevin Lim
e71ccde663 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix

--HG--
extra : convert_revision : a9a41e2c292bd95aa148e1cf4d9a77c0622a462b
2006-11-02 15:20:47 -05:00
Kevin Lim
45363ea658 Have bus use the BadAddress device to handle bad addresses. The O3 CPU should be able to boot into Linux with caches on after this change.
src/mem/bus.cc:
src/mem/bus.hh:
    Bus now will be setup with a default responder, unless the user overrides it.  This default responder should return BadAddress if no matching port is found.
src/python/m5/objects/Bus.py:
    Bus now has a default responder for FS mode if the user doesn't override it.  It returns BadAddress if no matching port is found.
src/python/m5/objects/Tsunami.py:
    Add bad address device.  Also record when the user has specified their own default responder.

--HG--
extra : convert_revision : 59070477ae313ee711b2d59baa2369c9a91c5b85
2006-11-02 15:20:37 -05:00
Kevin Lim
c3485a6548 Implement device that will return BadAddress.
--HG--
extra : convert_revision : d833c20f691e01c84a0678f19f7d83f3ee50c0c1
2006-11-02 15:18:35 -05:00
Kevin Lim
8d53f298a6 Caches return a new functional port whenever asked for one.
src/mem/cache/base_cache.cc:
    Have caches return a new functional port whenever asked for them.  I'm pretty sure this is desired behavior.  Ron can correct me if it's not.

--HG--
extra : convert_revision : e1fadf895a7d714968128ff900d10e86fde53387
2006-11-02 15:17:45 -05:00
Kevin Lim
dd5e2cd959 More proper handling of the ports.
src/cpu/simple_thread.cc:
    Fix up port handling to share code.
src/cpu/thread_state.cc:
    Separate code off into a function.
src/cpu/thread_state.hh:
    Make a separate function that will get the CPU's memory's functional port.

--HG--
extra : convert_revision : 96a9bb3c5e4b9ba5511678c0fd17f0017c8cd312
2006-11-02 14:58:31 -05:00
Kevin Lim
64f8cd12c6 Remove function that should have been deleted.
src/cpu/simple_thread.cc:
    This function should have been deleted from an earlier push.
src/cpu/simple_thread.hh:
    Delete this function; it's now in thread_state.hh/.cc.

--HG--
extra : convert_revision : f78dcf9c2b388418030d48d0ea4911c8b8b1f5ff
2006-11-02 13:12:36 -05:00
Kevin Lim
ccaf80cc46 Use ISA specific makeExtMI.
src/arch/alpha/utility.hh:
    For now makeExtMI will be specific to the ISA.

--HG--
extra : convert_revision : 89959c6499efcc3df9301ad8ea039580764a1496
2006-11-02 13:11:38 -05:00
Lisa Hsu
683d8f0831 Merge zizzer:/bk/newmem
into  zed.eecs.umich.edu:/z/hsul/work/m5/newmem

--HG--
extra : convert_revision : a30e2da1f0a272b8c867c0e7a3491118be92bc5e
2006-11-01 19:25:20 -05:00
Lisa Hsu
74ff45d353 factor some more commone code and enable going from checkpoint into arbitrary CPU with or without caches.
configs/common/Simulation.py:
    enable going from checkpoint into arbitrary CPU with or without caches.

--HG--
extra : convert_revision : 02e7ff8982fdb3a08bc609f89bd58df5b3a581b2
2006-11-01 19:25:09 -05:00
Gabe Black
b565660c42 Merge zizzer.eecs.umich.edu:/bk/newmem/
into  zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops

--HG--
extra : convert_revision : c2f7398a0d14dd11108579bb243ada7420285a22
2006-11-01 19:00:59 -05:00
Gabe Black
8dbab9f701 Added code to handle draining.
--HG--
extra : convert_revision : 3861f553bde5865cd21a8a58a4c410896726f0a3
2006-11-01 19:00:49 -05:00
Gabe Black
6f78d49410 Fix a range check on the ipr_index.
--HG--
extra : convert_revision : 84e25abd4bb2de0c877c883804d39feb019c7030
2006-11-01 18:46:18 -05:00
Gabe Black
2b11b47357 Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing register file functions to not take faults
--HG--
extra : convert_revision : 1cef0734462ee2e4db12482462c2ab3c134d3675
2006-11-01 16:44:45 -05:00
Lisa Hsu
7665be4f70 make it so that you can do a standard switch without the caches option. this will have only the o3 cpu have a cache, rather than timing (warmup) + o3 have cache.
--HG--
extra : convert_revision : d733de7ebb362bbd7376a0235ee7f117df2d6d37
2006-11-01 11:49:39 -05:00
Lisa Hsu
9ef8bf74c7 change name of 2nd switch_cpu so that ckpt recovery with multiple cpus doens't get confused.
--HG--
extra : convert_revision : 16c710c4196c520d03c1993a26f38cf1f04ab637
2006-11-01 11:40:49 -05:00
Gabe Black
f3ba6d20f6 Arg!
--HG--
extra : convert_revision : 8328d002780c0291e7eb264076a62084de88b7a5
2006-10-31 18:59:50 -05:00
Gabe Black
1543c3d0a1 More typos! I need to get nfs to work.
--HG--
extra : convert_revision : f5693e96d376254f777fb0cce7b5be3d36efbea9
2006-10-31 18:51:26 -05:00
Gabe Black
1dd903e856 Fix another typo
--HG--
extra : convert_revision : ad7058babf2a13bfe543e05f2662dc49a18a8b8b
2006-10-31 18:39:17 -05:00
Gabe Black
39de635fbf Check for out of range IPR values as well.
--HG--
extra : convert_revision : 9ca241bb71d8a1d022e54485383a88d2abece663
2006-10-31 18:19:45 -05:00
Gabe Black
45368c0300 Fix stupid typo
--HG--
extra : convert_revision : fbfc82974e89b2c726b689674c9f5d957682b280
2006-10-31 18:01:31 -05:00
Gabe Black
fb5ba85abb Make two simple utility functions to determine if a MiscReg index corresponding to an IPR is readable or writable.
--HG--
extra : convert_revision : 89eebba5eec01e629213997d24c734a6acad0ecb
2006-10-31 17:50:57 -05:00
Gabe Black
312a4710d7 Forgot to add intr_flag in one place.
--HG--
extra : convert_revision : 637256098e2283c18f98bdaabf21f3039d162a15
2006-10-31 17:14:46 -05:00
Gabe Black
ad201172c9 We don't include ipr.cc in SE builds, so don't call it.
--HG--
extra : convert_revision : 45e52d7afbf74e0ddde11f58aeb084186389fc06
2006-10-31 16:59:41 -05:00
Gabe Black
ace4f0c188 Made the old name refer to the miscreg index to prevent having to change code all over the place.
--HG--
extra : convert_revision : e890a3ce420336acdb220396dcbf66d4b9974c76
2006-10-31 16:36:45 -05:00
Gabe Black
44f2c05118 Forgot to change the index.
--HG--
extra : convert_revision : 5a444e635d20bcca445a10e43592b6c10d25e879
2006-10-31 16:18:54 -05:00
Gabe Black
ece796ab8a Make the IPRs use regular miscreg indexes, and make a table or two to find the miscreg index of a specific IPR.
--HG--
extra : convert_revision : dd235261e7086d6667b1b2bdc4a81b2573e21d53
2006-10-31 16:02:28 -05:00
Kevin Lim
f763864786 Fix up configs.
configs/common/Simulation.py:
    Remove mem parameter.
configs/example/se.py:
    Remove debug output that got included in my other push.

--HG--
extra : convert_revision : 643c34147f6c6cbb98b8e6d6e8206b9859593ab0
2006-10-31 14:58:09 -05:00
Kevin Lim
2fa535f740 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem

--HG--
extra : convert_revision : 88fa7ae5cc32be068787ee381fae9d8de0e9bd0f
2006-10-31 14:44:23 -05:00
Kevin Lim
5825a6c9d8 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix

configs/example/fs.py:
configs/example/se.py:
src/mem/tport.hh:
    Hand merge.

--HG--
extra : convert_revision : b9df95534d43b3b311f24ae24717371d03d615bf
2006-10-31 14:37:19 -05:00
Kevin Lim
bfd5eb2b08 Remove mem parameter. Now the translating port asks the CPU's dcache's peer for its MemObject instead of having to have a paramter for the MemObject.
configs/example/fs.py:
configs/example/se.py:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
src/cpu/thread_state.cc:
src/cpu/thread_state.hh:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
tests/configs/simple-atomic-mp.py:
tests/configs/simple-atomic.py:
tests/configs/simple-timing-mp.py:
tests/configs/simple-timing.py:
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
    No need for mem parameter any more.
src/cpu/checker/cpu.cc:
    Use new constructor for simple thread (no more MemObject parameter).
src/cpu/checker/cpu.hh:
    Remove MemObject parameter.
src/cpu/memtest/memtest.hh:
    Ports now take in their MemObject owner.
src/cpu/o3/alpha/cpu_builder.cc:
    Remove mem parameter.
src/cpu/o3/alpha/cpu_impl.hh:
    Remove memory parameter and clean up handling of TranslatingPort.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/mips/cpu_builder.cc:
src/cpu/o3/mips/cpu_impl.hh:
src/cpu/o3/params.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_builder.cc:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/simple_params.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/simple/atomic.cc:
    Remove memory parameter.

--HG--
extra : convert_revision : 43cb44a33b31320d44b69679dcf646c0380d07d3
2006-10-31 14:33:56 -05:00
Kevin Lim
b26355daa8 Ports now have a pointer to the MemObject that owns it (can be NULL).
src/cpu/simple/atomic.hh:
    Port now takes in the MemObject that owns it.
src/cpu/simple/timing.hh:
    Port now takes in MemObject that owns it.
src/dev/io_device.cc:
src/mem/bus.hh:
    Ports now take in the MemObject that owns it.
src/mem/cache/base_cache.cc:
    Ports now take in the MemObject that own it.
src/mem/port.hh:
src/mem/tport.hh:
    Ports now optionally take in the MemObject that owns it.

--HG--
extra : convert_revision : 890a72a871795987c2236c65937e06973412d349
2006-10-31 13:59:30 -05:00
Ali Saidi
7f39644609 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem.head

--HG--
extra : convert_revision : 42712a50ca46ebc891b78186f4b6d1412a35d374
2006-10-31 13:24:00 -05:00
Ali Saidi
17141a1be9 remove connectAll() and connect() code since it isn't used anymore. (The python does it all)
--HG--
extra : convert_revision : e16a1ff59d4522703b155c2e68379a3072e8f47f
2006-10-31 13:23:49 -05:00
Ali Saidi
c68f7feaa8 add the ability to insert into the middle of the timing port send list
--HG--
extra : convert_revision : 5422025f74ba7013f98d1d1dcbd1070f580aae61
2006-10-31 13:23:17 -05:00
Gabe Black
3c19c5f0f2 Missed a few instances of this function.
--HG--
extra : convert_revision : 581f97dafc2b30bd5067f6ff7f9cdbabc6890622
2006-10-31 04:12:52 -05:00
Gabe Black
eab445e1bc Get rid of old, commented out code.
--HG--
extra : convert_revision : 46e9f26917efab642b80ea9e4303ec95d43d935e
2006-10-31 03:44:39 -05:00
Gabe Black
038217049a Move IntrFlag into the MiscRegFile and get rid of specialized accessor functions.
--HG--
extra : convert_revision : e0d12a150b01d05de9bc02bcbc7c22797975a5b9
2006-10-31 03:37:01 -05:00
Gabe Black
4862879a94 Put the Alpha tlb stuff into the AlphaISA namespace, and give the classes more neutral names.
--HG--
extra : convert_revision : 702c715b7516a16602172deb1b78d6a7ab848fd4
2006-10-31 02:08:44 -05:00
Steve Reinhardt
79d4bede42 Delete obsolete directories: src/oldmem, src/mem/timing, src/mem/NOTES.
--HG--
extra : convert_revision : 948b4aaf484f7f7c2fce16201cd51ecb111af7d4
2006-10-30 23:53:20 -05:00
Lisa Hsu
697b432ba8 FSConfig.py:
Accidentally committed this last time

configs/common/FSConfig.py:
    Accidentally committed this last time

--HG--
extra : convert_revision : 32d49c17c661b57a9aa9c3b057258f6e037ba745
2006-10-30 16:55:52 -05:00