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Author SHA1 Message Date
Lisa Hsu
580c8421ab se.py, fs.py: 
import Caches
Simulation.py:
Fix typo - L2Cache --> L1Cache

configs/common/Simulation.py:
    Fix typo - L2Cache --> L1Cache
configs/example/fs.py:
configs/example/se.py:
    import Caches

--HG--
extra : convert_revision : 4292225b322c069665262eab7c83b5341844fba0
 2006-10-30 16:51:46 -05:00
Lisa Hsu
fe2698c435 ensure that there is a "/" between the cptdir and the cpt.%d. 
--HG--
extra : convert_revision : 9aed7c3aecad10b039f3cfb26e04a7950be6bed1
 2006-10-30 14:19:16 -05:00
Lisa Hsu
13cbd4e94b Merge zizzer:/bk/newmem 
into  zed.eecs.umich.edu:/z/hsul/work/m5/newmem

--HG--
extra : convert_revision : 836fcb45f399ed4f860be2d0bfe2ac4709bfe2ef
 2006-10-30 14:15:50 -05:00
Lisa Hsu
883f0394f5 decouple the switch option from the warmup period option - parsing was confused otherwise, oops. 
--HG--
extra : convert_revision : 951fc664c59363df5f5e026aa791d83c26f050ec
 2006-10-30 14:12:15 -05:00
Kevin Lim
bc93802fb8 Use some python os.path stuff to make it more flexible where we can execute this script from. 
--HG--
extra : convert_revision : a76861a0f2669a7cd3bf3a34177739c69a913545
 2006-10-30 14:01:34 -05:00
Lisa Hsu
9be53b10b3 Merge zizzer:/bk/newmem 
into  zed.eecs.umich.edu:/z/hsul/work/m5/newmem

--HG--
extra : convert_revision : ce5f394a4a62f7452b9631763425f65b911387bb
 2006-10-30 13:33:38 -05:00
Lisa Hsu
b40af2328a add some comments and make the warmup period in a switchover parameterizable. 
configs/common/Options.py:
    make the warmup period in a standard switch part of the option.
configs/common/Simulation.py:
    add some comments and also make the warmup period an option.

--HG--
extra : convert_revision : 0fa587291b97ff87c3b3a617e7359ac6d9bed7a5
 2006-10-30 13:33:27 -05:00
Gabe Black
628a3b1d01 An attempt to serialize the state of the micro code mechanism in the simple cpu. 
src/cpu/simple/base.cc:
    Make a microcoded op start at the current micropc, rather than starting at 0.
src/cpu/thread_state.cc:
    Serialize the microPC and nextMicroPC

--HG--
extra : convert_revision : 5302215f17312ecef3ff4c6548acb05297ee4ff6
 2006-10-29 04:04:50 -05:00
Gabe Black
349c7aff9b Move the mem classes into util.isa so that multiple inheritance can be used in the future for micro insts. 
--HG--
extra : convert_revision : c71faa5e43b56ed15d00ed5fd57c020d1c845445
 2006-10-29 03:40:52 -05:00
Gabe Black
6e66de7c75 Fix when the IsDelayedCommit flag is set. 
--HG--
extra : convert_revision : ab6cd69f82b2013d66a91beaa3e39d8f417a9251
 2006-10-29 03:26:41 -05:00
Gabe Black
9adba8d98e Bring casa and casxa up to date 
src/arch/sparc/isa/decoder.isa:
    Fix up the casa and casxa instructions.
src/arch/sparc/isa/formats/formats.isa:
    This is handled in loadstore.isa now
src/arch/sparc/isa/formats/mem/basicmem.isa:
src/arch/sparc/isa/formats/mem/blockmem.isa:
    Renamed doSplitExecute to doDualSplitExecute. This differentiates between the version that does both a register and immediate version, and one that just does a register version.
src/arch/sparc/isa/formats/mem/mem.isa:
    The cas format is handled in loadstore.isa as well now.
src/arch/sparc/isa/formats/mem/util.isa:
    Reorganized things a bit to better support cas

--HG--
extra : convert_revision : 12411e89e763287e52f9825bf7a417b263c1037f
 2006-10-29 02:57:32 -05:00
Gabe Black
ce313a15d5 Fixed ldstub to use the right format, and made the load/store operations use the integer microcode register. 
--HG--
extra : convert_revision : 7df5bd4bbe8a2607c7d2b4799826831d6a440926
 2006-10-29 01:59:30 -05:00
Gabe Black
6dddca9511 Add an integer microcode register. 
--HG--
extra : convert_revision : f23dbfdfe44e8e6cdd6948000669ad4f743b9fb4
 2006-10-29 01:58:37 -05:00
Ali Saidi
61c808ae1c Merge zizzer:/bk/newmem 
into  zeep.pool:/z/saidi/work/m5.newmem.head

--HG--
extra : convert_revision : df73fd850d6638cbce6ff31203857f51235b8763
 2006-10-28 13:17:05 -04:00
Ali Saidi
14f53b9b6b remove intel nic from SConscript 
--HG--
extra : convert_revision : b01bb258c97cf42d46a94faedab31726623fe437
 2006-10-28 13:16:53 -04:00
Gabe Black
ab6b6a9202 This one really needs to be arch/faults.hh 
--HG--
extra : convert_revision : aad1ee04ade9f4394c9ef0386f23d6f2ca373412
 2006-10-28 04:44:05 -04:00
Gabe Black
7f1463f94a Include the right version of faults.hh 
--HG--
extra : convert_revision : 4762b8ab46ac755726cc658a378c2cf5b2061dc3
 2006-10-28 04:00:24 -04:00
Gabe Black
477693c519 Merge zizzer.eecs.umich.edu:/bk/newmem 
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem

--HG--
extra : convert_revision : 9883fb35fd9c36e1819153f9976f8bdc73dbe8f3
 2006-10-28 03:48:23 -04:00
Gabe Black
27ef642a76 One last adjustment to get rid of skew in the simple atomic cpu. 
--HG--
extra : convert_revision : 8e46929ed7da5dae6888f773de4e1ecc9b249fe0
 2006-10-28 03:44:55 -04:00
Lisa Hsu
2305490de5 Merge zizzer:/bk/newmem 
into  zed.eecs.umich.edu:/z/hsul/work/m5/newmem

configs/example/fs.py:
configs/example/se.py:
    hand merge

--HG--
extra : convert_revision : 13d248add87ac373d2653bb42adf4ac065f75ce3
 2006-10-27 16:40:06 -04:00
Lisa Hsu
a6fd29ddf9 factor out common run code from se.py and fs.py. 
configs/example/fs.py:
    factor out common code.
configs/example/se.py:
    factor out common code

--HG--
extra : convert_revision : 72a1f653c84eae1b7d281e0a5e60ee116ad6b27d
 2006-10-27 16:32:26 -04:00
Ali Saidi
8a0c79a315 Merge zizzer:/bk/newmem 
into  zeep.pool:/z/saidi/work/m5.newmem.head

--HG--
extra : convert_revision : b8b8a4428b2462d2df600e2ec7a9014a08246df8
 2006-10-27 09:11:02 -04:00
Ali Saidi
baaadb0d43 add packet_access.hh 
--HG--
extra : convert_revision : 7fe4958549101fca9613baa4a317d96f4970d432
 2006-10-27 09:10:50 -04:00
Gabe Black
a46e19f738 A more complete attempt to fix the clock skew. 
--HG--
extra : convert_revision : b2d505de51fc5fcae5177b2a13140729474e249e
 2006-10-27 07:09:14 -04:00
Gabe Black
d5974eff73 Potential fix to clock skew problem. 
--HG--
extra : convert_revision : 51572523190a886fd0ff64817edc88e260c5fa9d
 2006-10-27 06:51:28 -04:00
Gabe Black
f985b752d3 Merge zizzer.eecs.umich.edu:/bk/newmem 
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem

--HG--
extra : convert_revision : ec35a9276ae21e0b9fe820bd700c020e4440a350
 2006-10-27 02:34:26 -04:00
Gabe Black
ca34c62bf9 Update stats for fill/spill handlers 
--HG--
extra : convert_revision : 2ed2e868ccbb3316f84ea691497d2e0dd4ec2416
 2006-10-27 02:21:09 -04:00
Gabe Black
709d50cd6b Got rid of some outdated comments. 
--HG--
extra : convert_revision : 30fa768c4a934cf5f9dc0ad84e0e421327ccbed3
 2006-10-27 01:43:51 -04:00
Gabe Black
b1cc98ed54 Made the regfile compatible with the new definitions in MiscRegFile 
--HG--
extra : convert_revision : d63ea6fb1e549e737204ee6653c06f89ec5e43ef
 2006-10-27 01:43:26 -04:00
Gabe Black
944bfde6b3 Clean up MiscRegFile 
--HG--
extra : convert_revision : 3bc792596c99df3a5c2c82da58b801a63ccf6ddb
 2006-10-27 01:36:42 -04:00
Gabe Black
2cb190d1e3 Reorganized the MiscRegFile 
--HG--
extra : convert_revision : 088112c9b8a4ea09c8015da5a0b65ed2fc9398d2
 2006-10-26 22:48:02 -04:00
Gabe Black
f33bab2386 Cleaned up the decoder slightly. 
--HG--
extra : convert_revision : a7050aa8768c132f0161f00ba17ae02d71f0b829
 2006-10-26 22:47:17 -04:00
Gabe Black
f88b90dd56 Added a few functions to stuff values into bitfields in an instruction. 
--HG--
extra : convert_revision : 507d7e13fd6276acf36b75eba31dff5e8080113f
 2006-10-26 20:25:22 -04:00
Gabe Black
d1b30102fd Changed the number of register windows to be more realistic. 
--HG--
extra : convert_revision : ae557307f377b19bae82226dafa8b4b2654cae52
 2006-10-26 20:24:01 -04:00
Gabe Black
5024b20278 Got rid of some debug output 
--HG--
extra : convert_revision : 6e98cf839dc92bde5f06f9b9bf11ca6ac661c907
 2006-10-26 20:23:00 -04:00
Gabe Black
e441be1b82 Change the default function from setMiscRegWithEffect to setMiscReg 
--HG--
extra : convert_revision : bedf422d51a52b009390b1e94f5330f752be2b87
 2006-10-26 20:22:23 -04:00
Lisa Hsu
2f30c2b4c9 Merge zizzer:/bk/newmem 
into  zed.eecs.umich.edu:/z/hsul/work/m5/clean

--HG--
extra : convert_revision : cb3f718bdcbd52540747a2696fb37bb4fcfe27a3
 2006-10-26 16:04:27 -04:00
Lisa Hsu
260b3c0cf0 se.py: 
make the same os.getcwd fix ali made in fs.py, make connectMemPorts occur after caches are created.

configs/example/se.py:
    make the same os.getcwd fix ali made in fs.py, make connectMemPorts occur after caches are created.

--HG--
extra : convert_revision : 9760ae073d97cd62d3e44f10199d31cce79d4a1d
 2006-10-26 16:04:09 -04:00
Ali Saidi
d626a32c52 Merge zizzer:/bk/newmem 
into  zeep.pool:/z/saidi/work/m5.newmem.head

--HG--
extra : convert_revision : 473901bcd44bd2c563a3293d7326cd5aed8b630f
 2006-10-26 15:49:19 -04:00
Kevin Lim
e912080d12 Merge ktlim@zizzer:/bk/newmem 
into  zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem

--HG--
extra : convert_revision : 30a912cf5d3f205a6301d291dd1799da21663056
 2006-10-26 14:37:19 -04:00
Kevin Lim
6824cdf660 Remove old py file. 
--HG--
extra : convert_revision : 91baa74139f65cab788f440fff06cd2415bdeb46
 2006-10-26 14:22:46 -04:00
Ali Saidi
f4be29804f Fix simple timing port keep a list of all packets, have only one event, and scan all packets on a functional access. 
--HG--
extra : convert_revision : c735a6408443b5cc90d1c1841c7aeb61e02ec6ae
 2006-10-25 18:34:21 -04:00
Gabe Black
93b3176d4e Fixed the priv instruction format. 
src/arch/sparc/isa/formats/priv.isa:
    Fix the priv format so that it uses isa_parser operands rather than accessing the registers directly in checkCode. Also, the expressions needed to be negated.
src/arch/sparc/isa/operands.isa:
    Added an Hpstate operand, and adjusted the numbering.

--HG--
extra : convert_revision : 4a70862df061aa9e1b9eab125c4c2fc839ac3b5a
 2006-10-25 17:58:44 -04:00
Gabe Black
99d9d40e6c Implemented the saved and restored instructions, fixed up register window instructions so that the cwp is modified at the correct time (when handling the fault), and fixed the "done" instruction. 
--HG--
extra : convert_revision : 3c9144422f087af1d375782cce1c9b77ca7936c9
 2006-10-25 17:54:14 -04:00
Gabe Black
047455625e Fixed the bitfield FCN to include the right bits. 
--HG--
extra : convert_revision : 040beb4dd982784773c3c3ad04cc48c2dc98b58c
 2006-10-25 17:50:39 -04:00
Gabe Black
e2eef8859b Implemented the SPARC fill and spill handlers. 
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
    Added a function to do normal SPARC trap processing, and implemented the spill and fill faults for SE
src/arch/sparc/process.cc:
src/arch/sparc/process.hh:
    Added fill and spill handlers which are stuffed into the processes address space. The location of these handlers are stored in fillStart and spillStart.

--HG--
extra : convert_revision : 59adb96570cce86f373fbc2c3e4c05abe1742d3b
 2006-10-25 17:49:41 -04:00
Ron Dreslinski
eda7148af2 Fix fixPacket functionality to calculate sizes properly 
src/mem/packet.cc:
    Copy size is calculated by END-BEGIN not BEGIN-END

--HG--
extra : convert_revision : 0e2725c5551f8f70ff05cb285e0822afc0bb3f87
 2006-10-25 14:14:37 -04:00
Gabe Black
1b1495930c Replace the Alpha No op with a SPARC one. 
--HG--
extra : convert_revision : bed03e63dc80bf24f21bad08e6553d7aab92c7b3
 2006-10-24 15:50:41 -04:00
Ali Saidi
86bd01dfc9 Fix fs.py. Lisa did you test this? Is there some wierd python version thing? 
--HG--
extra : convert_revision : 6df5f90d5b66e7af27d4f524744b9dc3c703a588
 2006-10-24 13:10:31 -04:00
Ali Saidi
0f98905ecc Merge zizzer:/bk/newmem 
into  zeep.pool:/z/saidi/work/m5.newmem.head

--HG--
extra : convert_revision : 4db140e6e8408b3ed39da327515b8e88a2701e6b
 2006-10-24 12:59:19 -04:00