Gabe Black
3f12eb02ab
ARM: Implement the unsigned 8 bit and 16 bit vector adds and subtracts.
2010-06-02 12:58:06 -05:00
Gabe Black
29acf9516c
ARM: Decode the unsigned saturating instructions.
2010-06-02 12:58:06 -05:00
Gabe Black
be888e67e7
ARM: Implement the unsigned saturating instructions.
2010-06-02 12:58:06 -05:00
Gabe Black
5495ebd68d
ARM: Decode the ssub instructions.
2010-06-02 12:58:06 -05:00
Gabe Black
fd6e9f304e
ARM: Implement the ssub instructions.
2010-06-02 12:58:06 -05:00
Gabe Black
bcf0454864
ARM: Decode the SADD8 and SADD16 instructions.
2010-06-02 12:58:06 -05:00
Gabe Black
87975aa691
ARM: Implement the SADD8 and SADD16 instructions.
2010-06-02 12:58:06 -05:00
Gabe Black
d70c31437a
ARM: Support instructions that set the GE bits when they write the condition codes.
2010-06-02 12:58:06 -05:00
Gabe Black
e32aaefe8c
ARM: Decode 32 bit thumb data processing register instructions.
2010-06-02 12:58:06 -05:00
Gabe Black
f19b605aed
ARM: Decode the 16 bit thumb versions of the REV* instructions.
2010-06-02 12:58:06 -05:00
Gabe Black
15356af288
ARM: Decode the ARM version of the REV* instructions.
2010-06-02 12:58:05 -05:00
Gabe Black
59c726b6f4
ARM: Pull decoding of ARM pack, unpack, saturate and reverse instructions into a format.
2010-06-02 12:58:05 -05:00
Gabe Black
aa8493d7d1
ARM: Implement the REV* instructions.
2010-06-02 12:58:05 -05:00
Gabe Black
c981a4de2b
ARM: Add base classes suitable for the REV* instructions.
2010-06-02 12:58:05 -05:00
Gabe Black
57443a2144
ARM: Make LDM that loads the PC perform an interworking branch.
2010-06-02 12:58:05 -05:00
Gabe Black
1344fc2668
ARM: Decode the swp and swpb instructions.
2010-06-02 12:58:05 -05:00
Gabe Black
e157b1f52a
ARM: Implement the swp and swpb instructions.
2010-06-02 12:58:05 -05:00
Gabe Black
1884ed65bd
ARM: Decode MRS and MSR for thumb.
2010-06-02 12:58:05 -05:00
Gabe Black
ff3b21bc2b
ARM: Replace the versions of MRS and MSR in the ARM decoder with the new ones.
2010-06-02 12:58:05 -05:00
Gabe Black
f0811eb208
ARM: Define versions of MSR and MRS outside the decoder.
2010-06-02 12:58:05 -05:00
Gabe Black
f61bb9adb9
ARM: Hook up the push/pop versions of stm/ldm in thumb.
2010-06-02 12:58:05 -05:00
Gabe Black
a76ab8e040
ARM: Hook SVC into the thumb decoder.
2010-06-02 12:58:05 -05:00
Gabe Black
cbdebf852e
ARM: Implement SVC (was SWI) outside of the decoder.
2010-06-02 12:58:05 -05:00
Gabe Black
caa95639ec
ARM: Update the stats for the new syscall behavior.
2010-06-02 12:58:05 -05:00
Gabe Black
34032f97d6
ARM: Trigger system calls from the SupervisorCall invoke method.
...
This simplifies the decoder slightly, and makes the system call mechanism
very slightly more realistic.
2010-06-02 12:58:05 -05:00
Gabe Black
52460938cb
ARM: Fix multiply operations.
...
These fixes were provided by Ali and fix the saturation condition code and
various multiply instructions.
2010-06-02 12:58:05 -05:00
Gabe Black
4fb6fcd82d
ARM: Decode the scalar saturating add/subtract instructions.
2010-06-02 12:58:05 -05:00
Gabe Black
30dd622622
ARM: Decode the parallel add and subtract instructions.
2010-06-02 12:58:05 -05:00
Gabe Black
62e8487d57
ARM: Implement signed saturating add and/or subtract instructions.
2010-06-02 12:58:05 -05:00
Gabe Black
a1253ec644
ARM: Implemented prefetch instructions/decoding (pli, pld, pldw).
2010-06-02 12:58:05 -05:00
Gabe Black
61b00d3224
ARM: Decode unconditional ARM instructions.
2010-06-02 12:58:04 -05:00
Gabe Black
b6e2f5d33f
ARM: Make sure ldm exception return writes back its base in the right mode.
...
This change moves the writeback of load multiple instructions to the beginning
of the macroop. That way, the MicroLdrRetUop that changes the mode will
necessarily happen later, ensuring the writeback happens in the original mode.
The actual value in the base register if it also shows up in the register list
is undefined, so it's fine if it gets clobbered by one of the loads. For
stores where the base register is the lowest numbered in the register list,
the original value should be written back. That means stores can't write back
at the beginning, but the mode changing problem doesn't affect them so they
can continue to write back at the end.
2010-06-02 12:58:04 -05:00
Gabe Black
89060f1fd8
ARM: Rework how unrecognized/unimplemented instructions are handled.
...
Instead of panic immediately when these instructions are executed, an
UndefinedInstruction fault is returned. In FS mode (not currently
implemented), this is the fault that should, to my knowledge, be triggered in
these situations and should be handled using the normal architected
mechanisms. In SE mode, the fault causes a panic when it's invoked that gives
the same information as the instruction did. When/if support for speculative
execution of ARM is supported, this will allow a mispeculated and unrecognized
and/or unimplemented instruction from causing a panic. Only once the
instruction is going to be committed will the fault be invoked, triggering the
panic.
2010-06-02 12:58:04 -05:00
Gabe Black
aa45fafb2e
ARM: Add support for "SUBS PC, LR and related instructions".
2010-06-02 12:58:04 -05:00
Gabe Black
2419903dc0
ARM: Make ldrs into the PC and ldm exception return do interworking branches.
2010-06-02 12:58:04 -05:00
Gabe Black
28227440a7
ARM: Align the PC when using it as the base for a load.
2010-06-02 12:58:04 -05:00
Gabe Black
d63f748b53
ARM: Implement ADR as separate from ADD.
2010-06-02 12:58:04 -05:00
Gabe Black
e92dc21fde
ARM: Add support for interworking branch ALU instructions.
2010-06-02 12:58:04 -05:00
Gabe Black
11c3361be4
ARM: Fix when the flag bits are updated for thumb.
2010-06-02 12:58:04 -05:00
Gabe Black
14d25fbad0
ARM: Don't rely on undefined behavior to get arithmetic right shift.
...
Shifting to the right of a signed value when the MSB is one is technically
undefined behavior, even though in my experience it's done the "right thing"
and sign extended the value. This replaces the arithmetic right shift code in
ARM that uses that coincidence with some code that relies on bit math.
2010-06-02 12:58:04 -05:00
Gabe Black
05d880f7a1
ARM: Restrict the shift amount from a register to 8 bits.
...
The shift amount when taken from a register is supposed to be truncated to an
8 bit value.
2010-06-02 12:58:04 -05:00
Gabe Black
d8294575e1
ARM: Update the stats now that VFP load/store multiple is implemented.
2010-06-02 12:58:04 -05:00
Gabe Black
9ebaf8ecd5
ARM: Define the VFP load/store multiple instructions.
2010-06-02 12:58:04 -05:00
Gabe Black
3f83094af2
ARM: Decode the VFP load/store multiple instructions.
2010-06-02 12:58:04 -05:00
Gabe Black
647edea970
ARM: Fix the constant describing the number of floating point registers.
2010-06-02 12:58:04 -05:00
Gabe Black
2f3102f1ef
ARM: Add templates for VFP load/store multiple instructions.
2010-06-02 12:58:04 -05:00
Gabe Black
739f23c64c
ARM: Add base classes for VFP load/store multiple.
2010-06-02 12:58:04 -05:00
Gabe Black
cb631d87c3
ARM: Add floating point load/store microops.
2010-06-02 12:58:04 -05:00
Gabe Black
3a11412c99
ARM: Add an fp version of one of the microop indexed registers.
2010-06-02 12:58:04 -05:00
Gabe Black
d5aee75efe
ARM: Move the mmap region to where Linux actually has it.
2010-06-02 12:58:04 -05:00
