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stats: Update stats for unified cache configuration

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This patch updates the stats to reflect the changes in the L2 MSHRs,
as the latter are now uniform across the regressions.
This commit is contained in:
Andreas Hansson 2012-10-30 09:35:32 -04:00
parent 9cbe1cb653
commit 10b70d5452
58 changed files with 24397 additions and 24748 deletions
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456
tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
View file

@ -1,24 +1,62 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.116889 # Number of seconds simulated
sim_ticks 2233777512 # Number of ticks simulated
final_tick 2233777512 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 2.233778 # Number of seconds simulated
sim_ticks 4467555024 # Number of ticks simulated
final_tick 4467555024 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 2000000000 # Frequency of simulated ticks
host_inst_rate 2751599 # Simulator instruction rate (inst/s)
host_op_rate 2752680 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2758381 # Simulator tick rate (ticks/s)
host_mem_usage 518836 # Number of bytes of host memory used
host_seconds 809.81 # Real time elapsed on the host
host_inst_rate 2515301 # Simulator instruction rate (inst/s)
host_op_rate 2516290 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 5043002 # Simulator tick rate (ticks/s)
host_mem_usage 518832 # Number of bytes of host memory used
host_seconds 885.89 # Real time elapsed on the host
sim_insts 2228284650 # Number of instructions simulated
sim_ops 2229160714 # Number of ops (including micro ops) simulated
system.hypervisor_desc.bytes_read::cpu.data 16792 # Number of bytes read from this memory
system.hypervisor_desc.bytes_read::total 16792 # Number of bytes read from this memory
system.hypervisor_desc.num_reads::cpu.data 9024 # Number of read requests responded to by this memory
system.hypervisor_desc.num_reads::total 9024 # Number of read requests responded to by this memory
system.hypervisor_desc.bw_read::cpu.data 15035 # Total read bandwidth from this memory (bytes/s)
system.hypervisor_desc.bw_read::total 15035 # Total read bandwidth from this memory (bytes/s)
system.hypervisor_desc.bw_total::cpu.data 15035 # Total bandwidth to/from this memory (bytes/s)
system.hypervisor_desc.bw_total::total 15035 # Total bandwidth to/from this memory (bytes/s)
system.hypervisor_desc.bw_read::cpu.data 7517 # Total read bandwidth from this memory (bytes/s)
system.hypervisor_desc.bw_read::total 7517 # Total read bandwidth from this memory (bytes/s)
system.hypervisor_desc.bw_total::cpu.data 7517 # Total bandwidth to/from this memory (bytes/s)
system.hypervisor_desc.bw_total::total 7517 # Total bandwidth to/from this memory (bytes/s)
system.partition_desc.bytes_read::cpu.data 4846 # Number of bytes read from this memory
system.partition_desc.bytes_read::total 4846 # Number of bytes read from this memory
system.partition_desc.num_reads::cpu.data 608 # Number of read requests responded to by this memory
system.partition_desc.num_reads::total 608 # Number of read requests responded to by this memory
system.partition_desc.bw_read::cpu.data 2169 # Total read bandwidth from this memory (bytes/s)
system.partition_desc.bw_read::total 2169 # Total read bandwidth from this memory (bytes/s)
system.partition_desc.bw_total::cpu.data 2169 # Total bandwidth to/from this memory (bytes/s)
system.partition_desc.bw_total::total 2169 # Total bandwidth to/from this memory (bytes/s)
system.rom.bytes_read::cpu.inst 432296 # Number of bytes read from this memory
system.rom.bytes_read::cpu.data 696392 # Number of bytes read from this memory
system.rom.bytes_read::total 1128688 # Number of bytes read from this memory
system.rom.bytes_inst_read::cpu.inst 432296 # Number of instructions bytes read from this memory
system.rom.bytes_inst_read::total 432296 # Number of instructions bytes read from this memory
system.rom.num_reads::cpu.inst 108074 # Number of read requests responded to by this memory
system.rom.num_reads::cpu.data 87049 # Number of read requests responded to by this memory
system.rom.num_reads::total 195123 # Number of read requests responded to by this memory
system.rom.bw_read::cpu.inst 193527 # Total read bandwidth from this memory (bytes/s)
system.rom.bw_read::cpu.data 311755 # Total read bandwidth from this memory (bytes/s)
system.rom.bw_read::total 505282 # Total read bandwidth from this memory (bytes/s)
system.rom.bw_inst_read::cpu.inst 193527 # Instruction read bandwidth from this memory (bytes/s)
system.rom.bw_inst_read::total 193527 # Instruction read bandwidth from this memory (bytes/s)
system.rom.bw_total::cpu.inst 193527 # Total bandwidth to/from this memory (bytes/s)
system.rom.bw_total::cpu.data 311755 # Total bandwidth to/from this memory (bytes/s)
system.rom.bw_total::total 505282 # Total bandwidth to/from this memory (bytes/s)
system.nvram.bytes_read::cpu.data 284 # Number of bytes read from this memory
system.nvram.bytes_read::total 284 # Number of bytes read from this memory
system.nvram.bytes_written::cpu.data 92 # Number of bytes written to this memory
system.nvram.bytes_written::total 92 # Number of bytes written to this memory
system.nvram.num_reads::cpu.data 284 # Number of read requests responded to by this memory
system.nvram.num_reads::total 284 # Number of read requests responded to by this memory
system.nvram.num_writes::cpu.data 92 # Number of write requests responded to by this memory
system.nvram.num_writes::total 92 # Number of write requests responded to by this memory
system.nvram.bw_read::cpu.data 127 # Total read bandwidth from this memory (bytes/s)
system.nvram.bw_read::total 127 # Total read bandwidth from this memory (bytes/s)
system.nvram.bw_write::cpu.data 41 # Write bandwidth from this memory (bytes/s)
system.nvram.bw_write::total 41 # Write bandwidth from this memory (bytes/s)
system.nvram.bw_total::cpu.data 168 # Total bandwidth to/from this memory (bytes/s)
system.nvram.bw_total::total 168 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 612291324 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 97534024 # Number of bytes read from this memory
system.physmem.bytes_read::total 709825348 # Number of bytes read from this memory
@ -33,24 +71,174 @@ system.physmem.num_writes::cpu.data 1927067 # Nu
system.physmem.num_writes::total 1927067 # Number of write requests responded to by this memory
system.physmem.num_other::cpu.data 14 # Number of other requests responded to by this memory
system.physmem.num_other::total 14 # Number of other requests responded to by this memory
system.physmem.bw_read::cpu.inst 548211557 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 87326534 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 635538091 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 548211557 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 548211557 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 13788502 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 13788502 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 548211557 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 101115036 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 649326593 # Total bandwidth to/from this memory (bytes/s)
system.partition_desc.bytes_read::cpu.data 4846 # Number of bytes read from this memory
system.partition_desc.bytes_read::total 4846 # Number of bytes read from this memory
system.partition_desc.num_reads::cpu.data 608 # Number of read requests responded to by this memory
system.partition_desc.num_reads::total 608 # Number of read requests responded to by this memory
system.partition_desc.bw_read::cpu.data 4339 # Total read bandwidth from this memory (bytes/s)
system.partition_desc.bw_read::total 4339 # Total read bandwidth from this memory (bytes/s)
system.partition_desc.bw_total::cpu.data 4339 # Total bandwidth to/from this memory (bytes/s)
system.partition_desc.bw_total::total 4339 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 274105779 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 43663267 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 317769046 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 274105779 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 274105779 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 6894251 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 6894251 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 274105779 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 50557518 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 324663297 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 0 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 0 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 0 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 0 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
system.physmem.writePktSize::2 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
system.physmem.writePktSize::6 0 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 0 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
system.physmem.totBusLat 0 # Total cycles spent in databus access
system.physmem.totBankLat 0 # Total cycles spent in bank access
system.physmem.avgQLat nan # Average queueing delay per request
system.physmem.avgBankLat nan # Average bank access latency per request
system.physmem.avgBusLat nan # Average bus latency per request
system.physmem.avgMemAccLat nan # Average memory access latency
system.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.00 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
system.physmem.readRowHits 0 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate nan # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap nan # Average gap between requests
system.physmem2.bytes_read::cpu.inst 8318106840 # Number of bytes read from this memory
system.physmem2.bytes_read::cpu.data 1495885127 # Number of bytes read from this memory
system.physmem2.bytes_read::total 9813991967 # Number of bytes read from this memory
@ -65,46 +253,174 @@ system.physmem2.num_writes::cpu.data 187387796 # Nu
system.physmem2.num_writes::total 187387796 # Number of write requests responded to by this memory
system.physmem2.num_other::cpu.data 5403067 # Number of other requests responded to by this memory
system.physmem2.num_other::total 5403067 # Number of other requests responded to by this memory
system.physmem2.bw_read::cpu.inst 7447569684 # Total read bandwidth from this memory (bytes/s)
system.physmem2.bw_read::cpu.data 1339332247 # Total read bandwidth from this memory (bytes/s)
system.physmem2.bw_read::total 8786901931 # Total read bandwidth from this memory (bytes/s)
system.physmem2.bw_inst_read::cpu.inst 7447569684 # Instruction read bandwidth from this memory (bytes/s)
system.physmem2.bw_inst_read::total 7447569684 # Instruction read bandwidth from this memory (bytes/s)
system.physmem2.bw_write::cpu.data 803364182 # Write bandwidth from this memory (bytes/s)
system.physmem2.bw_write::total 803364182 # Write bandwidth from this memory (bytes/s)
system.physmem2.bw_total::cpu.inst 7447569684 # Total bandwidth to/from this memory (bytes/s)
system.physmem2.bw_total::cpu.data 2142696429 # Total bandwidth to/from this memory (bytes/s)
system.physmem2.bw_total::total 9590266113 # Total bandwidth to/from this memory (bytes/s)
system.rom.bytes_read::cpu.inst 432296 # Number of bytes read from this memory
system.rom.bytes_read::cpu.data 696392 # Number of bytes read from this memory
system.rom.bytes_read::total 1128688 # Number of bytes read from this memory
system.rom.bytes_inst_read::cpu.inst 432296 # Number of instructions bytes read from this memory
system.rom.bytes_inst_read::total 432296 # Number of instructions bytes read from this memory
system.rom.num_reads::cpu.inst 108074 # Number of read requests responded to by this memory
system.rom.num_reads::cpu.data 87049 # Number of read requests responded to by this memory
system.rom.num_reads::total 195123 # Number of read requests responded to by this memory
system.rom.bw_read::cpu.inst 387054 # Total read bandwidth from this memory (bytes/s)
system.rom.bw_read::cpu.data 623511 # Total read bandwidth from this memory (bytes/s)
system.rom.bw_read::total 1010564 # Total read bandwidth from this memory (bytes/s)
system.rom.bw_inst_read::cpu.inst 387054 # Instruction read bandwidth from this memory (bytes/s)
system.rom.bw_inst_read::total 387054 # Instruction read bandwidth from this memory (bytes/s)
system.rom.bw_total::cpu.inst 387054 # Total bandwidth to/from this memory (bytes/s)
system.rom.bw_total::cpu.data 623511 # Total bandwidth to/from this memory (bytes/s)
system.rom.bw_total::total 1010564 # Total bandwidth to/from this memory (bytes/s)
system.nvram.bytes_read::cpu.data 284 # Number of bytes read from this memory
system.nvram.bytes_read::total 284 # Number of bytes read from this memory
system.nvram.bytes_written::cpu.data 92 # Number of bytes written to this memory
system.nvram.bytes_written::total 92 # Number of bytes written to this memory
system.nvram.num_reads::cpu.data 284 # Number of read requests responded to by this memory
system.nvram.num_reads::total 284 # Number of read requests responded to by this memory
system.nvram.num_writes::cpu.data 92 # Number of write requests responded to by this memory
system.nvram.num_writes::total 92 # Number of write requests responded to by this memory
system.nvram.bw_read::cpu.data 254 # Total read bandwidth from this memory (bytes/s)
system.nvram.bw_read::total 254 # Total read bandwidth from this memory (bytes/s)
system.nvram.bw_write::cpu.data 82 # Write bandwidth from this memory (bytes/s)
system.nvram.bw_write::total 82 # Write bandwidth from this memory (bytes/s)
system.nvram.bw_total::cpu.data 337 # Total bandwidth to/from this memory (bytes/s)
system.nvram.bw_total::total 337 # Total bandwidth to/from this memory (bytes/s)
system.physmem2.bw_read::cpu.inst 3723784842 # Total read bandwidth from this memory (bytes/s)
system.physmem2.bw_read::cpu.data 669666123 # Total read bandwidth from this memory (bytes/s)
system.physmem2.bw_read::total 4393450966 # Total read bandwidth from this memory (bytes/s)
system.physmem2.bw_inst_read::cpu.inst 3723784842 # Instruction read bandwidth from this memory (bytes/s)
system.physmem2.bw_inst_read::total 3723784842 # Instruction read bandwidth from this memory (bytes/s)
system.physmem2.bw_write::cpu.data 401682091 # Write bandwidth from this memory (bytes/s)
system.physmem2.bw_write::total 401682091 # Write bandwidth from this memory (bytes/s)
system.physmem2.bw_total::cpu.inst 3723784842 # Total bandwidth to/from this memory (bytes/s)
system.physmem2.bw_total::cpu.data 1071348214 # Total bandwidth to/from this memory (bytes/s)
system.physmem2.bw_total::total 4795133057 # Total bandwidth to/from this memory (bytes/s)
system.physmem2.readReqs 0 # Total number of read requests seen
system.physmem2.writeReqs 0 # Total number of write requests seen
system.physmem2.cpureqs 0 # Reqs generatd by CPU via cache - shady
system.physmem2.bytesRead 0 # Total number of bytes read from memory
system.physmem2.bytesWritten 0 # Total number of bytes written to memory
system.physmem2.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
system.physmem2.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem2.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem2.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem2.perBankRdReqs::0 0 # Track reads on a per bank basis
system.physmem2.perBankRdReqs::1 0 # Track reads on a per bank basis
system.physmem2.perBankRdReqs::2 0 # Track reads on a per bank basis
system.physmem2.perBankRdReqs::3 0 # Track reads on a per bank basis
system.physmem2.perBankRdReqs::4 0 # Track reads on a per bank basis
system.physmem2.perBankRdReqs::5 0 # Track reads on a per bank basis
system.physmem2.perBankRdReqs::6 0 # Track reads on a per bank basis
system.physmem2.perBankRdReqs::7 0 # Track reads on a per bank basis
system.physmem2.perBankRdReqs::8 0 # Track reads on a per bank basis
system.physmem2.perBankRdReqs::9 0 # Track reads on a per bank basis
system.physmem2.perBankRdReqs::10 0 # Track reads on a per bank basis
system.physmem2.perBankRdReqs::11 0 # Track reads on a per bank basis
system.physmem2.perBankRdReqs::12 0 # Track reads on a per bank basis
system.physmem2.perBankRdReqs::13 0 # Track reads on a per bank basis
system.physmem2.perBankRdReqs::14 0 # Track reads on a per bank basis
system.physmem2.perBankRdReqs::15 0 # Track reads on a per bank basis
system.physmem2.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem2.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem2.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem2.perBankWrReqs::3 0 # Track writes on a per bank basis
system.physmem2.perBankWrReqs::4 0 # Track writes on a per bank basis
system.physmem2.perBankWrReqs::5 0 # Track writes on a per bank basis
system.physmem2.perBankWrReqs::6 0 # Track writes on a per bank basis
system.physmem2.perBankWrReqs::7 0 # Track writes on a per bank basis
system.physmem2.perBankWrReqs::8 0 # Track writes on a per bank basis
system.physmem2.perBankWrReqs::9 0 # Track writes on a per bank basis
system.physmem2.perBankWrReqs::10 0 # Track writes on a per bank basis
system.physmem2.perBankWrReqs::11 0 # Track writes on a per bank basis
system.physmem2.perBankWrReqs::12 0 # Track writes on a per bank basis
system.physmem2.perBankWrReqs::13 0 # Track writes on a per bank basis
system.physmem2.perBankWrReqs::14 0 # Track writes on a per bank basis
system.physmem2.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem2.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem2.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem2.totGap 0 # Total gap between requests
system.physmem2.readPktSize::0 0 # Categorize read packet sizes
system.physmem2.readPktSize::1 0 # Categorize read packet sizes
system.physmem2.readPktSize::2 0 # Categorize read packet sizes
system.physmem2.readPktSize::3 0 # Categorize read packet sizes
system.physmem2.readPktSize::4 0 # Categorize read packet sizes
system.physmem2.readPktSize::5 0 # Categorize read packet sizes
system.physmem2.readPktSize::6 0 # Categorize read packet sizes
system.physmem2.readPktSize::7 0 # Categorize read packet sizes
system.physmem2.readPktSize::8 0 # Categorize read packet sizes
system.physmem2.writePktSize::0 0 # categorize write packet sizes
system.physmem2.writePktSize::1 0 # categorize write packet sizes
system.physmem2.writePktSize::2 0 # categorize write packet sizes
system.physmem2.writePktSize::3 0 # categorize write packet sizes
system.physmem2.writePktSize::4 0 # categorize write packet sizes
system.physmem2.writePktSize::5 0 # categorize write packet sizes
system.physmem2.writePktSize::6 0 # categorize write packet sizes
system.physmem2.writePktSize::7 0 # categorize write packet sizes
system.physmem2.writePktSize::8 0 # categorize write packet sizes
system.physmem2.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem2.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem2.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem2.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem2.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem2.neitherpktsize::5 0 # categorize neither packet sizes
system.physmem2.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem2.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem2.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem2.rdQLenPdf::0 0 # What read queue length does an incoming req see
system.physmem2.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.physmem2.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.physmem2.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem2.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem2.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem2.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem2.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem2.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem2.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem2.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem2.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem2.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem2.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem2.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem2.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem2.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem2.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem2.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem2.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem2.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem2.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem2.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem2.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem2.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem2.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem2.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem2.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem2.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem2.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem2.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem2.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem2.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem2.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem2.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem2.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem2.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem2.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem2.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem2.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem2.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem2.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem2.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem2.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem2.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem2.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem2.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem2.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem2.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem2.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem2.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem2.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem2.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem2.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem2.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem2.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem2.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem2.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem2.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem2.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem2.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem2.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem2.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem2.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem2.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem2.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem2.totQLat 0 # Total cycles spent in queuing delays
system.physmem2.totMemAccLat 0 # Sum of mem lat for all requests
system.physmem2.totBusLat 0 # Total cycles spent in databus access
system.physmem2.totBankLat 0 # Total cycles spent in bank access
system.physmem2.avgQLat nan # Average queueing delay per request
system.physmem2.avgBankLat nan # Average bank access latency per request
system.physmem2.avgBusLat nan # Average bus latency per request
system.physmem2.avgMemAccLat nan # Average memory access latency
system.physmem2.avgRdBW 0.00 # Average achieved read bandwidth in MB/s
system.physmem2.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem2.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
system.physmem2.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem2.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem2.busUtil 0.00 # Data bus utilization in percentage
system.physmem2.avgRdQLen 0.00 # Average read queue length over time
system.physmem2.avgWrQLen 0.00 # Average write queue length over time
system.physmem2.readRowHits 0 # Number of row buffer hits during reads
system.physmem2.writeRowHits 0 # Number of row buffer hits during writes
system.physmem2.readRowHitRate nan # Row buffer hit rate for reads
system.physmem2.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem2.avgGap nan # Average gap between requests
system.cpu.numCycles 2233777513 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed

834
tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
View file

@ -1,90 +1,90 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.271565 # Number of seconds simulated
sim_ticks 271565222500 # Number of ticks simulated
final_tick 271565222500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.269731 # Number of seconds simulated
sim_ticks 269730745500 # Number of ticks simulated
final_tick 269730745500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 118122 # Simulator instruction rate (inst/s)
host_op_rate 118122 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 53298093 # Simulator tick rate (ticks/s)
host_mem_usage 217868 # Number of bytes of host memory used
host_seconds 5095.21 # Real time elapsed on the host
host_inst_rate 168515 # Simulator instruction rate (inst/s)
host_op_rate 168515 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 75522303 # Simulator tick rate (ticks/s)
host_mem_usage 218132 # Number of bytes of host memory used
host_seconds 3571.54 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated
sim_ops 601856964 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1620224 # Number of bytes read from this memory
system.physmem.bytes_read::total 1674048 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1628992 # Number of bytes read from this memory
system.physmem.bytes_read::total 1682816 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 53824 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 53824 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 57024 # Number of bytes written to this memory
system.physmem.bytes_written::total 57024 # Number of bytes written to this memory
system.physmem.bytes_written::writebacks 64896 # Number of bytes written to this memory
system.physmem.bytes_written::total 64896 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 841 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 25316 # Number of read requests responded to by this memory
system.physmem.num_reads::total 26157 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 891 # Number of write requests responded to by this memory
system.physmem.num_writes::total 891 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 198199 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 5966243 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 6164442 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 198199 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 198199 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 209983 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 209983 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 209983 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 198199 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5966243 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6374424 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 26157 # Total number of read requests seen
system.physmem.writeReqs 891 # Total number of write requests seen
system.physmem.cpureqs 27048 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 1674048 # Total number of bytes read from memory
system.physmem.bytesWritten 57024 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 1674048 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 57024 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 5 # Number of read reqs serviced by write Q
system.physmem.num_reads::cpu.data 25453 # Number of read requests responded to by this memory
system.physmem.num_reads::total 26294 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1014 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1014 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 199547 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 6039326 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 6238873 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 199547 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 199547 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 240595 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 240595 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 240595 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 199547 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 6039326 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6479469 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 26294 # Total number of read requests seen
system.physmem.writeReqs 1014 # Total number of write requests seen
system.physmem.cpureqs 27308 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 1682816 # Total number of bytes read from memory
system.physmem.bytesWritten 64896 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 1682816 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 64896 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 14 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 1710 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 1723 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 1560 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 1574 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 1699 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 1625 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 1662 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 1653 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 1553 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 1614 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 1596 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 1543 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 1643 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 1645 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 1686 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 1666 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 58 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 65 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 51 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 46 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 65 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 53 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 67 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 71 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 48 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 52 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 51 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 41 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 49 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 54 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 60 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 60 # Track writes on a per bank basis
system.physmem.perBankRdReqs::0 1718 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 1732 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 1568 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 1581 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 1708 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 1632 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 1673 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 1665 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 1558 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 1618 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 1600 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 1550 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 1652 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 1653 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 1697 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 1675 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 66 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 76 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 52 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 51 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 74 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 60 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 79 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 81 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 53 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 56 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 55 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 48 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 58 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 62 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 74 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 69 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 271565170500 # Total gap between requests
system.physmem.totGap 269730693500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 26157 # Categorize read packet sizes
system.physmem.readPktSize::6 26294 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
system.physmem.writePktSize::6 891 # categorize write packet sizes
system.physmem.writePktSize::6 1014 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
@ -105,16 +105,16 @@ system.physmem.neitherpktsize::5 0 # ca
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 22499 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 383 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 120 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 800 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1522 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 782 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 17 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 10 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 11 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::0 17613 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 6143 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 1651 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 868 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
@ -138,31 +138,31 @@ system.physmem.rdQLenPdf::29 0 # Wh
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 38 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 38 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 38 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 38 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 38 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 38 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 38 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::0 42 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
@ -171,47 +171,47 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 129156577 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 809724577 # Sum of mem lat for all requests
system.physmem.totBusLat 104608000 # Total cycles spent in databus access
system.physmem.totBankLat 575960000 # Total cycles spent in bank access
system.physmem.avgQLat 4938.69 # Average queueing delay per request
system.physmem.avgBankLat 22023.55 # Average bank access latency per request
system.physmem.totQLat 360576187 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 1020404187 # Sum of mem lat for all requests
system.physmem.totBusLat 105120000 # Total cycles spent in databus access
system.physmem.totBankLat 554708000 # Total cycles spent in bank access
system.physmem.avgQLat 13720.56 # Average queueing delay per request
system.physmem.avgBankLat 21107.61 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 30962.24 # Average memory access latency
system.physmem.avgRdBW 6.16 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.21 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 6.16 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.21 # Average consumed write bandwidth in MB/s
system.physmem.avgMemAccLat 38828.17 # Average memory access latency
system.physmem.avgRdBW 6.24 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 6.24 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.24 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.04 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 7.68 # Average write queue length over time
system.physmem.readRowHits 17269 # Number of row buffer hits during reads
system.physmem.writeRowHits 120 # Number of row buffer hits during writes
system.physmem.readRowHitRate 66.03 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 13.47 # Row buffer hit rate for writes
system.physmem.avgGap 10040120.18 # Average gap between requests
system.physmem.avgWrQLen 12.19 # Average write queue length over time
system.physmem.readRowHits 17405 # Number of row buffer hits during reads
system.physmem.writeRowHits 51 # Number of row buffer hits during writes
system.physmem.readRowHitRate 66.23 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 5.03 # Row buffer hit rate for writes
system.physmem.avgGap 9877350.72 # Average gap between requests
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 114517787 # DTB read hits
system.cpu.dtb.read_hits 114517567 # DTB read hits
system.cpu.dtb.read_misses 2631 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 114520418 # DTB read accesses
system.cpu.dtb.write_hits 39661841 # DTB write hits
system.cpu.dtb.read_accesses 114520198 # DTB read accesses
system.cpu.dtb.write_hits 39453373 # DTB write hits
system.cpu.dtb.write_misses 2302 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 39664143 # DTB write accesses
system.cpu.dtb.data_hits 154179628 # DTB hits
system.cpu.dtb.write_accesses 39455675 # DTB write accesses
system.cpu.dtb.data_hits 153970940 # DTB hits
system.cpu.dtb.data_misses 4933 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 154184561 # DTB accesses
system.cpu.itb.fetch_hits 25070821 # ITB hits
system.cpu.dtb.data_accesses 153975873 # DTB accesses
system.cpu.itb.fetch_hits 25065868 # ITB hits
system.cpu.itb.fetch_misses 22 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 25070843 # ITB accesses
system.cpu.itb.fetch_accesses 25065890 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -225,42 +225,42 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 543130446 # number of cpu cycles simulated
system.cpu.numCycles 539461492 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.lookups 86310002 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 81365597 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 36354316 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 52694902 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 34317638 # Number of BTB hits
system.cpu.branch_predictor.lookups 86297721 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 81352852 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 36357676 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 52914836 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 34319624 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 65.125158 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 36895088 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 49414914 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 541552418 # Number of Reads from Int. Register File
system.cpu.branch_predictor.BTBHitPct 64.858226 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 36896934 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 49400787 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 541636673 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 1005407264 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 1005491519 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 161 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 203 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 255071398 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 155051796 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 33757784 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 2591545 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 36349329 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 26198578 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 58.114381 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 412334991 # Number of Instructions Executed.
system.cpu.regfile_manager.regForwards 254989713 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 155053642 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 33759621 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 2593068 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 36352689 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 26195221 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 58.119750 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 412334808 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 538350006 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.threadCycles 535900413 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 387710 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 54025519 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 489104927 # Number of cycles cpu stages are processed.
system.cpu.activity 90.052939 # Percentage of cycles cpu is active
system.cpu.timesIdled 295985 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 50743768 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 488717724 # Number of cycles cpu stages are processed.
system.cpu.activity 90.593626 # Percentage of cycles cpu is active
system.cpu.comLoads 114514042 # Number of Load instructions committed
system.cpu.comStores 39451321 # Number of Store instructions committed
system.cpu.comBranches 62547159 # Number of Branches instructions committed
@ -272,144 +272,144 @@ system.cpu.committedInsts 601856964 # Nu
system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total)
system.cpu.cpi 0.902424 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.cpi 0.896328 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 0.902424 # CPI: Total CPI of All Threads
system.cpu.ipc 1.108126 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.cpi_total 0.896328 # CPI: Total CPI of All Threads
system.cpu.ipc 1.115663 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 1.108126 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 204275308 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 338855138 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 62.389273 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 232303926 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 310826520 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 57.228705 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 201351117 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 341779329 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 62.927669 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 431560271 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 111570175 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 20.542059 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 196153041 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 346977405 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 63.884727 # Percentage of cycles stage was utilized (processing insts).
system.cpu.ipc_total 1.115663 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 200698192 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 338763300 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 62.796568 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 228822575 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 310638917 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 57.583149 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 197865765 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 341595727 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 63.321615 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 428073840 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 111387652 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 20.647934 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 192651610 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 346809882 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 64.288163 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 30 # number of replacements
system.cpu.icache.tagsinuse 729.013382 # Cycle average of tags in use
system.cpu.icache.total_refs 25069798 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 729.083311 # Cycle average of tags in use
system.cpu.icache.total_refs 25064833 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 29321.401170 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 29315.594152 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 729.013382 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.355964 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.355964 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 25069798 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 25069798 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 25069798 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 25069798 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 25069798 # number of overall hits
system.cpu.icache.overall_hits::total 25069798 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1021 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1021 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1021 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1021 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1021 # number of overall misses
system.cpu.icache.overall_misses::total 1021 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 53787000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 53787000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 53787000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 53787000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 53787000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 53787000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 25070819 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 25070819 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 25070819 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 25070819 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 25070819 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 25070819 # number of overall (read+write) accesses
system.cpu.icache.occ_blocks::cpu.inst 729.083311 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.355998 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.355998 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 25064833 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 25064833 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 25064833 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 25064833 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 25064833 # number of overall hits
system.cpu.icache.overall_hits::total 25064833 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1035 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1035 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1035 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1035 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1035 # number of overall misses
system.cpu.icache.overall_misses::total 1035 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 52854000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 52854000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 52854000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 52854000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 52854000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 52854000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 25065868 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 25065868 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 25065868 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 25065868 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 25065868 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 25065868 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52680.705191 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 52680.705191 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 52680.705191 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 52680.705191 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 52680.705191 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 52680.705191 # average overall miss latency
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system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51066.666667 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 51066.666667 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 51066.666667 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 51066.666667 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 51066.666667 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 51066.666667 # average overall miss latency
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system.cpu.icache.ReadReq_mshr_hits::total 166 # number of ReadReq MSHR hits
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system.cpu.icache.demand_mshr_hits::total 166 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 166 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 166 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 180 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 180 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 180 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 180 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 180 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 180 # number of overall MSHR hits
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system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses
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system.cpu.icache.demand_mshr_miss_latency::total 43651000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 43651000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_latency::total 43286500 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::total 43286500 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 43286500 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51053.801170 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51053.801170 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51053.801170 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 51053.801170 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51053.801170 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 51053.801170 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50627.485380 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50627.485380 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50627.485380 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 50627.485380 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50627.485380 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 50627.485380 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 451299 # number of replacements
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system.cpu.dcache.total_refs 151786041 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 334.668912 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 342752000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.WriteReq_hits::total 38286044 # number of WriteReq hits
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system.cpu.dcache.demand_misses::total 1558814 # number of demand (read+write) misses
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system.cpu.dcache.warmup_cycle 334129000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.WriteReq_hits::total 37665413 # number of WriteReq hits
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system.cpu.dcache.overall_misses::total 2179322 # number of overall misses
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system.cpu.dcache.overall_miss_latency::total 28867029500 # number of overall miss cycles
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@ -418,40 +418,40 @@ system.cpu.dcache.demand_accesses::cpu.data 153965363 #
system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14310.673456 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14310.673456 # average ReadReq miss latency
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system.cpu.dcache.demand_avg_miss_latency::total 14206.624716 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14206.624716 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14206.624716 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 44530 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 3993200 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 3165 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 211455 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.069510 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 18.884396 # average number of cycles each access was blocked
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003436 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.003436 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045269 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.045269 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.014155 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.014155 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.014155 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.014155 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15229.731275 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15229.731275 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12808.856895 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 12808.856895 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13245.876240 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 13245.876240 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13245.876240 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 13245.876240 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 165761 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 544 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 5600 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.600179 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 60.444444 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 436902 # number of writebacks
system.cpu.dcache.writebacks::total 436902 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192305 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 192305 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 911114 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 911114 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1103419 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1103419 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1103419 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1103419 # number of overall MSHR hits
system.cpu.dcache.writebacks::writebacks 436887 # number of writebacks
system.cpu.dcache.writebacks::total 436887 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192182 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 192182 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1531745 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1531745 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1723927 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1723927 # number of demand (read+write) MSHR hits
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system.cpu.dcache.overall_mshr_hits::total 1723927 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses
@ -460,14 +460,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395
system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2467175500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2467175500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3742658000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3742658000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6209833500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 6209833500 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::total 6209833500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2645854500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2645854500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency::total 3731128500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6376983000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::total 6376983000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
@ -476,68 +476,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958
system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12260.353721 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12260.353721 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14725.424236 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14725.424236 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13636.147740 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13636.147740 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13636.147740 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13636.147740 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13148.279101 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13148.279101 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14680.061614 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14680.061614 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14003.190637 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 14003.190637 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14003.190637 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 14003.190637 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 917 # number of replacements
system.cpu.l2cache.tagsinuse 22846.870251 # Cycle average of tags in use
system.cpu.l2cache.total_refs 538836 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 23142 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 23.283899 # Average number of references to valid blocks.
system.cpu.l2cache.replacements 1042 # number of replacements
system.cpu.l2cache.tagsinuse 22878.552216 # Cycle average of tags in use
system.cpu.l2cache.total_refs 531848 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 23279 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 22.846686 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 21647.185426 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 719.934202 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 479.750624 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.660620 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.021971 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.014641 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.697231 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::writebacks 21684.756059 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 718.203653 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 475.592503 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.661766 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.021918 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.014514 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.698198 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 197087 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 197101 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 436902 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 436902 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 232992 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 232992 # number of ReadExReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 197082 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 197096 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 436887 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 436887 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 232860 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 232860 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 14 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 430079 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 430093 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 429942 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 429956 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 14 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 430079 # number of overall hits
system.cpu.l2cache.overall_hits::total 430093 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 429942 # number of overall hits
system.cpu.l2cache.overall_hits::total 429956 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 841 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 4120 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 4961 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 21196 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 21196 # number of ReadExReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 4125 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 4966 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 21328 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 21328 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 841 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 25316 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 26157 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 25453 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 26294 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 841 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 25316 # number of overall misses
system.cpu.l2cache.overall_misses::total 26157 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42642500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 287448500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 330091000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1158328500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1158328500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 42642500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 1445777000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 1488419500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 42642500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 1445777000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1488419500 # number of overall miss cycles
system.cpu.l2cache.overall_misses::cpu.data 25453 # number of overall misses
system.cpu.l2cache.overall_misses::total 26294 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42280500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 472681500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 514962000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1146890000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1146890000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 42280500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 1619571500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 1661852000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 42280500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 1619571500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1661852000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 201207 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 202062 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 436902 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 436902 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 436887 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 436887 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 254188 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 254188 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 855 # number of demand (read+write) accesses
@ -547,81 +547,81 @@ system.cpu.l2cache.overall_accesses::cpu.inst 855
system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 456250 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.983626 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020476 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.024552 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083387 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.083387 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020501 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.024577 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083906 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.083906 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983626 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.055591 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.057330 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.055892 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.057631 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983626 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.055591 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.057330 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50704.518430 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69769.053398 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 66537.190083 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54648.447820 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54648.447820 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50704.518430 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 57109.219466 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 56903.295485 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50704.518430 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 57109.219466 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 56903.295485 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 2538 # number of cycles access was blocked
system.cpu.l2cache.overall_miss_rate::cpu.data 0.055892 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.057631 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50274.078478 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 114589.454545 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 103697.543294 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53773.912228 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53773.912228 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50274.078478 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 63629.886457 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 63202.707842 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50274.078478 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 63629.886457 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 63202.707842 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 11 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 230.727273 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 891 # number of writebacks
system.cpu.l2cache.writebacks::total 891 # number of writebacks
system.cpu.l2cache.writebacks::writebacks 1014 # number of writebacks
system.cpu.l2cache.writebacks::total 1014 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 841 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4120 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 4961 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21196 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 21196 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4125 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 4966 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21328 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 21328 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 841 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 25316 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 26157 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 25453 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 26294 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 841 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 25316 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 26157 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32026854 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 234985616 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 267012470 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 891005143 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 891005143 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32026854 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1125990759 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 1158017613 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32026854 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1125990759 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 1158017613 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_misses::cpu.data 25453 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 26294 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31666859 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 419253922 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 450920781 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 877062534 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 877062534 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31666859 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1296316456 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 1327983315 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31666859 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1296316456 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 1327983315 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020476 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024552 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083387 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083387 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020501 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024577 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083906 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083906 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055591 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.057330 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055892 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.057631 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055591 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.057330 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38081.871581 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57035.343689 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53822.308002 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42036.475892 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42036.475892 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38081.871581 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44477.435574 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44271.805368 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38081.871581 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44477.435574 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44271.805368 # average overall mshr miss latency
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055892 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.057631 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37653.815696 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 101637.314424 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 90801.607128 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41122.586928 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41122.586928 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37653.815696 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50929.810081 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50505.184263 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37653.815696 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50929.810081 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50505.184263 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

1337
tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
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376
tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -1,39 +1,39 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.762398 # Number of seconds simulated
sim_ticks 762397656000 # Number of ticks simulated
final_tick 762397656000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.762403 # Number of seconds simulated
sim_ticks 762403375000 # Number of ticks simulated
final_tick 762403375000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1514073 # Simulator instruction rate (inst/s)
host_op_rate 1514073 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1917939864 # Simulator tick rate (ticks/s)
host_mem_usage 219440 # Number of bytes of host memory used
host_seconds 397.51 # Real time elapsed on the host
host_inst_rate 2059312 # Simulator instruction rate (inst/s)
host_op_rate 2059312 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2608636387 # Simulator tick rate (ticks/s)
host_mem_usage 217100 # Number of bytes of host memory used
host_seconds 292.26 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated
sim_ops 601856964 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1620160 # Number of bytes read from this memory
system.physmem.bytes_read::total 1670272 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1628864 # Number of bytes read from this memory
system.physmem.bytes_read::total 1678976 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 50112 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 50112 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 56512 # Number of bytes written to this memory
system.physmem.bytes_written::total 56512 # Number of bytes written to this memory
system.physmem.bytes_written::writebacks 64384 # Number of bytes written to this memory
system.physmem.bytes_written::total 64384 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 783 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 25315 # Number of read requests responded to by this memory
system.physmem.num_reads::total 26098 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 883 # Number of write requests responded to by this memory
system.physmem.num_writes::total 883 # Number of write requests responded to by this memory
system.physmem.num_reads::cpu.data 25451 # Number of read requests responded to by this memory
system.physmem.num_reads::total 26234 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1006 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1006 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 65729 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2125085 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2190815 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2136486 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2202215 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 65729 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 65729 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 74124 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 74124 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 74124 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_write::writebacks 84449 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 84449 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 84449 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 65729 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2125085 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2264939 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2136486 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2286664 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 1524795312 # number of cpu cycles simulated
system.cpu.numCycles 1524806750 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 601856964 # Number of instructions committed
@ -86,18 +86,18 @@ system.cpu.num_mem_refs 153970296 # nu
system.cpu.num_load_insts 114516673 # Number of load instructions
system.cpu.num_store_insts 39453623 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1524795312 # Number of busy cycles
system.cpu.num_busy_cycles 1524806750 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 24 # number of replacements
system.cpu.icache.tagsinuse 673.382950 # Cycle average of tags in use
system.cpu.icache.tagsinuse 673.381157 # Cycle average of tags in use
system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 757057.991195 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 673.382950 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.328800 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.328800 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::cpu.inst 673.381157 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.328799 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.328799 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 601861103 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 601861103 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 601861103 # number of demand (read+write) hits
@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 795 # n
system.cpu.icache.demand_misses::total 795 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 795 # number of overall misses
system.cpu.icache.overall_misses::total 795 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 43221000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 43221000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 43221000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 43221000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 43221000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 43221000 # number of overall miss cycles
system.cpu.icache.ReadReq_miss_latency::cpu.inst 43222000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 43222000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 43222000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 43222000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 43222000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 43222000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 601861898 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 601861898 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 601861898 # number of demand (read+write) accesses
@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001
system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54366.037736 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 54366.037736 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54366.037736 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 54366.037736 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54366.037736 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 54366.037736 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54367.295597 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 54367.295597 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54367.295597 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 54367.295597 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54367.295597 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 54367.295597 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -148,32 +148,32 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 795
system.cpu.icache.demand_mshr_misses::total 795 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 795 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 795 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41631000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 41631000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41631000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 41631000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41631000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 41631000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41632000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 41632000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41632000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 41632000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41632000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 41632000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52366.037736 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52366.037736 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52366.037736 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 52366.037736 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52366.037736 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52366.037736 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52367.295597 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52367.295597 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52367.295597 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 52367.295597 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52367.295597 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52367.295597 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 451299 # number of replacements
system.cpu.dcache.tagsinuse 4094.202421 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4094.203488 # Cycle average of tags in use
system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 563489000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4094.202421 # Average occupied blocks per requestor
system.cpu.dcache.warmup_cycle 563363000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4094.203488 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999561 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999561 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 114312810 # number of ReadReq hits
@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 455395 # n
system.cpu.dcache.demand_misses::total 455395 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 455395 # number of overall misses
system.cpu.dcache.overall_misses::total 455395 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2789140000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 2789140000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4194225000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 4194225000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 6983365000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 6983365000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 6983365000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 6983365000 # number of overall miss cycles
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2789356000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 2789356000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4199727000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 4199727000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 6989083000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 6989083000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 6989083000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 6989083000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002958
system.cpu.dcache.demand_miss_rate::total 0.002958 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002958 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002958 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13860.320426 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13860.320426 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16502.106916 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 16502.106916 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15334.742367 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 15334.742367 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15334.742367 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 15334.742367 # average overall miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13861.393814 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13861.393814 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16523.754441 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 16523.754441 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15347.298499 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 15347.298499 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15347.298499 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 15347.298499 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -232,8 +232,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 436902 # number of writebacks
system.cpu.dcache.writebacks::total 436902 # number of writebacks
system.cpu.dcache.writebacks::writebacks 436887 # number of writebacks
system.cpu.dcache.writebacks::total 436887 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses
@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395
system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2386676000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2386676000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3685899000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3685899000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6072575000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 6072575000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6072575000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 6072575000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2386892000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2386892000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3691401000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3691401000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6078293000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 6078293000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6078293000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 6078293000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
@ -258,68 +258,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958
system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11860.320426 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11860.320426 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14502.106916 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14502.106916 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13334.742367 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13334.742367 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13334.742367 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13334.742367 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11861.393814 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11861.393814 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14523.754441 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14523.754441 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13347.298499 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13347.298499 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13347.298499 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13347.298499 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 903 # number of replacements
system.cpu.l2cache.tagsinuse 22842.908958 # Cycle average of tags in use
system.cpu.l2cache.total_refs 538870 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 23085 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 23.342863 # Average number of references to valid blocks.
system.cpu.l2cache.replacements 1028 # number of replacements
system.cpu.l2cache.tagsinuse 22854.086849 # Cycle average of tags in use
system.cpu.l2cache.total_refs 531883 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 23221 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 22.905258 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 21649.670438 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 668.334752 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 524.903769 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.660696 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.020396 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.016019 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.697110 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::writebacks 21662.155591 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 666.530347 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 525.400911 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.661077 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.020341 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.016034 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.697451 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 12 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 197110 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 197122 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 436902 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 436902 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 232970 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 232970 # number of ReadExReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 197105 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 197117 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 436887 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 436887 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 232839 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 232839 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 12 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 430080 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 430092 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 429944 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 429956 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 12 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 430080 # number of overall hits
system.cpu.l2cache.overall_hits::total 430092 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 429944 # number of overall hits
system.cpu.l2cache.overall_hits::total 429956 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 783 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 4122 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 4905 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 21193 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 21193 # number of ReadExReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 4127 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 4910 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 21324 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 21324 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 783 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 25315 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 26098 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 25451 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 26234 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 783 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 25315 # number of overall misses
system.cpu.l2cache.overall_misses::total 26098 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 40716000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 214344000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 255060000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1102036000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1102036000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 40716000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 1316380000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 1357096000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 40716000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 1316380000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1357096000 # number of overall miss cycles
system.cpu.l2cache.overall_misses::cpu.data 25451 # number of overall misses
system.cpu.l2cache.overall_misses::total 26234 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 40717000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 214610000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 255327000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1108848000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1108848000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 40717000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 1323458000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 1364175000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 40717000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 1323458000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1364175000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 795 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 201232 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 202027 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 436902 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 436902 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 436887 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 436887 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 254163 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 254163 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 795 # number of demand (read+write) accesses
@ -329,27 +329,27 @@ system.cpu.l2cache.overall_accesses::cpu.inst 795
system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 456190 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.984906 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020484 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.024279 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083383 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.083383 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020509 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.024304 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083899 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.083899 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.984906 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.055589 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.057209 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.055888 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.057507 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984906 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.055589 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.057209 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
system.cpu.l2cache.overall_miss_rate::cpu.data 0.055888 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.057507 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52001.277139 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52001.453841 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52001.425662 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52001.277139 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.235747 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000.266829 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52001.277139 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.235747 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000.266829 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -358,52 +358,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 883 # number of writebacks
system.cpu.l2cache.writebacks::total 883 # number of writebacks
system.cpu.l2cache.writebacks::writebacks 1006 # number of writebacks
system.cpu.l2cache.writebacks::total 1006 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 783 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4122 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 4905 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21193 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 21193 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4127 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 4910 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21324 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 21324 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 783 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 25315 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 26098 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 25451 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 26234 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 783 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 25315 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 26098 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31320000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 164880000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 196200000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 847720000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 847720000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31320000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1012600000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 1043920000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31320000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1012600000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 1043920000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_misses::cpu.data 25451 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 26234 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31321000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 165086000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 196407000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 852960000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 852960000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31321000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1018046000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 1049367000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31321000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1018046000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 1049367000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.984906 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020484 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024279 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083383 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083383 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020509 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024304 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083899 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083899 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984906 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055589 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.057209 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055888 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.057507 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984906 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055589 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.057209 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055888 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.057507 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40001.277139 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40001.453841 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40001.425662 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40001.277139 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.235747 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.266829 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40001.277139 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.235747 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.266829 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

1304
tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

406
tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,39 +1,39 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.793710 # Number of seconds simulated
sim_ticks 793709507000 # Number of ticks simulated
final_tick 793709507000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.793670 # Number of seconds simulated
sim_ticks 793670137000 # Number of ticks simulated
final_tick 793670137000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1083083 # Simulator instruction rate (inst/s)
host_op_rate 1143775 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1512037928 # Simulator tick rate (ticks/s)
host_mem_usage 233820 # Number of bytes of host memory used
host_seconds 524.93 # Real time elapsed on the host
host_inst_rate 897110 # Simulator instruction rate (inst/s)
host_op_rate 947381 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1252348386 # Simulator tick rate (ticks/s)
host_mem_usage 231392 # Number of bytes of host memory used
host_seconds 633.75 # Real time elapsed on the host
sim_insts 568539335 # Number of instructions simulated
sim_ops 600398272 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 39104 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1735040 # Number of bytes read from this memory
system.physmem.bytes_read::total 1774144 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 39104 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 39104 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 194752 # Number of bytes written to this memory
system.physmem.bytes_written::total 194752 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 611 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 27110 # Number of read requests responded to by this memory
system.physmem.num_reads::total 27721 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 3043 # Number of write requests responded to by this memory
system.physmem.num_writes::total 3043 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 49267 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2185989 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2235256 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 49267 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 49267 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 245369 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 245369 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 245369 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 49267 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2185989 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2480625 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 38592 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1675072 # Number of bytes read from this memory
system.physmem.bytes_read::total 1713664 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 38592 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 38592 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 159552 # Number of bytes written to this memory
system.physmem.bytes_written::total 159552 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 603 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 26173 # Number of read requests responded to by this memory
system.physmem.num_reads::total 26776 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 2493 # Number of write requests responded to by this memory
system.physmem.num_writes::total 2493 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 48625 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2110539 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2159164 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 48625 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 48625 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 201031 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 201031 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 201031 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 48625 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2110539 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2360195 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -77,7 +77,7 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 1587419014 # number of cpu cycles simulated
system.cpu.numCycles 1587340274 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 568539335 # Number of instructions committed
@ -96,16 +96,16 @@ system.cpu.num_mem_refs 219173606 # nu
system.cpu.num_load_insts 148952593 # Number of load instructions
system.cpu.num_store_insts 70221013 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1587419014 # Number of busy cycles
system.cpu.num_busy_cycles 1587340274 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 12 # number of replacements
system.cpu.icache.tagsinuse 577.773227 # Cycle average of tags in use
system.cpu.icache.tagsinuse 577.773656 # Cycle average of tags in use
system.cpu.icache.total_refs 570073883 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 886584.576983 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 577.773227 # Average occupied blocks per requestor
system.cpu.icache.occ_blocks::cpu.inst 577.773656 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.282116 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.282116 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 570073883 # number of ReadReq hits
@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst 643 # n
system.cpu.icache.demand_misses::total 643 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 643 # number of overall misses
system.cpu.icache.overall_misses::total 643 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 34021000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 34021000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 34021000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 34021000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 34021000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 34021000 # number of overall miss cycles
system.cpu.icache.ReadReq_miss_latency::cpu.inst 33685000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 33685000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 33685000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 33685000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 33685000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 33685000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 570074526 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 570074526 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 570074526 # number of demand (read+write) accesses
@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001
system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52909.797823 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 52909.797823 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 52909.797823 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 52909.797823 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 52909.797823 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 52909.797823 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52387.247278 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 52387.247278 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 52387.247278 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 52387.247278 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 52387.247278 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 52387.247278 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -158,32 +158,32 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 643
system.cpu.icache.demand_mshr_misses::total 643 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 643 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 643 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32735000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 32735000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32735000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 32735000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32735000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 32735000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32399000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 32399000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32399000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 32399000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32399000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 32399000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50909.797823 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50909.797823 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50909.797823 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 50909.797823 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50909.797823 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 50909.797823 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50387.247278 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50387.247278 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50387.247278 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 50387.247278 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50387.247278 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 50387.247278 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 433468 # number of replacements
system.cpu.dcache.tagsinuse 4094.242161 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4094.241219 # Cycle average of tags in use
system.cpu.dcache.total_refs 216774472 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 437564 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 495.412036 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 529482000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4094.242161 # Average occupied blocks per requestor
system.cpu.dcache.warmup_cycle 529622000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4094.241219 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999571 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999571 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 147602035 # number of ReadReq hits
@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data 437564 # n
system.cpu.dcache.demand_misses::total 437564 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 437564 # number of overall misses
system.cpu.dcache.overall_misses::total 437564 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2675478000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 2675478000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4151654000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 4151654000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 6827132000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 6827132000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 6827132000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 6827132000 # number of overall miss cycles
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2650304000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 2650304000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4137794000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 4137794000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 6788098000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 6788098000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 6788098000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 6788098000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 147791851 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 147791851 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses)
@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002014
system.cpu.dcache.demand_miss_rate::total 0.002014 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002014 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002014 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14095.113162 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14095.113162 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16757.568174 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 16757.568174 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15602.590707 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 15602.590707 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15602.590707 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 15602.590707 # average overall miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13962.489990 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13962.489990 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16701.624231 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 16701.624231 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15513.383185 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 15513.383185 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15513.383185 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 15513.383185 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -250,8 +250,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 418219 # number of writebacks
system.cpu.dcache.writebacks::total 418219 # number of writebacks
system.cpu.dcache.writebacks::writebacks 418626 # number of writebacks
system.cpu.dcache.writebacks::total 418626 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 189816 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 189816 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247748 # number of WriteReq MSHR misses
@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 437564
system.cpu.dcache.demand_mshr_misses::total 437564 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 437564 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 437564 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2295846000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2295846000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3656158000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3656158000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5952004000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 5952004000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5952004000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 5952004000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2270672000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2270672000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3642298000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3642298000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5912970000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 5912970000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5912970000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 5912970000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001284 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001284 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003569 # mshr miss rate for WriteReq accesses
@ -276,68 +276,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002014
system.cpu.dcache.demand_mshr_miss_rate::total 0.002014 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002014 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12095.113162 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12095.113162 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14757.568174 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14757.568174 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13602.590707 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13602.590707 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13602.590707 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13602.590707 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11962.489990 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11962.489990 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14701.624231 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14701.624231 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13513.383185 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13513.383185 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13513.383185 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13513.383185 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 3963 # number of replacements
system.cpu.l2cache.tagsinuse 21582.814171 # Cycle average of tags in use
system.cpu.l2cache.total_refs 495400 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 24559 # Sample count of references to valid blocks.
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system.cpu.l2cache.replacements 2512 # number of replacements
system.cpu.l2cache.tagsinuse 22024.775302 # Cycle average of tags in use
system.cpu.l2cache.total_refs 506990 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 23599 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 21.483537 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 20943.692003 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 130.073000 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 509.049168 # Average occupied blocks per requestor
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system.cpu.l2cache.ReadReq_hits::cpu.data 184871 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 184903 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 418219 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 418219 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 225583 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 225583 # number of ReadExReq hits
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system.cpu.l2cache.demand_hits::cpu.data 410454 # number of demand (read+write) hits
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system.cpu.l2cache.overall_hits::cpu.data 410454 # number of overall hits
system.cpu.l2cache.overall_hits::total 410486 # number of overall hits
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system.cpu.l2cache.ReadReq_misses::cpu.data 4945 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 5556 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 22165 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 22165 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 611 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 27110 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 27721 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 611 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 27110 # number of overall misses
system.cpu.l2cache.overall_misses::total 27721 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31772000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 257320000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 289092000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1152580000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1152580000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 31772000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 1409900000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 1441672000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 31772000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 1409900000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1441672000 # number of overall miss cycles
system.cpu.l2cache.occ_blocks::writebacks 20978.651717 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 539.196236 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 506.927350 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.640218 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.016455 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.015470 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.672143 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 40 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 185478 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 185518 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 418626 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 418626 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 225913 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 225913 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 40 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 411391 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 411431 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 40 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 411391 # number of overall hits
system.cpu.l2cache.overall_hits::total 411431 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 603 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 4338 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 4941 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 21835 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 21835 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 603 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 26173 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 26776 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 603 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 26173 # number of overall misses
system.cpu.l2cache.overall_misses::total 26776 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31356000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 226076000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 257432000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1135420000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1135420000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 31356000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 1361496000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 1392852000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 31356000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 1361496000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1392852000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 643 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 189816 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 190459 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 418219 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 418219 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 418626 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 418626 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 247748 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 247748 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 643 # number of demand (read+write) accesses
@ -346,28 +346,28 @@ system.cpu.l2cache.demand_accesses::total 438207 # n
system.cpu.l2cache.overall_accesses::cpu.inst 643 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 437564 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 438207 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.950233 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026052 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.029172 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.089466 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.089466 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.950233 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.061957 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.063260 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.950233 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.061957 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.063260 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.937792 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022854 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.025943 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.088134 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.088134 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.937792 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.059815 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.061104 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.937792 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.059815 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.061104 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52036.400404 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52032.397408 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52115.260489 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52101.194090 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52006.639616 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52006.493272 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52019.103656 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52018.673439 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52006.639616 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52006.493272 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52019.103656 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52018.673439 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -376,52 +376,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 3043 # number of writebacks
system.cpu.l2cache.writebacks::total 3043 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 611 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4945 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 5556 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 22165 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 22165 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 611 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 27110 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 27721 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 611 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 27110 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 27721 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24440000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 197980000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 222420000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 886600000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 886600000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24440000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1084580000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 1109020000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24440000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1084580000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 1109020000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.950233 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026052 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.029172 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089466 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089466 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.950233 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.061957 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.063260 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.950233 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.061957 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.063260 # mshr miss rate for overall accesses
system.cpu.l2cache.writebacks::writebacks 2493 # number of writebacks
system.cpu.l2cache.writebacks::total 2493 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 603 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4338 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 4941 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21835 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 21835 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 603 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 26173 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 26776 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 603 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 26173 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 26776 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24120000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 174020000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 198140000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 873400000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 873400000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24120000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1047420000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 1071540000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24120000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1047420000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 1071540000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.937792 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022854 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.025943 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.088134 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.088134 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.937792 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.059815 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.061104 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.937792 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059815 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.061104 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40036.400404 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40032.397408 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40115.260489 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40101.194090 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40006.639616 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40006.493272 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40019.103656 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40018.673439 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40006.639616 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40006.493272 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40019.103656 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40018.673439 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

1237
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

364
tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt
View file

@ -1,41 +1,41 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.061067 # Number of seconds simulated
sim_ticks 2061066683000 # Number of ticks simulated
final_tick 2061066683000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 2.061066 # Number of seconds simulated
sim_ticks 2061066313000 # Number of ticks simulated
final_tick 2061066313000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1352034 # Simulator instruction rate (inst/s)
host_op_rate 1356054 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1876383782 # Simulator tick rate (ticks/s)
host_mem_usage 222536 # Number of bytes of host memory used
host_seconds 1098.43 # Real time elapsed on the host
host_inst_rate 632829 # Simulator instruction rate (inst/s)
host_op_rate 634711 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 878254717 # Simulator tick rate (ticks/s)
host_mem_usage 225052 # Number of bytes of host memory used
host_seconds 2346.78 # Real time elapsed on the host
sim_insts 1485108088 # Number of instructions simulated
sim_ops 1489523282 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 65728 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1672576 # Number of bytes read from this memory
system.physmem.bytes_read::total 1738304 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 65728 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 65728 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 161472 # Number of bytes written to this memory
system.physmem.bytes_written::total 161472 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1027 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 26134 # Number of read requests responded to by this memory
system.physmem.num_reads::total 27161 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 2523 # Number of write requests responded to by this memory
system.physmem.num_writes::total 2523 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 31890 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 811510 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 843400 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 31890 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 31890 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 78344 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 78344 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 78344 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 31890 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 811510 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 921744 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1672512 # Number of bytes read from this memory
system.physmem.bytes_read::total 1737728 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 65216 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 65216 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 161152 # Number of bytes written to this memory
system.physmem.bytes_written::total 161152 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1019 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 26133 # Number of read requests responded to by this memory
system.physmem.num_reads::total 27152 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 2518 # Number of write requests responded to by this memory
system.physmem.num_writes::total 2518 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 31642 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 811479 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 843121 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 31642 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 31642 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 78189 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 78189 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 78189 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 31642 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 811479 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 921310 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 49 # Number of system calls
system.cpu.numCycles 4122133366 # number of cpu cycles simulated
system.cpu.numCycles 4122132626 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1485108088 # Number of instructions committed
@ -54,16 +54,16 @@ system.cpu.num_mem_refs 569365766 # nu
system.cpu.num_load_insts 402515345 # Number of load instructions
system.cpu.num_store_insts 166850421 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 4122133366 # Number of busy cycles
system.cpu.num_busy_cycles 4122132626 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 118 # number of replacements
system.cpu.icache.tagsinuse 906.468708 # Cycle average of tags in use
system.cpu.icache.tagsinuse 906.468716 # Cycle average of tags in use
system.cpu.icache.total_refs 1485111892 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1341564.491418 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 906.468708 # Average occupied blocks per requestor
system.cpu.icache.occ_blocks::cpu.inst 906.468716 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.442612 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.442612 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1485111892 # number of ReadReq hits
@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 1107 # n
system.cpu.icache.demand_misses::total 1107 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1107 # number of overall misses
system.cpu.icache.overall_misses::total 1107 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 57527000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 57527000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 57527000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 57527000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 57527000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 57527000 # number of overall miss cycles
system.cpu.icache.ReadReq_miss_latency::cpu.inst 57199000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 57199000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 57199000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 57199000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 57199000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 57199000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1485112999 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1485112999 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1485112999 # number of demand (read+write) accesses
@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001
system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51966.576332 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 51966.576332 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 51966.576332 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 51966.576332 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 51966.576332 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 51966.576332 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51670.280036 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 51670.280036 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 51670.280036 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 51670.280036 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 51670.280036 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 51670.280036 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -116,32 +116,32 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1107
system.cpu.icache.demand_mshr_misses::total 1107 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1107 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1107 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 55313000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 55313000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 55313000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 55313000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 55313000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 55313000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54985000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 54985000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54985000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 54985000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54985000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 54985000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49966.576332 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49966.576332 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49966.576332 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 49966.576332 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49966.576332 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 49966.576332 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49670.280036 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49670.280036 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49670.280036 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 49670.280036 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49670.280036 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 49670.280036 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 449125 # number of replacements
system.cpu.dcache.tagsinuse 4095.236029 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4095.236014 # Cycle average of tags in use
system.cpu.dcache.total_refs 568907764 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 1255.254642 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 559332000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4095.236029 # Average occupied blocks per requestor
system.cpu.dcache.warmup_cycle 559340000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4095.236014 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999813 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999813 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 402319357 # number of ReadReq hits
@ -166,14 +166,14 @@ system.cpu.dcache.overall_misses::cpu.data 453214 #
system.cpu.dcache.overall_misses::total 453214 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2694826000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 2694826000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4294542000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 4294542000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4294500000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 4294500000 # number of WriteReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::cpu.data 133000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::total 133000 # number of SwapReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 6989368000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 6989368000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 6989368000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 6989368000 # number of overall miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 6989326000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 6989326000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 6989326000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 6989326000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 402512843 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 402512843 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses)
@ -196,14 +196,14 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.000796
system.cpu.dcache.overall_miss_rate::total 0.000796 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13927.757047 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13927.757047 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16534.767141 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 16534.767141 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16534.605433 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 16534.605433 # average WriteReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 19000 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::total 19000 # average SwapReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15421.783087 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 15421.783087 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15421.783087 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 15421.783087 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15421.690416 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 15421.690416 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15421.690416 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 15421.690416 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -226,14 +226,14 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 453214
system.cpu.dcache.overall_mshr_misses::total 453214 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2307854000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2307854000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3775086000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3775086000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3775044000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3775044000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 119000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::total 119000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6082940000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 6082940000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6082940000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 6082940000 # number of overall MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6082898000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 6082898000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::total 6082898000 # number of overall MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001557 # mshr miss rate for WriteReq accesses
@ -246,63 +246,63 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000796
system.cpu.dcache.overall_mshr_miss_rate::total 0.000796 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11927.757047 # average ReadReq mshr miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14534.767141 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14534.605433 # average WriteReq mshr miss latency
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system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 17000 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 17000 # average SwapReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13421.783087 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13421.783087 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13421.783087 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13421.783087 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13421.690416 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13421.690416 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13421.690416 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2614 # number of replacements
system.cpu.l2cache.tagsinuse 22187.209427 # Cycle average of tags in use
system.cpu.l2cache.total_refs 527657 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 23998 # Sample count of references to valid blocks.
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system.cpu.l2cache.replacements 2539 # number of replacements
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system.cpu.l2cache.total_refs 534785 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 23989 # Sample count of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 20830.496331 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.inst 913.017348 # Average occupied blocks per requestor
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system.cpu.l2cache.Writeback_hits::total 435341 # number of Writeback hits
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system.cpu.l2cache.ReadExReq_miss_latency::total 1136720000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 53406000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 1358968000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 1412374000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 53406000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 1358968000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1412374000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 275246000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1136668000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1136668000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 52998000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 1358916000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 1411914000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 52998000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 1358916000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1411914000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1107 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 193486 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 194593 # number of ReadReq accesses(hits+misses)
@ -316,28 +316,28 @@ system.cpu.l2cache.demand_accesses::total 454328 # n
system.cpu.l2cache.overall_accesses::cpu.inst 1107 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 453221 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 454328 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.927733 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.920506 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022089 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.027241 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.084163 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.084163 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.927733 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.057663 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.059783 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.927733 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.057663 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.059783 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52001.947420 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_miss_rate::total 0.027200 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.084159 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.084159 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.920506 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.057661 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.059763 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.920506 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.057661 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.059763 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52009.813543 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.377287 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52001.889288 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52001.947420 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52009.813543 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000.073635 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52001.947420 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000.368297 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52009.813543 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000.073635 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000.368297 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -346,52 +346,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 2523 # number of writebacks
system.cpu.l2cache.writebacks::total 2523 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1027 # number of ReadReq MSHR misses
system.cpu.l2cache.writebacks::writebacks 2518 # number of writebacks
system.cpu.l2cache.writebacks::total 2518 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1019 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4274 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 5301 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21860 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 21860 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1027 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 26134 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 27161 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1027 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 26134 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 27161 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 41082000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_misses::total 5293 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21859 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 21859 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1019 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 26133 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 27152 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1019 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 26133 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 27152 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40770000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 170960000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 212042000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 874400000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 874400000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41082000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1045360000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 1086442000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41082000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1045360000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 1086442000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.927733 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 211730000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 874360000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 874360000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40770000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1045320000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 1086090000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40770000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1045320000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 1086090000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.920506 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022089 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027241 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.084163 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.084163 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.927733 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.057663 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.059783 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.927733 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.057663 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.059783 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40001.947420 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027200 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.084159 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.084159 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.920506 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.057661 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.059763 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.920506 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.057661 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.059763 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40009.813543 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.377287 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40001.889288 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40001.947420 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40009.813543 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.073635 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40001.947420 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.368297 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40009.813543 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.073635 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.368297 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

1196
tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
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File diff suppressed because it is too large Load diff

248
tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.800193 # Number of seconds simulated
sim_ticks 1800193072000 # Number of ticks simulated
final_tick 1800193072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 1800193396000 # Number of ticks simulated
final_tick 1800193396000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 480678 # Simulator instruction rate (inst/s)
host_op_rate 885676 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 983283018 # Simulator tick rate (ticks/s)
host_mem_usage 228792 # Number of bytes of host memory used
host_seconds 1830.80 # Real time elapsed on the host
host_inst_rate 332254 # Simulator instruction rate (inst/s)
host_op_rate 612196 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 679663607 # Simulator tick rate (ticks/s)
host_mem_usage 227800 # Number of bytes of host memory used
host_seconds 2648.65 # Real time elapsed on the host
sim_insts 880025278 # Number of instructions simulated
sim_ops 1621493926 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory
@ -16,26 +16,26 @@ system.physmem.bytes_read::cpu.data 1682368 # Nu
system.physmem.bytes_read::total 1728576 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 46208 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 46208 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 160640 # Number of bytes written to this memory
system.physmem.bytes_written::total 160640 # Number of bytes written to this memory
system.physmem.bytes_written::writebacks 160704 # Number of bytes written to this memory
system.physmem.bytes_written::total 160704 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 722 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 26287 # Number of read requests responded to by this memory
system.physmem.num_reads::total 27009 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 2510 # Number of write requests responded to by this memory
system.physmem.num_writes::total 2510 # Number of write requests responded to by this memory
system.physmem.num_writes::writebacks 2511 # Number of write requests responded to by this memory
system.physmem.num_writes::total 2511 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 25668 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 934549 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 934548 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 960217 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 25668 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 25668 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 89235 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 89235 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 89235 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_write::writebacks 89270 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 89270 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 89270 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 25668 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 934549 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1049452 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 934548 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1049487 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 3600386144 # number of cpu cycles simulated
system.cpu.numCycles 3600386792 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 880025278 # Number of instructions committed
@ -54,16 +54,16 @@ system.cpu.num_mem_refs 607228178 # nu
system.cpu.num_load_insts 419042121 # Number of load instructions
system.cpu.num_store_insts 188186057 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 3600386144 # Number of busy cycles
system.cpu.num_busy_cycles 3600386792 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 4 # number of replacements
system.cpu.icache.tagsinuse 660.197374 # Cycle average of tags in use
system.cpu.icache.tagsinuse 660.197306 # Cycle average of tags in use
system.cpu.icache.total_refs 1186515974 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1643373.925208 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 660.197374 # Average occupied blocks per requestor
system.cpu.icache.occ_blocks::cpu.inst 660.197306 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.322362 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.322362 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1186515974 # number of ReadReq hits
@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 722 # n
system.cpu.icache.demand_misses::total 722 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 722 # number of overall misses
system.cpu.icache.overall_misses::total 722 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 39710000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 39710000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 39710000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 39710000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 39710000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 39710000 # number of overall miss cycles
system.cpu.icache.ReadReq_miss_latency::cpu.inst 39712000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 39712000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 39712000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 39712000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 39712000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 39712000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1186516696 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1186516696 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1186516696 # number of demand (read+write) accesses
@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001
system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55000 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55000 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 55000 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55000 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 55000 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55002.770083 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 55002.770083 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55002.770083 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 55002.770083 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55002.770083 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 55002.770083 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -116,32 +116,32 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 722
system.cpu.icache.demand_mshr_misses::total 722 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 722 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 722 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38266000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 38266000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38266000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 38266000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38266000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 38266000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38268000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 38268000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38268000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 38268000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38268000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 38268000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53002.770083 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53002.770083 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53002.770083 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 53002.770083 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53002.770083 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53002.770083 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 437952 # number of replacements
system.cpu.dcache.tagsinuse 4094.905905 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4094.905744 # Cycle average of tags in use
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system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks.
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system.cpu.dcache.warmup_cycle 771462000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.warmup_cycle 771786000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4094.905744 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999733 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999733 # Average percentage of cache occupancy
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@ -162,12 +162,12 @@ system.cpu.dcache.overall_misses::cpu.data 442048 #
system.cpu.dcache.overall_misses::total 442048 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency::total 2746552000 # number of ReadReq miss cycles
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system.cpu.dcache.overall_miss_latency::cpu.data 6851259000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 6851259000 # number of overall miss cycles
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system.cpu.dcache.WriteReq_miss_latency::total 4105029000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 6851581000 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency::cpu.data 6851581000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 6851581000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 419042121 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 419042121 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses)
@ -186,12 +186,12 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.000728
system.cpu.dcache.overall_miss_rate::total 0.000728 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13918.855093 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13918.855093 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16772.938273 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 16772.938273 # average WriteReq miss latency
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system.cpu.dcache.demand_avg_miss_latency::total 15498.902834 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15498.902834 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 15498.902834 # average overall miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16774.254052 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 16774.254052 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15499.631262 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 15499.631262 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15499.631262 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 15499.631262 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -212,12 +212,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 442048
system.cpu.dcache.overall_mshr_misses::total 442048 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2351900000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5967163000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 5967163000 # number of overall MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3615585000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::total 5967485000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000471 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000471 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001300 # mshr miss rate for WriteReq accesses
@ -228,26 +228,26 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000728
system.cpu.dcache.overall_mshr_miss_rate::total 0.000728 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11918.855093 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11918.855093 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14772.938273 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14772.938273 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13498.902834 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13498.902834 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13498.902834 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13498.902834 # average overall mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14774.254052 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14774.254052 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13499.631262 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13499.631262 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13499.631262 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13499.631262 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2581 # number of replacements
system.cpu.l2cache.tagsinuse 22163.399604 # Cycle average of tags in use
system.cpu.l2cache.total_refs 506758 # Total number of references to valid blocks.
system.cpu.l2cache.replacements 2532 # number of replacements
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system.cpu.l2cache.total_refs 519268 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 23832 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 21.263763 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 21.788687 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 21020.012941 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 596.858262 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 546.528401 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_percent::cpu.inst 0.018215 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::writebacks 21021.301366 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 643.199216 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 546.528757 # Average occupied blocks per requestor
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system.cpu.l2cache.Writeback_hits::writebacks 422980 # number of Writeback hits
@ -269,17 +269,17 @@ system.cpu.l2cache.demand_misses::total 27009 # nu
system.cpu.l2cache.overall_misses::cpu.inst 722 # number of overall misses
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system.cpu.l2cache.demand_miss_latency::cpu.inst 37546000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.inst 37546000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 1367827000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1405373000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 722 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_accesses::total 198048 # number of ReadReq accesses(hits+misses)
@ -304,17 +304,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.061000 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.059466 # miss rate for overall accesses
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system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52002.770083 # average ReadReq miss latency
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@ -323,8 +323,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.writebacks::writebacks 2510 # number of writebacks
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@ -336,17 +336,17 @@ system.cpu.l2cache.demand_mshr_misses::total 27009
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@ -358,17 +358,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.061000
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40026.445152 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40022.102180 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40021.511348 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40022.102180 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40021.511348 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.396904 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40041.101502 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40041.101502 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40002.770083 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40034.351581 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40033.507349 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40002.770083 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40034.351581 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40033.507349 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

1212
tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
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File diff suppressed because it is too large Load diff

14
tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.147136 # Nu
sim_ticks 147135976000 # Number of ticks simulated
final_tick 147135976000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1039833 # Simulator instruction rate (inst/s)
host_op_rate 1047288 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1689137215 # Simulator tick rate (ticks/s)
host_mem_usage 366884 # Number of bytes of host memory used
host_seconds 87.11 # Real time elapsed on the host
host_inst_rate 1200528 # Simulator instruction rate (inst/s)
host_op_rate 1209136 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1950176496 # Simulator tick rate (ticks/s)
host_mem_usage 364464 # Number of bytes of host memory used
host_seconds 75.45 # Real time elapsed on the host
sim_insts 90576861 # Number of instructions simulated
sim_ops 91226312 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory
@ -280,9 +280,9 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::total 11654.842955
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 9565.271881 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1827210 # Total number of references to valid blocks.
system.cpu.l2cache.total_refs 1827177 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 15323 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 119.246231 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 119.244078 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 8876.925013 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 495.124137 # Average occupied blocks per requestor

14
tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.361489 # Nu
sim_ticks 361488530000 # Number of ticks simulated
final_tick 361488530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1171246 # Simulator instruction rate (inst/s)
host_op_rate 1171295 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1736457304 # Simulator tick rate (ticks/s)
host_mem_usage 354676 # Number of bytes of host memory used
host_seconds 208.18 # Real time elapsed on the host
host_inst_rate 1414417 # Simulator instruction rate (inst/s)
host_op_rate 1414475 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2096975339 # Simulator tick rate (ticks/s)
host_mem_usage 357072 # Number of bytes of host memory used
host_seconds 172.39 # Real time elapsed on the host
sim_insts 243825150 # Number of instructions simulated
sim_ops 243835265 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory
@ -250,9 +250,9 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 9730.625290 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1813121 # Total number of references to valid blocks.
system.cpu.l2cache.total_refs 1813290 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 15586 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 116.330104 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 116.340947 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 8847.670241 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 738.635592 # Average occupied blocks per requestor

1309
tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
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File diff suppressed because it is too large Load diff

393
tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,41 +1,41 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.365994 # Number of seconds simulated
sim_ticks 365994481000 # Number of ticks simulated
final_tick 365994481000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.365989 # Number of seconds simulated
sim_ticks 365989063000 # Number of ticks simulated
final_tick 365989063000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 452383 # Simulator instruction rate (inst/s)
host_op_rate 796575 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1047986231 # Simulator tick rate (ticks/s)
host_mem_usage 363904 # Number of bytes of host memory used
host_seconds 349.24 # Real time elapsed on the host
host_inst_rate 621192 # Simulator instruction rate (inst/s)
host_op_rate 1093819 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1439024491 # Simulator tick rate (ticks/s)
host_mem_usage 361884 # Number of bytes of host memory used
host_seconds 254.33 # Real time elapsed on the host
sim_insts 157988548 # Number of instructions simulated
sim_ops 278192463 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 51712 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1879680 # Number of bytes read from this memory
system.physmem.bytes_read::total 1931392 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 51712 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 51712 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 14528 # Number of bytes written to this memory
system.physmem.bytes_written::total 14528 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 808 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 29370 # Number of read requests responded to by this memory
system.physmem.num_reads::total 30178 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 227 # Number of write requests responded to by this memory
system.physmem.num_writes::total 227 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 141292 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 5135815 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 5277107 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 141292 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 141292 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 39695 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 39695 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 39695 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 141292 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5135815 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 5316801 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1871744 # Number of bytes read from this memory
system.physmem.bytes_read::total 1923136 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 51392 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 51392 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 6400 # Number of bytes written to this memory
system.physmem.bytes_written::total 6400 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 803 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 29246 # Number of read requests responded to by this memory
system.physmem.num_reads::total 30049 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 100 # Number of write requests responded to by this memory
system.physmem.num_writes::total 100 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 140419 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 5114207 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 5254627 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 140419 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 140419 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 17487 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 17487 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 17487 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 140419 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5114207 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 5272114 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 444 # Number of system calls
system.cpu.numCycles 731988962 # number of cpu cycles simulated
system.cpu.numCycles 731978126 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 157988548 # Number of instructions committed
@ -54,16 +54,16 @@ system.cpu.num_mem_refs 122219135 # nu
system.cpu.num_load_insts 90779384 # Number of load instructions
system.cpu.num_store_insts 31439751 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 731988962 # Number of busy cycles
system.cpu.num_busy_cycles 731978126 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 24 # number of replacements
system.cpu.icache.tagsinuse 665.633473 # Cycle average of tags in use
system.cpu.icache.tagsinuse 665.632511 # Cycle average of tags in use
system.cpu.icache.total_refs 217695357 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 269424.946782 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 665.633473 # Average occupied blocks per requestor
system.cpu.icache.occ_blocks::cpu.inst 665.632511 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.325016 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 217695357 # number of ReadReq hits
@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 808 # n
system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses
system.cpu.icache.overall_misses::total 808 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 44440000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 44440000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 44440000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 44440000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 44440000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 44440000 # number of overall miss cycles
system.cpu.icache.ReadReq_miss_latency::cpu.inst 44230000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 44230000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 44230000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 44230000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 44230000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 44230000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 217696165 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 217696165 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 217696165 # number of demand (read+write) accesses
@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000004
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55000 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55000 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 55000 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55000 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 55000 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54740.099010 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 54740.099010 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54740.099010 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 54740.099010 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54740.099010 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 54740.099010 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 808
system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42824000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 42824000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42824000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 42824000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42824000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 42824000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42614000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 42614000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42614000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 42614000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42614000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 42614000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52740.099010 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52740.099010 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2062733 # number of replacements
system.cpu.dcache.tagsinuse 4076.488929 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4076.488641 # Cycle average of tags in use
system.cpu.dcache.total_refs 120152368 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 58.133676 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 126079699000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4076.488929 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.995237 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.995237 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::cpu.data 4076.488641 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.995236 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 88818726 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 88818726 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 31333642 # number of WriteReq hits
@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 2066829 # n
system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses
system.cpu.dcache.overall_misses::total 2066829 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 25503766000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 25503766000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598582000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 2598582000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 28102348000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 28102348000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 28102348000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 28102348000 # number of overall miss cycles
system.cpu.dcache.ReadReq_miss_latency::cpu.data 25498684000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 25498684000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598456000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 2598456000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 28097140000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 28097140000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 28097140000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 28097140000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 90779446 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 90779446 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses)
@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.016911
system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.347301 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.347301 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24489.741681 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 24489.741681 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13596.842313 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 13596.842313 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13596.842313 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 13596.842313 # average overall miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13004.755396 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13004.755396 # average ReadReq miss latency
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system.cpu.dcache.overall_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency
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@ -200,8 +200,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2066829
system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses
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@ -226,65 +226,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911
system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11596.842313 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency
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system.cpu.l2cache.tagsinuse 19679.255550 # Cycle average of tags in use
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system.cpu.l2cache.sampled_refs 30157 # Sample count of references to valid blocks.
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@ -323,41 +326,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
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system.cpu.l2cache.demand_mshr_misses::cpu.data 29246 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 30049 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 29246 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 30049 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32120000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8880000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41000000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1160960000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1160960000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32120000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1169840000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 1201960000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32120000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1169840000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 1201960000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000113 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000523 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273530 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273530 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.014533 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.014533 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency

1375
tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

434
tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,39 +1,39 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.717833 # Number of seconds simulated
sim_ticks 717832876000 # Number of ticks simulated
final_tick 717832876000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.717366 # Number of seconds simulated
sim_ticks 717366012000 # Number of ticks simulated
final_tick 717366012000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1074460 # Simulator instruction rate (inst/s)
host_op_rate 1210735 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1527332222 # Simulator tick rate (ticks/s)
host_mem_usage 237040 # Number of bytes of host memory used
host_seconds 469.99 # Real time elapsed on the host
host_inst_rate 512177 # Simulator instruction rate (inst/s)
host_op_rate 577137 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 727580493 # Simulator tick rate (ticks/s)
host_mem_usage 234620 # Number of bytes of host memory used
host_seconds 985.96 # Real time elapsed on the host
sim_insts 504986853 # Number of instructions simulated
sim_ops 569034839 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 178368 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9663872 # Number of bytes read from this memory
system.physmem.bytes_read::total 9842240 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 178368 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 178368 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 6574720 # Number of bytes written to this memory
system.physmem.bytes_written::total 6574720 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 2787 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 150998 # Number of read requests responded to by this memory
system.physmem.num_reads::total 153785 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 102730 # Number of write requests responded to by this memory
system.physmem.num_writes::total 102730 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 248481 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 13462565 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 13711047 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 248481 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 248481 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 9159124 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 9159124 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 9159124 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 248481 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 13462565 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 22870170 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 177280 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8952256 # Number of bytes read from this memory
system.physmem.bytes_read::total 9129536 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 177280 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 177280 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 6140992 # Number of bytes written to this memory
system.physmem.bytes_written::total 6140992 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 2770 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 139879 # Number of read requests responded to by this memory
system.physmem.num_reads::total 142649 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 95953 # Number of write requests responded to by this memory
system.physmem.num_writes::total 95953 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 247126 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 12479342 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 12726469 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 247126 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 247126 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 8560472 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 8560472 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 8560472 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 247126 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 12479342 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 21286941 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -77,7 +77,7 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
system.cpu.numCycles 1435665752 # number of cpu cycles simulated
system.cpu.numCycles 1434732024 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 504986853 # Number of instructions committed
@ -96,18 +96,18 @@ system.cpu.num_mem_refs 182890034 # nu
system.cpu.num_load_insts 126029555 # Number of load instructions
system.cpu.num_store_insts 56860479 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1435665752 # Number of busy cycles
system.cpu.num_busy_cycles 1434732024 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 9788 # number of replacements
system.cpu.icache.tagsinuse 982.776891 # Cycle average of tags in use
system.cpu.icache.tagsinuse 982.663229 # Cycle average of tags in use
system.cpu.icache.total_refs 516599855 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 44839.845066 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 982.776891 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.479872 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.479872 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::cpu.inst 982.663229 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.479816 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.479816 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 516599855 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 516599855 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 516599855 # number of demand (read+write) hits
@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst 11521 # n
system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses
system.cpu.icache.overall_misses::total 11521 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 266834000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 266834000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 266834000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 266834000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 266834000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 266834000 # number of overall miss cycles
system.cpu.icache.ReadReq_miss_latency::cpu.inst 266195000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 266195000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 266195000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 266195000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 266195000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 266195000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 516611376 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 516611376 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 516611376 # number of demand (read+write) accesses
@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000022
system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23160.663137 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 23160.663137 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 23160.663137 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 23160.663137 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 23160.663137 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 23160.663137 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23105.199201 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 23105.199201 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 23105.199201 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 23105.199201 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 23105.199201 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 23105.199201 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 11521
system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243792000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 243792000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243792000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 243792000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243792000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 243792000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243153000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 243153000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243153000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 243153000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243153000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 243153000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21160.663137 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21160.663137 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21160.663137 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 21160.663137 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21160.663137 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 21160.663137 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21105.199201 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21105.199201 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21105.199201 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 21105.199201 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21105.199201 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 21105.199201 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1134822 # number of replacements
system.cpu.dcache.tagsinuse 4065.317414 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4065.297446 # Cycle average of tags in use
system.cpu.dcache.total_refs 179817786 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1138918 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 157.884752 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 11885124000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4065.317414 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.992509 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::cpu.data 4065.297446 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.992504 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.992504 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 122957658 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 122957658 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits
@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data 1138918 # n
system.cpu.dcache.demand_misses::total 1138918 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses
system.cpu.dcache.overall_misses::total 1138918 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 12178377000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 12178377000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8970025000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 8970025000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 21148402000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 21148402000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 21148402000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 21148402000 # number of overall miss cycles
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11817433000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 11817433000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8864744000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 8864744000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 20682177000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 20682177000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 20682177000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 20682177000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 123740316 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 123740316 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.006399
system.cpu.dcache.demand_miss_rate::total 0.006399 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.006399 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.006399 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15560.279202 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15560.279202 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25178.310784 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 25178.310784 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 18568.853947 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 18568.853947 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 18568.853947 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 18568.853947 # average overall miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15099.102034 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15099.102034 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24882.793465 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 24882.793465 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 18159.496118 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 18159.496118 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 18159.496118 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 18159.496118 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -250,8 +250,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 1061444 # number of writebacks
system.cpu.dcache.writebacks::total 1061444 # number of writebacks
system.cpu.dcache.writebacks::writebacks 1064905 # number of writebacks
system.cpu.dcache.writebacks::total 1064905 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782658 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 782658 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses
@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1138918
system.cpu.dcache.demand_mshr_misses::total 1138918 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses
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@ -376,52 +376,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
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system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100794 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 100794 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2770 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 139879 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 142649 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2770 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 139879 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 142649 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 110882000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1564709000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1675591000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4031776000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4031776000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 110882000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5596485000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 5707367000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110882000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5596485000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 5707367000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.049939 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.052702 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282923 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282923 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122817 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.123995 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122817 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.123995 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40029.602888 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40033.491109 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40033.233783 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.158740 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.158740 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40029.602888 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40009.472473 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40009.863371 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40029.602888 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40009.472473 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40009.863371 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

1346
tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

434
tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,41 +1,41 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.649901 # Number of seconds simulated
sim_ticks 1649900881000 # Number of ticks simulated
final_tick 1649900881000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 1.647873 # Number of seconds simulated
sim_ticks 1647872847000 # Number of ticks simulated
final_tick 1647872847000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 669860 # Simulator instruction rate (inst/s)
host_op_rate 1238647 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1336598464 # Simulator tick rate (ticks/s)
host_mem_usage 232964 # Number of bytes of host memory used
host_seconds 1234.40 # Real time elapsed on the host
host_inst_rate 897428 # Simulator instruction rate (inst/s)
host_op_rate 1659445 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1788472844 # Simulator tick rate (ticks/s)
host_mem_usage 230968 # Number of bytes of host memory used
host_seconds 921.39 # Real time elapsed on the host
sim_insts 826877110 # Number of instructions simulated
sim_ops 1528988700 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 123584 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 27359872 # Number of bytes read from this memory
system.physmem.bytes_read::total 27483456 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 123584 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 123584 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 20708480 # Number of bytes written to this memory
system.physmem.bytes_written::total 20708480 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1931 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 427498 # Number of read requests responded to by this memory
system.physmem.num_reads::total 429429 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 323570 # Number of write requests responded to by this memory
system.physmem.num_writes::total 323570 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 74904 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 16582737 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 16657641 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 74904 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 74904 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 12551348 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 12551348 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 12551348 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 74904 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 16582737 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 29208989 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 120704 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 24272448 # Number of bytes read from this memory
system.physmem.bytes_read::total 24393152 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 120704 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 120704 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 18706304 # Number of bytes written to this memory
system.physmem.bytes_written::total 18706304 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1886 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 379257 # Number of read requests responded to by this memory
system.physmem.num_reads::total 381143 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 292286 # Number of write requests responded to by this memory
system.physmem.num_writes::total 292286 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 73248 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 14729564 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 14802812 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 73248 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 73248 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 11351788 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 11351788 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 11351788 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 73248 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 14729564 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 26154601 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 551 # Number of system calls
system.cpu.numCycles 3299801762 # number of cpu cycles simulated
system.cpu.numCycles 3295745694 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 826877110 # Number of instructions committed
@ -54,18 +54,18 @@ system.cpu.num_mem_refs 533262341 # nu
system.cpu.num_load_insts 384102156 # Number of load instructions
system.cpu.num_store_insts 149160185 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 3299801762 # Number of busy cycles
system.cpu.num_busy_cycles 3295745694 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 1253 # number of replacements
system.cpu.icache.tagsinuse 881.283724 # Cycle average of tags in use
system.cpu.icache.tagsinuse 881.356492 # Cycle average of tags in use
system.cpu.icache.total_refs 1068344252 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 379653.252310 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 881.283724 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.430314 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.430314 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::cpu.inst 881.356492 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.430350 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.430350 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1068344252 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1068344252 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1068344252 # number of demand (read+write) hits
@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 2814 # n
system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses
system.cpu.icache.overall_misses::total 2814 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 117690500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 117690500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 117690500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 117690500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 117690500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 117690500 # number of overall miss cycles
system.cpu.icache.ReadReq_miss_latency::cpu.inst 115806000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 115806000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 115806000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 115806000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 115806000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 115806000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1068347066 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1068347066 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1068347066 # number of demand (read+write) accesses
@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000003
system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41823.205402 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 41823.205402 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 41823.205402 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 41823.205402 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 41823.205402 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 41823.205402 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41153.518124 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 41153.518124 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 41153.518124 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 41153.518124 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 41153.518124 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 41153.518124 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 2814
system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 112062500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 112062500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 112062500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 112062500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 112062500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 112062500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 110178000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 110178000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 110178000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 110178000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 110178000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 110178000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39823.205402 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39823.205402 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39823.205402 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 39823.205402 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39823.205402 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 39823.205402 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39153.518124 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39153.518124 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39153.518124 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39153.518124 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2514362 # number of replacements
system.cpu.dcache.tagsinuse 4086.427569 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4086.415788 # Cycle average of tags in use
system.cpu.dcache.total_refs 530743928 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 210.741624 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 8211722000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4086.427569 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.997663 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.997663 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::cpu.data 4086.415788 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.997660 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 382374771 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 382374771 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 148369157 # number of WriteReq hits
@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 2518458 # n
system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses
system.cpu.dcache.overall_misses::total 2518458 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 31594062000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 31594062000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 19100972000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 19100972000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 50695034000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 50695034000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 50695034000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 50695034000 # number of overall miss cycles
system.cpu.dcache.ReadReq_miss_latency::cpu.data 29704283000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 29704283000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 18964601500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 18964601500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 48668884500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 48668884500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 48668884500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 48668884500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 384102185 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 384102185 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses)
@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.004723
system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18289.803139 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 18289.803139 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24146.535465 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 24146.535465 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 20129.394256 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 20129.394256 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 20129.394256 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 20129.394256 # average overall miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17195.810037 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 17195.810037 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23974.142399 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 23974.142399 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19324.874387 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 19324.874387 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 19324.874387 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 19324.874387 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -200,8 +200,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2518458
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@ -226,68 +226,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723
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system.cpu.dcache.overall_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency
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@ -296,28 +296,28 @@ system.cpu.l2cache.demand_accesses::total 2521272 # n
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@ -326,52 +326,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
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system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40003.107198 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.353218 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.365602 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40003.107198 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.353218 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.365602 # average overall mshr miss latency
system.cpu.l2cache.writebacks::writebacks 292286 # number of writebacks
system.cpu.l2cache.writebacks::total 292286 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1886 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 172566 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 174452 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206691 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 206691 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1886 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 379257 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 381143 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1886 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 379257 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 381143 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 75452000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6902758000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 6978210000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8267645000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8267645000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 75452000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15170403000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 15245855000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 75452000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15170403000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 15245855000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099898 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.100826 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.261289 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.261289 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150591 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.151171 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150591 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.151171 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40006.362672 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.683796 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.745191 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.024191 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.024191 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40006.362672 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.324318 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.354198 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40006.362672 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.324318 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.354198 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

702
tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
View file

@ -1,38 +1,38 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.141149 # Number of seconds simulated
sim_ticks 141148809500 # Number of ticks simulated
final_tick 141148809500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.141089 # Number of seconds simulated
sim_ticks 141089296500 # Number of ticks simulated
final_tick 141089296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 76319 # Simulator instruction rate (inst/s)
host_op_rate 76319 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 27020959 # Simulator tick rate (ticks/s)
host_mem_usage 222760 # Number of bytes of host memory used
host_seconds 5223.68 # Real time elapsed on the host
host_inst_rate 83115 # Simulator instruction rate (inst/s)
host_op_rate 83115 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 29414893 # Simulator tick rate (ticks/s)
host_mem_usage 223012 # Number of bytes of host memory used
host_seconds 4796.53 # Real time elapsed on the host
sim_insts 398664595 # Number of instructions simulated
sim_ops 398664595 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 214592 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 254016 # Number of bytes read from this memory
system.physmem.bytes_read::total 468608 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 214592 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 214592 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 3353 # Number of read requests responded to by this memory
system.physmem.bytes_read::total 468992 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 214976 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 214976 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 3359 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7322 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1520325 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1799633 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 3319957 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1520325 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1520325 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1520325 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1799633 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3319957 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 7322 # Total number of read requests seen
system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1523688 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1800392 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 3324079 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1523688 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1523688 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1523688 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1800392 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3324079 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 7328 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 7322 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 468608 # Total number of bytes read from memory
system.physmem.cpureqs 7328 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 468992 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 468608 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedRd 468992 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
@ -41,17 +41,17 @@ system.physmem.perBankRdReqs::1 464 # Tr
system.physmem.perBankRdReqs::2 518 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 520 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 382 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 397 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 398 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 457 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 443 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 405 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 444 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 407 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 457 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 588 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 397 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 529 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 418 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 395 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 487 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 396 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 488 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 141148757500 # Total gap between requests
system.physmem.totGap 141089244500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 7322 # Categorize read packet sizes
system.physmem.readPktSize::6 7328 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
@ -98,12 +98,12 @@ system.physmem.neitherpktsize::5 0 # ca
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 5336 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 1506 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 331 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 124 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 25 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::0 4661 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 1890 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 520 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 190 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 66 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
@ -164,14 +164,14 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 28738807 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 171664807 # Sum of mem lat for all requests
system.physmem.totBusLat 29288000 # Total cycles spent in databus access
system.physmem.totBankLat 113638000 # Total cycles spent in bank access
system.physmem.avgQLat 3924.99 # Average queueing delay per request
system.physmem.avgBankLat 15520.08 # Average bank access latency per request
system.physmem.totQLat 39617295 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 175175295 # Sum of mem lat for all requests
system.physmem.totBusLat 29312000 # Total cycles spent in databus access
system.physmem.totBankLat 106246000 # Total cycles spent in bank access
system.physmem.avgQLat 5406.29 # Average queueing delay per request
system.physmem.avgBankLat 14498.64 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 23445.07 # Average memory access latency
system.physmem.avgMemAccLat 23904.93 # Average memory access latency
system.physmem.avgRdBW 3.32 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 3.32 # Average consumed read bandwidth in MB/s
@ -180,31 +180,31 @@ system.physmem.peakBW 16000.00 # Th
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
system.physmem.readRowHits 6437 # Number of row buffer hits during reads
system.physmem.readRowHits 6442 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 87.91 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 19277350.11 # Average gap between requests
system.physmem.avgGap 19253444.94 # Average gap between requests
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 94755019 # DTB read hits
system.cpu.dtb.read_hits 94754611 # DTB read hits
system.cpu.dtb.read_misses 21 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 94755040 # DTB read accesses
system.cpu.dtb.write_hits 73522092 # DTB write hits
system.cpu.dtb.read_accesses 94754632 # DTB read accesses
system.cpu.dtb.write_hits 73521102 # DTB write hits
system.cpu.dtb.write_misses 35 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 73522127 # DTB write accesses
system.cpu.dtb.data_hits 168277111 # DTB hits
system.cpu.dtb.write_accesses 73521137 # DTB write accesses
system.cpu.dtb.data_hits 168275713 # DTB hits
system.cpu.dtb.data_misses 56 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 168277167 # DTB accesses
system.cpu.itb.fetch_hits 49111843 # ITB hits
system.cpu.itb.fetch_misses 88782 # ITB misses
system.cpu.dtb.data_accesses 168275769 # DTB accesses
system.cpu.itb.fetch_hits 49091192 # ITB hits
system.cpu.itb.fetch_misses 88817 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 49200625 # ITB accesses
system.cpu.itb.fetch_accesses 49180009 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -218,42 +218,42 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 215 # Number of system calls
system.cpu.numCycles 282297620 # number of cpu cycles simulated
system.cpu.numCycles 282178594 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.lookups 53870359 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 30921660 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 16037209 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 33426943 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 15653988 # Number of BTB hits
system.cpu.branch_predictor.lookups 53863325 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 30909619 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 16029157 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 33388385 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 15622160 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 8007516 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 18 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 46.830451 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 29683847 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 24186512 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 280818433 # Number of Reads from Int. Register File
system.cpu.branch_predictor.RASInCorrect 19 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 46.789205 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 29654286 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 24209039 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 280812298 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 440154292 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 119907695 # Number of Reads from FP Register File
system.cpu.regfile_manager.intRegFileAccesses 440148157 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 119908557 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 220104176 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 100457659 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 168700458 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 14475221 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 1561329 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 16036550 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 28551001 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 35.966429 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 205750873 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 2124330 # Number of Multipy Operations Executed
system.cpu.regfile_manager.floatRegFileAccesses 220105038 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 100451904 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 168699560 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 14461353 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 1567145 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 16028498 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 28559053 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 35.948370 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 205751378 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 2124332 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 281928004 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.threadCycles 281883987 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 8014 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 13423125 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 268874495 # Number of cycles cpu stages are processed.
system.cpu.activity 95.245045 # Percentage of cycles cpu is active
system.cpu.timesIdled 7632 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 13336617 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 268841977 # Number of cycles cpu stages are processed.
system.cpu.activity 95.273696 # Percentage of cycles cpu is active
system.cpu.comLoads 94754489 # Number of Load instructions committed
system.cpu.comStores 73520729 # Number of Store instructions committed
system.cpu.comBranches 44587532 # Number of Branches instructions committed
@ -265,144 +265,144 @@ system.cpu.committedInsts 398664595 # Nu
system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total)
system.cpu.cpi 0.708108 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.cpi 0.707810 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 0.708108 # CPI: Total CPI of All Threads
system.cpu.ipc 1.412214 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.cpi_total 0.707810 # CPI: Total CPI of All Threads
system.cpu.ipc 1.412809 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 1.412214 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 78483642 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 203813978 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 72.198263 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 108810922 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 173486698 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 61.455246 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 104588213 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 177709407 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 62.951082 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 183516209 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 98781411 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 34.991939 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 92605054 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 189692566 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 67.195949 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 1974 # number of replacements
system.cpu.icache.tagsinuse 1830.000422 # Cycle average of tags in use
system.cpu.icache.total_refs 49107453 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 3901 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 12588.426814 # Average number of references to valid blocks.
system.cpu.ipc_total 1.412809 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 78396963 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 203781631 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 72.217254 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 108683745 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 173494849 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 61.484058 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 104474173 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 177704421 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 62.975869 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 183396585 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 98782009 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 35.006911 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 92487828 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 189690766 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 67.223656 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 1982 # number of replacements
system.cpu.icache.tagsinuse 1831.235862 # Cycle average of tags in use
system.cpu.icache.total_refs 49086683 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 3910 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 12554.138875 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1830.000422 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.893555 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.893555 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 49107453 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 49107453 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 49107453 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 49107453 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 49107453 # number of overall hits
system.cpu.icache.overall_hits::total 49107453 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 4389 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 4389 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 4389 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 4389 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 4389 # number of overall misses
system.cpu.icache.overall_misses::total 4389 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 191814500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 191814500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 191814500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 191814500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 191814500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 191814500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 49111842 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 49111842 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 49111842 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 49111842 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 49111842 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 49111842 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::total 0.000089 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::total 0.000089 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000089 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000089 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43703.463203 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 43703.463203 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 43703.463203 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 43703.463203 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 43703.463203 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 43703.463203 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_targets 66 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.icache.occ_blocks::cpu.inst 1831.235862 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.894158 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.894158 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::total 49086683 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 49086683 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 49086683 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 49086683 # number of overall hits
system.cpu.icache.overall_hits::total 49086683 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 4508 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 4508 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 4508 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 4508 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 4508 # number of overall misses
system.cpu.icache.overall_misses::total 4508 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 196984000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 196984000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 196984000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 196984000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 196984000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 196984000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 49091191 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 49091191 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 49091191 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 49091191 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 49091191 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 49091191 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000092 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000092 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000092 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000092 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000092 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000092 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43696.539485 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 43696.539485 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 43696.539485 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 43696.539485 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 43696.539485 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 43696.539485 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 220 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 488 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 488 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 488 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 488 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 488 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 488 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3901 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 3901 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 3901 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 3901 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 3901 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 3901 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 169767000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 169767000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 169767000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 169767000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 169767000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 169767000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000079 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43518.841323 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43518.841323 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43518.841323 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 43518.841323 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43518.841323 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 43518.841323 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 598 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 598 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 598 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 598 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 598 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 598 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3910 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 3910 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 3910 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 3910 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 3910 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 3910 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 172100500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 172100500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 172100500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 172100500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 172100500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 172100500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 44015.473146 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 44015.473146 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 44015.473146 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 44015.473146 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 44015.473146 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 44015.473146 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 764 # number of replacements
system.cpu.dcache.tagsinuse 3285.037423 # Cycle average of tags in use
system.cpu.dcache.total_refs 168261838 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 3285.555145 # Cycle average of tags in use
system.cpu.dcache.total_refs 168254416 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 40525.490848 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 40523.703276 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.occ_percent::cpu.data 0.802011 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.802011 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 94753259 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 94753259 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::total 73508579 # number of WriteReq hits
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system.cpu.dcache.overall_hits::total 168261838 # number of overall hits
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system.cpu.dcache.WriteReq_misses::cpu.data 12150 # number of WriteReq misses
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system.cpu.dcache.overall_misses::total 13380 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency::total 62962000 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::total 525724500 # number of WriteReq miss cycles
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system.cpu.dcache.occ_percent::cpu.data 0.802137 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits::cpu.data 94753185 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 94753185 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::total 73501231 # number of WriteReq hits
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system.cpu.dcache.demand_hits::total 168254416 # number of demand (read+write) hits
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system.cpu.dcache.overall_hits::total 168254416 # number of overall hits
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system.cpu.dcache.ReadReq_misses::total 1304 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 19498 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 19498 # number of WriteReq misses
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@ -411,40 +411,40 @@ system.cpu.dcache.demand_accesses::cpu.data 168275218 #
system.cpu.dcache.demand_accesses::total 168275218 # number of demand (read+write) accesses
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system.cpu.dcache.ReadReq_avg_miss_latency::total 51188.617886 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43269.506173 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 43269.506173 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 43997.496263 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 43997.496263 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 43997.496263 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 43997.496263 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 132949 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1897 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 70.083817 # average number of cycles each access was blocked
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000014 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000014 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000265 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000265 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000124 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000124 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000124 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000124 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49792.944785 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 49792.944785 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36421.120115 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 36421.120115 # average WriteReq miss latency
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system.cpu.dcache.demand_avg_miss_latency::total 37259.350062 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 37259.350062 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 37259.350062 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 15899 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 535 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.717757 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 649 # number of writebacks
system.cpu.dcache.writebacks::total 649 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 280 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 280 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 8948 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 8948 # number of WriteReq MSHR hits
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system.cpu.dcache.demand_mshr_hits::total 9228 # number of demand (read+write) MSHR hits
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system.cpu.dcache.overall_mshr_hits::total 9228 # number of overall MSHR hits
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system.cpu.dcache.ReadReq_mshr_hits::total 354 # number of ReadReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_hits::total 16296 # number of WriteReq MSHR hits
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system.cpu.dcache.demand_mshr_hits::total 16650 # number of demand (read+write) MSHR hits
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system.cpu.dcache.overall_mshr_hits::total 16650 # number of overall MSHR hits
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system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses
@ -453,14 +453,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152
system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses
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system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses
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system.cpu.dcache.ReadReq_mshr_miss_latency::total 47641000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency::total 148441000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency::total 196082000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency::total 153897000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
@ -469,98 +469,98 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50148.421053 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50148.421053 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46358.838226 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46358.838226 # average WriteReq mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 47225.915222 # average overall mshr miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48062.773267 # average WriteReq mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48642.943160 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 48642.943160 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 3900.679461 # Cycle average of tags in use
system.cpu.l2cache.total_refs 754 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 4711 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.160051 # Average number of references to valid blocks.
system.cpu.l2cache.tagsinuse 3908.656926 # Cycle average of tags in use
system.cpu.l2cache.total_refs 760 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 4717 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.161119 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 370.560631 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 2902.521753 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 627.597077 # Average occupied blocks per requestor
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system.cpu.l2cache.ReadReq_hits::cpu.inst 548 # number of ReadReq hits
system.cpu.l2cache.occ_blocks::writebacks 370.653922 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 2910.300742 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 627.702262 # Average occupied blocks per requestor
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system.cpu.l2cache.demand_hits::cpu.inst 551 # number of demand (read+write) hits
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system.cpu.l2cache.overall_miss_rate::total 0.908956 # miss rate for overall accesses
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@ -569,50 +569,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3353 # number of ReadReq MSHR misses
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system.cpu.l2cache.demand_mshr_misses::total 7328 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3359 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 7322 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117992891 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 34864220 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 152857111 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 105232120 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 105232120 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117992891 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 140096340 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 258089231 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117992891 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 140096340 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 258089231 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 120134545 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 35298214 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 155432759 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 111138322 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 111138322 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 120134545 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 146436536 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 266571081 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 120134545 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 146436536 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 266571081 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.859079 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.861592 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.861231 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981279 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981279 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.859079 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.909226 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for overall accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.908956 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.859079 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.909226 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35190.244855 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42310.946602 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36594.951161 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33460.133545 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33460.133545 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35190.244855 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35297.641723 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35248.460940 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35190.244855 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35297.641723 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35248.460940 # average overall mshr miss latency
system.cpu.l2cache.overall_mshr_miss_rate::total 0.908956 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35764.973206 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42837.638350 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37158.202008 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35338.099205 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35338.099205 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35764.973206 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36895.070799 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36377.057997 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35764.973206 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36895.070799 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36377.057997 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

1137
tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
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14
tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.567335 # Nu
sim_ticks 567335093000 # Number of ticks simulated
final_tick 567335093000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1259990 # Simulator instruction rate (inst/s)
host_op_rate 1259990 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1793077476 # Simulator tick rate (ticks/s)
host_mem_usage 225476 # Number of bytes of host memory used
host_seconds 316.40 # Real time elapsed on the host
host_inst_rate 1803555 # Simulator instruction rate (inst/s)
host_op_rate 1803555 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2566617886 # Simulator tick rate (ticks/s)
host_mem_usage 223016 # Number of bytes of host memory used
host_seconds 221.04 # Real time elapsed on the host
sim_insts 398664609 # Number of instructions simulated
sim_ops 398664609 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory
@ -262,9 +262,9 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::total 51148.843931
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 3772.485305 # Cycle average of tags in use
system.cpu.l2cache.total_refs 674 # Total number of references to valid blocks.
system.cpu.l2cache.total_refs 677 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 4566 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.147613 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 0.148270 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 371.540221 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 2770.469924 # Average occupied blocks per requestor

1135
tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
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1299
tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
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368
tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
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@ -1,39 +1,39 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.811836 # Number of seconds simulated
sim_ticks 2811836424000 # Number of ticks simulated
final_tick 2811836424000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 2.769740 # Number of seconds simulated
sim_ticks 2769739533000 # Number of ticks simulated
final_tick 2769739533000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1325085 # Simulator instruction rate (inst/s)
host_op_rate 1325085 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1854626286 # Simulator tick rate (ticks/s)
host_mem_usage 228472 # Number of bytes of host memory used
host_seconds 1516.12 # Real time elapsed on the host
host_inst_rate 1761560 # Simulator instruction rate (inst/s)
host_op_rate 1761559 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2428616742 # Simulator tick rate (ticks/s)
host_mem_usage 226024 # Number of bytes of host memory used
host_seconds 1140.46 # Real time elapsed on the host
sim_insts 2008987605 # Number of instructions simulated
sim_ops 2008987605 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 152128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 94417856 # Number of bytes read from this memory
system.physmem.bytes_read::total 94569984 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 152128 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 152128 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4281472 # Number of bytes written to this memory
system.physmem.bytes_written::total 4281472 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 2377 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1475279 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1477656 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66898 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66898 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 54103 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 33578716 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 33632818 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 54103 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 54103 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1522660 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1522660 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1522660 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 54103 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 33578716 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 35155479 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 137792 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 30284544 # Number of bytes read from this memory
system.physmem.bytes_read::total 30422336 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 137792 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 137792 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory
system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 2153 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 473196 # Number of read requests responded to by this memory
system.physmem.num_reads::total 475349 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 49749 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 10934077 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 10983826 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 49749 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 49749 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1546034 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1546034 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1546034 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 49749 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 10934077 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 12529860 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 39 # Number of system calls
system.cpu.numCycles 5623672848 # number of cpu cycles simulated
system.cpu.numCycles 5539479066 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 2008987605 # Number of instructions committed
@ -86,18 +86,18 @@ system.cpu.num_mem_refs 722298387 # nu
system.cpu.num_load_insts 511488910 # Number of load instructions
system.cpu.num_store_insts 210809477 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 5623672848 # Number of busy cycles
system.cpu.num_busy_cycles 5539479066 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 9046 # number of replacements
system.cpu.icache.tagsinuse 1478.427768 # Cycle average of tags in use
system.cpu.icache.tagsinuse 1478.418050 # Cycle average of tags in use
system.cpu.icache.total_refs 2009410475 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 189638.587675 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1478.427768 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.721889 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.721889 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::cpu.inst 1478.418050 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.721884 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.721884 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 2009410475 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 2009410475 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 2009410475 # number of demand (read+write) hits
@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 10596 # n
system.cpu.icache.demand_misses::total 10596 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 10596 # number of overall misses
system.cpu.icache.overall_misses::total 10596 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 237582000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 237582000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 237582000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 237582000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 237582000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 237582000 # number of overall miss cycles
system.cpu.icache.ReadReq_miss_latency::cpu.inst 228174000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 228174000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 228174000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 228174000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 228174000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 228174000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 2009421071 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 2009421071 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 2009421071 # number of demand (read+write) accesses
@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000005
system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22421.857305 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 22421.857305 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22421.857305 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 22421.857305 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22421.857305 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 22421.857305 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21533.975085 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 21533.975085 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21533.975085 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 21533.975085 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21533.975085 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 21533.975085 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 10596
system.cpu.icache.demand_mshr_misses::total 10596 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 10596 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 10596 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 216390000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 216390000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 216390000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 216390000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 216390000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 216390000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 206982000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 206982000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 206982000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 206982000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 206982000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 206982000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20421.857305 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20421.857305 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20421.857305 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 20421.857305 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20421.857305 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 20421.857305 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19533.975085 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19533.975085 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19533.975085 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 19533.975085 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19533.975085 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 19533.975085 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1526048 # number of replacements
system.cpu.dcache.tagsinuse 4095.209846 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4095.197836 # Cycle average of tags in use
system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks.
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system.cpu.dcache.warmup_cycle 1041395000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.occ_blocks::cpu.data 4095.197836 # Average occupied blocks per requestor
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@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 1530144 # n
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system.cpu.dcache.ReadReq_miss_latency::total 36022065000 # number of ReadReq miss cycles
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@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002120
system.cpu.dcache.demand_miss_rate::total 0.002120 # miss rate for demand accesses
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system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24703.238668 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 24703.238668 # average ReadReq miss latency
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@ -232,8 +232,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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@ -258,68 +258,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002120
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system.cpu.l2cache.demand_mshr_misses::cpu.data 1475279 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 1477656 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2377 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1475279 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 1477656 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 95080000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 56336240000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 56431320000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2153 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 473196 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 475349 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2153 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 473196 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 475349 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 86120000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16252923000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16339043000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2674920000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2674920000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 95080000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 59011160000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 59106240000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 95080000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59011160000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 59106240000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.224330 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.965858 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.960508 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 86120000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18927843000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 19013963000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 86120000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18927843000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 19013963000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.203190 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278648 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278104 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.929411 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.929411 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.224330 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964144 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.959056 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.224330 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964144 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.959056 # mshr miss rate for overall accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.203190 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.309249 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.308520 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.203190 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.309249 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.308520 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.007383 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.007344 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.006340 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.006311 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.006340 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.006311 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

1335
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

356
tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,39 +1,39 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.368273 # Number of seconds simulated
sim_ticks 2368273403000 # Number of ticks simulated
final_tick 2368273403000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 2.326119 # Number of seconds simulated
sim_ticks 2326118592000 # Number of ticks simulated
final_tick 2326118592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 821983 # Simulator instruction rate (inst/s)
host_op_rate 1115078 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1408999350 # Simulator tick rate (ticks/s)
host_mem_usage 241788 # Number of bytes of host memory used
host_seconds 1680.82 # Real time elapsed on the host
host_inst_rate 541548 # Simulator instruction rate (inst/s)
host_op_rate 734649 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 911769830 # Simulator tick rate (ticks/s)
host_mem_usage 240408 # Number of bytes of host memory used
host_seconds 2551.21 # Real time elapsed on the host
sim_insts 1381604339 # Number of instructions simulated
sim_ops 1874244941 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 144448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 94437440 # Number of bytes read from this memory
system.physmem.bytes_read::total 94581888 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 144448 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 144448 # Number of instructions bytes read from this memory
system.physmem.bytes_read::cpu.inst 113472 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 30232512 # Number of bytes read from this memory
system.physmem.bytes_read::total 30345984 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 113472 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 113472 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory
system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 2257 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1475585 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1477842 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 1773 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 472383 # Number of read requests responded to by this memory
system.physmem.num_reads::total 474156 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 60993 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 39876072 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 39937065 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 60993 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 60993 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1786253 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1786253 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1786253 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 60993 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 39876072 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 41723318 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 48782 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 12996978 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 13045760 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 48782 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 48782 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1818624 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1818624 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1818624 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 48782 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 12996978 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 14864384 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -77,7 +77,7 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1411 # Number of system calls
system.cpu.numCycles 4736546806 # number of cpu cycles simulated
system.cpu.numCycles 4652237184 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1381604339 # Number of instructions committed
@ -96,18 +96,18 @@ system.cpu.num_mem_refs 908382479 # nu
system.cpu.num_load_insts 631387181 # Number of load instructions
system.cpu.num_store_insts 276995298 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 4736546806 # Number of busy cycles
system.cpu.num_busy_cycles 4652237184 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 18364 # number of replacements
system.cpu.icache.tagsinuse 1392.329214 # Cycle average of tags in use
system.cpu.icache.tagsinuse 1392.317060 # Cycle average of tags in use
system.cpu.icache.total_refs 1390251699 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 19803 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 70204.095289 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1392.329214 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.679848 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.679848 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::cpu.inst 1392.317060 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.679842 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.679842 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1390251699 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1390251699 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1390251699 # number of demand (read+write) hits
@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst 19803 # n
system.cpu.icache.demand_misses::total 19803 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 19803 # number of overall misses
system.cpu.icache.overall_misses::total 19803 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 352238000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 352238000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 352238000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 352238000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 352238000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 352238000 # number of overall miss cycles
system.cpu.icache.ReadReq_miss_latency::cpu.inst 331911000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 331911000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 331911000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 331911000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 331911000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 331911000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1390271502 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1390271502 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1390271502 # number of demand (read+write) accesses
@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000014
system.cpu.icache.demand_miss_rate::total 0.000014 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000014 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000014 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17787.102964 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 17787.102964 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 17787.102964 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 17787.102964 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 17787.102964 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 17787.102964 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16760.642327 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 16760.642327 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16760.642327 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 16760.642327 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16760.642327 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 16760.642327 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 19803
system.cpu.icache.demand_mshr_misses::total 19803 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 19803 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 19803 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 312632000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 312632000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 312632000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 312632000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 312632000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 312632000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 292305000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 292305000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 292305000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 292305000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 292305000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 292305000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000014 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000014 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000014 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15787.102964 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15787.102964 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15787.102964 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 15787.102964 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15787.102964 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 15787.102964 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14760.642327 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14760.642327 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14760.642327 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 14760.642327 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14760.642327 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 14760.642327 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1529557 # number of replacements
system.cpu.dcache.tagsinuse 4094.965929 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4094.947189 # Cycle average of tags in use
system.cpu.dcache.total_refs 895757408 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1533653 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 584.067848 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 991199000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4094.965929 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999748 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999748 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::cpu.data 4094.947189 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999743 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999743 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 618874540 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 618874540 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 276862898 # number of WriteReq hits
@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data 1533653 # n
system.cpu.dcache.demand_misses::total 1533653 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1533653 # number of overall misses
system.cpu.dcache.overall_misses::total 1533653 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 78190013000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 78190013000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::cpu.data 36055529000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 36055529000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 3722046000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 3722046000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 81912059000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 81912059000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 81912059000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 81912059000 # number of overall miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 39777575000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 39777575000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 39777575000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 39777575000 # number of overall miss cycles
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system.cpu.dcache.ReadReq_accesses::total 620335413 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.001709
system.cpu.dcache.demand_miss_rate::total 0.001709 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.001709 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.001709 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53522.799723 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 53522.799723 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24680.810036 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 24680.810036 # average ReadReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::total 51141.055235 # average WriteReq miss latency
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system.cpu.dcache.demand_avg_miss_latency::total 53409.773267 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 53409.773267 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 53409.773267 # average overall miss latency
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system.cpu.dcache.demand_avg_miss_latency::total 25936.489545 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 25936.489545 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 25936.489545 # average overall miss latency
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -250,8 +250,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
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@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1533653
system.cpu.dcache.demand_mshr_misses::total 1533653 # number of demand (read+write) MSHR misses
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system.cpu.dcache.overall_mshr_miss_latency::total 36710269000 # number of overall MSHR miss cycles
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@ -276,68 +276,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001709
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system.cpu.dcache.overall_avg_mshr_miss_latency::total 23936.489545 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.tagsinuse 32690.092056 # Cycle average of tags in use
system.cpu.l2cache.total_refs 77413 # Total number of references to valid blocks.
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system.cpu.l2cache.occ_blocks::writebacks 1298.141733 # Average occupied blocks per requestor
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@ -346,28 +346,28 @@ system.cpu.l2cache.demand_accesses::total 1553456 # n
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@ -378,50 +378,50 @@ system.cpu.l2cache.fast_writes 0 # nu
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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113973 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964829 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.953449 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70926000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18895320000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 18966246000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70926000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18895320000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 18966246000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.089532 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278115 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.275592 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.908120 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.908120 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113973 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.962137 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.951325 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113973 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.962137 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.951325 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.215330 # average ReadReq mshr miss latency
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.089532 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.308012 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.305227 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.089532 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.308012 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.305227 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40003.384095 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.003542 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.014704 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40002.215330 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40003.384095 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.003383 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40002.215330 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.012654 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40003.384095 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.003383 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.012654 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

942
tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
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1365
tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
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432
tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
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@ -1,39 +1,39 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.133756 # Number of seconds simulated
sim_ticks 133756135000 # Number of ticks simulated
final_tick 133756135000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.133635 # Number of seconds simulated
sim_ticks 133634727000 # Number of ticks simulated
final_tick 133634727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1270571 # Simulator instruction rate (inst/s)
host_op_rate 1270570 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1923763163 # Simulator tick rate (ticks/s)
host_mem_usage 227600 # Number of bytes of host memory used
host_seconds 69.53 # Real time elapsed on the host
host_inst_rate 783809 # Simulator instruction rate (inst/s)
host_op_rate 783809 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1185683886 # Simulator tick rate (ticks/s)
host_mem_usage 225136 # Number of bytes of host memory used
host_seconds 112.71 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
sim_ops 88340673 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 485312 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10270528 # Number of bytes read from this memory
system.physmem.bytes_read::total 10755840 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 485312 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 485312 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7421120 # Number of bytes written to this memory
system.physmem.bytes_written::total 7421120 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 7583 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 160477 # Number of read requests responded to by this memory
system.physmem.num_reads::total 168060 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 115955 # Number of write requests responded to by this memory
system.physmem.num_writes::total 115955 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 3628335 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 76785472 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 80413807 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 3628335 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 3628335 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 55482464 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 55482464 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 55482464 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 3628335 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 76785472 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 135896271 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 432896 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10136896 # Number of bytes read from this memory
system.physmem.bytes_read::total 10569792 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 432896 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 432896 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7294848 # Number of bytes written to this memory
system.physmem.bytes_written::total 7294848 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 6764 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 158389 # Number of read requests responded to by this memory
system.physmem.num_reads::total 165153 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 113982 # Number of write requests responded to by this memory
system.physmem.num_writes::total 113982 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 3239397 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 75855253 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 79094650 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 3239397 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 3239397 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 54587966 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 54587966 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 54587966 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 3239397 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 75855253 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 133682617 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls
system.cpu.numCycles 267512270 # number of cpu cycles simulated
system.cpu.numCycles 267269454 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 88340673 # Number of instructions committed
@ -86,18 +86,18 @@ system.cpu.num_mem_refs 34987415 # nu
system.cpu.num_load_insts 20366786 # Number of load instructions
system.cpu.num_store_insts 14620629 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 267512270 # Number of busy cycles
system.cpu.num_busy_cycles 267269454 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 74391 # number of replacements
system.cpu.icache.tagsinuse 1871.674409 # Cycle average of tags in use
system.cpu.icache.tagsinuse 1871.686406 # Cycle average of tags in use
system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1156.021220 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1871.674409 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.913904 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.913904 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::cpu.inst 1871.686406 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.913909 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.913909 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 88361638 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 88361638 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 88361638 # number of demand (read+write) hits
@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 76436 # n
system.cpu.icache.demand_misses::total 76436 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 76436 # number of overall misses
system.cpu.icache.overall_misses::total 76436 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1312229000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 1312229000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 1312229000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 1312229000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 1312229000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 1312229000 # number of overall miss cycles
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1278112000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 1278112000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 1278112000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 1278112000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 1278112000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 1278112000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 88438074 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 88438074 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 88438074 # number of demand (read+write) accesses
@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000864
system.cpu.icache.demand_miss_rate::total 0.000864 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000864 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000864 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17167.682767 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 17167.682767 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 17167.682767 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 17167.682767 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 17167.682767 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 17167.682767 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16721.335496 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 16721.335496 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16721.335496 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 16721.335496 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16721.335496 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 16721.335496 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 76436
system.cpu.icache.demand_mshr_misses::total 76436 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 76436 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 76436 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1159357000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 1159357000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1159357000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 1159357000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1159357000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 1159357000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1125240000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 1125240000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1125240000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 1125240000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1125240000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 1125240000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000864 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000864 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000864 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15167.682767 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15167.682767 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15167.682767 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 15167.682767 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15167.682767 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 15167.682767 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14721.335496 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14721.335496 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14721.335496 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 14721.335496 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14721.335496 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 14721.335496 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 200248 # number of replacements
system.cpu.dcache.tagsinuse 4078.879185 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4078.863631 # Cycle average of tags in use
system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 936463000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4078.879185 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.995820 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.995820 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::cpu.data 4078.863631 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.995816 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits
@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 204344 # n
system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses
system.cpu.dcache.overall_misses::total 204344 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2026896000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 2026896000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 7369702000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 7369702000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 9396598000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 9396598000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 9396598000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 9396598000 # number of overall miss cycles
system.cpu.dcache.ReadReq_miss_latency::cpu.data 1945752000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 1945752000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 7363555000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 7363555000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 9309307000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 9309307000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 9309307000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 9309307000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.005857
system.cpu.dcache.demand_miss_rate::total 0.005857 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33355.758154 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 33355.758154 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51328.908329 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 51328.908329 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 45984.212896 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 45984.212896 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 45984.212896 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 45984.212896 # average overall miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32020.406148 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 32020.406148 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51286.095363 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 51286.095363 # average WriteReq miss latency
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system.cpu.dcache.overall_avg_miss_latency::cpu.data 45557.036174 # average overall miss latency
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -232,8 +232,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses
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@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204344
system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses
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@ -258,68 +258,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43557.036174 # average overall mshr miss latency
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system.cpu.l2cache.tagsinuse 29005.267541 # Cycle average of tags in use
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@ -328,28 +328,28 @@ system.cpu.l2cache.demand_accesses::total 280780 # n
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@ -358,52 +358,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40009.890545 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40002.716561 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40004.185569 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.091583 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.091583 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40009.890545 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.573291 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.993693 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40009.890545 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.573291 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.993693 # average overall mshr miss latency
system.cpu.l2cache.writebacks::writebacks 113982 # number of writebacks
system.cpu.l2cache.writebacks::total 113982 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 6764 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27508 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 34272 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130881 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 130881 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 6764 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 158389 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 165153 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 6764 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 158389 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 165153 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 270916000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1100778000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1371694000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5235279000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5235279000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 270916000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6336057000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 6606973000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 270916000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6336057000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 6606973000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088492 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.452687 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.249792 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911567 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911567 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088492 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775110 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.588194 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088492 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775110 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.588194 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40052.631579 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40016.649702 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40023.751167 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.297981 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.297981 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40052.631579 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40003.137844 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.164908 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40052.631579 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40003.137844 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.164908 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

1433
tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

432
tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,39 +1,39 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.132746 # Number of seconds simulated
sim_ticks 132746076000 # Number of ticks simulated
final_tick 132746076000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.132689 # Number of seconds simulated
sim_ticks 132689045000 # Number of ticks simulated
final_tick 132689045000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 594787 # Simulator instruction rate (inst/s)
host_op_rate 843423 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1121948184 # Simulator tick rate (ticks/s)
host_mem_usage 240564 # Number of bytes of host memory used
host_seconds 118.32 # Real time elapsed on the host
host_inst_rate 796611 # Simulator instruction rate (inst/s)
host_op_rate 1129615 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1502004709 # Simulator tick rate (ticks/s)
host_mem_usage 239164 # Number of bytes of host memory used
host_seconds 88.34 # Real time elapsed on the host
sim_insts 70373628 # Number of instructions simulated
sim_ops 99791654 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 273728 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8003456 # Number of bytes read from this memory
system.physmem.bytes_read::total 8277184 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 273728 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 273728 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 5403392 # Number of bytes written to this memory
system.physmem.bytes_written::total 5403392 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 4277 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 125054 # Number of read requests responded to by this memory
system.physmem.num_reads::total 129331 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 84428 # Number of write requests responded to by this memory
system.physmem.num_writes::total 84428 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 2062042 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 60291470 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 62353512 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 2062042 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 2062042 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 40704721 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 40704721 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 40704721 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 2062042 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 60291470 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 103058233 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 255488 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 7924480 # Number of bytes read from this memory
system.physmem.bytes_read::total 8179968 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 255488 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 255488 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 5370176 # Number of bytes written to this memory
system.physmem.bytes_written::total 5370176 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 3992 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 123820 # Number of read requests responded to by this memory
system.physmem.num_reads::total 127812 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 83909 # Number of write requests responded to by this memory
system.physmem.num_writes::total 83909 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 1925464 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 59722187 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 61647651 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1925464 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1925464 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 40471887 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 40471887 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 40471887 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1925464 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 59722187 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 102119538 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -77,7 +77,7 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.numCycles 265492152 # number of cpu cycles simulated
system.cpu.numCycles 265378090 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 70373628 # Number of instructions committed
@ -96,18 +96,18 @@ system.cpu.num_mem_refs 47862847 # nu
system.cpu.num_load_insts 27307108 # Number of load instructions
system.cpu.num_store_insts 20555739 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 265492152 # Number of busy cycles
system.cpu.num_busy_cycles 265378090 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 16890 # number of replacements
system.cpu.icache.tagsinuse 1736.430287 # Cycle average of tags in use
system.cpu.icache.tagsinuse 1736.497265 # Cycle average of tags in use
system.cpu.icache.total_refs 78126161 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 18908 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 4131.910355 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1736.430287 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.847866 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.847866 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::cpu.inst 1736.497265 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.847899 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.847899 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 78126161 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 78126161 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 78126161 # number of demand (read+write) hits
@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst 18908 # n
system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses
system.cpu.icache.overall_misses::total 18908 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 425522000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 425522000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 425522000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 425522000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 425522000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 425522000 # number of overall miss cycles
system.cpu.icache.ReadReq_miss_latency::cpu.inst 413722000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 413722000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 413722000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 413722000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 413722000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 413722000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 78145069 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 78145069 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 78145069 # number of demand (read+write) accesses
@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000242
system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22504.865665 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 22504.865665 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22504.865665 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 22504.865665 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22504.865665 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 22504.865665 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21880.791199 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 21880.791199 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21880.791199 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 21880.791199 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21880.791199 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 21880.791199 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 18908
system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 387706000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 387706000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 387706000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 387706000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 387706000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 387706000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 375906000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 375906000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 375906000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 375906000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 375906000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 375906000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20504.865665 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20504.865665 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20504.865665 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 20504.865665 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20504.865665 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 20504.865665 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19880.791199 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19880.791199 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19880.791199 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 19880.791199 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19880.791199 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 19880.791199 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 155902 # number of replacements
system.cpu.dcache.tagsinuse 4076.962537 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4076.954355 # Cycle average of tags in use
system.cpu.dcache.total_refs 46862074 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 159998 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 292.891624 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 1072595000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4076.962537 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.995352 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.995352 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::cpu.data 4076.954355 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.995350 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.995350 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 27087367 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 27087367 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits
@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data 159998 # n
system.cpu.dcache.demand_misses::total 159998 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 159998 # number of overall misses
system.cpu.dcache.overall_misses::total 159998 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 1642566000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 1642566000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689754000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 5689754000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 7332320000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 7332320000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 7332320000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 7332320000 # number of overall miss cycles
system.cpu.dcache.ReadReq_miss_latency::cpu.data 1599899000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 1599899000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5687190000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 5687190000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 7287089000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 7287089000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 7287089000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 7287089000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 27140333 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 27140333 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.003405
system.cpu.dcache.demand_miss_rate::total 0.003405 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.003405 # miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_miss_latency::total 31011.705622 # average ReadReq miss latency
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system.cpu.dcache.demand_avg_miss_latency::total 45827.572845 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 45827.572845 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 45827.572845 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::cpu.data 45544.875561 # average overall miss latency
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -250,8 +250,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 159998
system.cpu.dcache.demand_mshr_misses::total 159998 # number of demand (read+write) MSHR misses
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@ -276,68 +276,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003405
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system.cpu.dcache.overall_avg_mshr_miss_latency::total 43544.875561 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.tagsinuse 28875.776749 # Cycle average of tags in use
system.cpu.l2cache.total_refs 71387 # Total number of references to valid blocks.
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system.cpu.l2cache.replacements 94693 # number of replacements
system.cpu.l2cache.tagsinuse 30368.194893 # Cycle average of tags in use
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system.cpu.l2cache.sampled_refs 125788 # Sample count of references to valid blocks.
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@ -346,28 +346,28 @@ system.cpu.l2cache.demand_accesses::total 178906 # n
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@ -376,52 +376,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.226201 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.428822 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.375518 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.956172 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.956172 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.226201 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.781597 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.722899 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.226201 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.781597 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.722899 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40019.639935 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40002.729714 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40005.409411 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.156340 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.156340 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40019.639935 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.623731 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40001.252600 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40019.639935 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.623731 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40001.252600 # average overall mshr miss latency
system.cpu.l2cache.writebacks::writebacks 83909 # number of writebacks
system.cpu.l2cache.writebacks::total 83909 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3992 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21540 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 25532 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102280 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 102280 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3992 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 123820 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 127812 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3992 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 123820 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 127812 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 159934000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 868261000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1028195000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4091214000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4091214000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 159934000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4959475000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 5119409000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 159934000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4959475000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 5119409000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.406676 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.355233 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955602 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955602 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773885 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.714409 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773885 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.714409 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40063.627255 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40309.238626 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40270.836597 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.136879 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.136879 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40063.627255 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40053.908900 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40054.212437 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40063.627255 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40053.908900 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40054.212437 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

434
tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
View file

@ -1,41 +1,41 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.202343 # Number of seconds simulated
sim_ticks 202342809000 # Number of ticks simulated
final_tick 202342809000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.202242 # Number of seconds simulated
sim_ticks 202242260000 # Number of ticks simulated
final_tick 202242260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1232815 # Simulator instruction rate (inst/s)
host_op_rate 1248778 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1856050290 # Simulator tick rate (ticks/s)
host_mem_usage 230736 # Number of bytes of host memory used
host_seconds 109.02 # Real time elapsed on the host
host_inst_rate 1258181 # Simulator instruction rate (inst/s)
host_op_rate 1274472 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1893298806 # Simulator tick rate (ticks/s)
host_mem_usage 233128 # Number of bytes of host memory used
host_seconds 106.82 # Real time elapsed on the host
sim_insts 134398962 # Number of instructions simulated
sim_ops 136139190 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 665664 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 7906112 # Number of bytes read from this memory
system.physmem.bytes_read::total 8571776 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 665664 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 665664 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 5301376 # Number of bytes written to this memory
system.physmem.bytes_written::total 5301376 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 10401 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 123533 # Number of read requests responded to by this memory
system.physmem.num_reads::total 133934 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 82834 # Number of write requests responded to by this memory
system.physmem.num_writes::total 82834 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 3289783 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 39072859 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 42362642 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 3289783 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 3289783 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 26199972 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 26199972 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 26199972 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 3289783 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 39072859 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 68562614 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 591488 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 7826624 # Number of bytes read from this memory
system.physmem.bytes_read::total 8418112 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 591488 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 591488 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 5303552 # Number of bytes written to this memory
system.physmem.bytes_written::total 5303552 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 9242 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 122291 # Number of read requests responded to by this memory
system.physmem.num_reads::total 131533 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 82868 # Number of write requests responded to by this memory
system.physmem.num_writes::total 82868 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 2924651 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 38699251 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 41623902 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 2924651 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 2924651 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 26223758 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 26223758 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 26223758 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 2924651 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 38699251 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 67847660 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.numCycles 404685618 # number of cpu cycles simulated
system.cpu.numCycles 404484520 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 134398962 # Number of instructions committed
@ -54,18 +54,18 @@ system.cpu.num_mem_refs 58160248 # nu
system.cpu.num_load_insts 37275867 # Number of load instructions
system.cpu.num_store_insts 20884381 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 404685618 # Number of busy cycles
system.cpu.num_busy_cycles 404484520 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 184976 # number of replacements
system.cpu.icache.tagsinuse 2004.814192 # Cycle average of tags in use
system.cpu.icache.tagsinuse 2004.815325 # Cycle average of tags in use
system.cpu.icache.total_refs 134366547 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 718.445478 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 144074079000 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 2004.814192 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.978913 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.978913 # Average percentage of cache occupancy
system.cpu.icache.warmup_cycle 143972294000 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 2004.815325 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.978914 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.978914 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 134366547 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 134366547 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 134366547 # number of demand (read+write) hits
@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 187024 # n
system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses
system.cpu.icache.overall_misses::total 187024 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 2868177000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 2868177000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 2868177000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 2868177000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 2868177000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 2868177000 # number of overall miss cycles
system.cpu.icache.ReadReq_miss_latency::cpu.inst 2819681000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 2819681000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 2819681000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 2819681000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 2819681000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 2819681000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 134553571 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 134553571 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 134553571 # number of demand (read+write) accesses
@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.001390
system.cpu.icache.demand_miss_rate::total 0.001390 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.001390 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15335.876679 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 15335.876679 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 15335.876679 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 15335.876679 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 15335.876679 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 15335.876679 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15076.573060 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 15076.573060 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 15076.573060 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 15076.573060 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 15076.573060 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 15076.573060 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 187024
system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2494129000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 2494129000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2494129000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 2494129000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2494129000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 2494129000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2445633000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 2445633000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2445633000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 2445633000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2445633000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 2445633000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001390 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.001390 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13335.876679 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13335.876679 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13335.876679 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13335.876679 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13335.876679 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13335.876679 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13076.573060 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13076.573060 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13076.573060 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13076.573060 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13076.573060 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13076.573060 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 146582 # number of replacements
system.cpu.dcache.tagsinuse 4087.652500 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4087.648350 # Cycle average of tags in use
system.cpu.dcache.total_refs 57960842 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 384.666919 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 769040000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4087.652500 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.997962 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.997962 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::cpu.data 4087.648350 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.997961 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 37185801 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 37185801 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits
@ -164,16 +164,16 @@ system.cpu.dcache.demand_misses::cpu.data 150663 # n
system.cpu.dcache.demand_misses::total 150663 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 150663 # number of overall misses
system.cpu.dcache.overall_misses::total 150663 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 1523847000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 1523847000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5622992000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 5622992000 # number of WriteReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::cpu.data 1475111000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 1475111000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5619675000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 5619675000 # number of WriteReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::cpu.data 405000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::total 405000 # number of SwapReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 7146839000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 7146839000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 7146839000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 7146839000 # number of overall miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 7094786000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 7094786000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 7094786000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 7094786000 # number of overall miss cycles
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system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses)
@ -194,16 +194,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002593
system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33491.878942 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 33491.878942 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53468.791602 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 53468.791602 # average WriteReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32420.734522 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 32420.734522 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53437.250390 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 53437.250390 # average WriteReq miss latency
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system.cpu.dcache.SwapReq_avg_miss_latency::total 27000 # average SwapReq miss latency
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system.cpu.dcache.demand_avg_miss_latency::total 47435.926538 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 47435.926538 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 47435.926538 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 47090.433617 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 47090.433617 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 47090.433617 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 47090.433617 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -212,8 +212,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.writebacks::total 122378 # number of writebacks
system.cpu.dcache.writebacks::writebacks 123970 # number of writebacks
system.cpu.dcache.writebacks::total 123970 # number of writebacks
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system.cpu.dcache.ReadReq_mshr_misses::total 45499 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses
@ -224,16 +224,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 150663
system.cpu.dcache.demand_mshr_misses::total 150663 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 150663 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 150663 # number of overall MSHR misses
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system.cpu.dcache.WriteReq_mshr_miss_latency::total 5412664000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1384113000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1384113000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency::total 5409347000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 375000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::total 375000 # number of SwapReq MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency::total 6845513000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::total 6845513000 # number of overall MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6793460000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6793460000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 6793460000 # number of overall MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses
@ -244,70 +244,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593
system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31491.878942 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31491.878942 # average ReadReq mshr miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51468.791602 # average WriteReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30420.734522 # average ReadReq mshr miss latency
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system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 25000 # average SwapReq mshr miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency::total 45435.926538 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45435.926538 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45090.433617 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 45090.433617 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 101560 # number of replacements
system.cpu.l2cache.tagsinuse 29290.996090 # Cycle average of tags in use
system.cpu.l2cache.total_refs 222505 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 132357 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 1.681097 # Average number of references to valid blocks.
system.cpu.l2cache.replacements 98540 # number of replacements
system.cpu.l2cache.tagsinuse 30850.759699 # Cycle average of tags in use
system.cpu.l2cache.total_refs 226933 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 129534 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 1.751918 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 24775.786415 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 3266.546663 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 1248.663012 # Average occupied blocks per requestor
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system.cpu.l2cache.overall_hits::cpu.data 27145 # number of overall hits
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system.cpu.l2cache.Writeback_accesses::writebacks 122378 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 122378 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 123970 # number of Writeback accesses(hits+misses)
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@ -316,28 +316,28 @@ system.cpu.l2cache.demand_accesses::total 337702 # n
system.cpu.l2cache.overall_accesses::cpu.inst 187024 # number of overall (read+write) accesses
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system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52022.181346 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52007.321131 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52011.857185 # average ReadReq miss latency
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system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.267469 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52022.181346 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.267469 # average overall miss latency
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@ -346,52 +346,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.l2cache.demand_mshr_misses::cpu.inst 10401 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 123533 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 133934 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 10401 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 123533 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 133934 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 416063000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 887964000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1304027000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4053400000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4053400000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 416063000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4941364000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 5357427000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 416063000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4941364000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 5357427000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.055613 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.487879 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.140197 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.963453 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.963453 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.055613 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.819848 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.396604 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.055613 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.819848 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.396604 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.211326 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40001.982161 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40002.055278 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40002.211326 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.356180 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.500246 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40002.211326 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.356180 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.500246 # average overall mshr miss latency
system.cpu.l2cache.writebacks::writebacks 82868 # number of writebacks
system.cpu.l2cache.writebacks::total 82868 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 9242 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21035 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 30277 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101256 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 101256 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 9242 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 122291 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 131533 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 9242 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 122291 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 131533 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 369885000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 841554000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1211439000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4050241000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4050241000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 369885000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4891795000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 5261680000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 369885000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4891795000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 5261680000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.049416 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.462318 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.130211 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.962702 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.962702 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.049416 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.811605 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.389494 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.049416 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.811605 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.389494 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40022.181346 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40007.321131 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40011.857185 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.009876 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.009876 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40022.181346 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40001.267469 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40002.736956 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40022.181346 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40001.267469 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40002.736956 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

890
tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
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tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
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tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
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@ -1,39 +1,39 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.631385 # Number of seconds simulated
sim_ticks 2631384990000 # Number of ticks simulated
final_tick 2631384990000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 2.623386 # Number of seconds simulated
sim_ticks 2623386226000 # Number of ticks simulated
final_tick 2623386226000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1011793 # Simulator instruction rate (inst/s)
host_op_rate 1011793 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1463043658 # Simulator tick rate (ticks/s)
host_mem_usage 219388 # Number of bytes of host memory used
host_seconds 1798.57 # Real time elapsed on the host
host_inst_rate 1789114 # Simulator instruction rate (inst/s)
host_op_rate 1789114 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2579177735 # Simulator tick rate (ticks/s)
host_mem_usage 217052 # Number of bytes of host memory used
host_seconds 1017.14 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 137580288 # Number of bytes read from this memory
system.physmem.bytes_read::total 137631616 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 125367104 # Number of bytes read from this memory
system.physmem.bytes_read::total 125418432 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 51328 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 51328 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 67105600 # Number of bytes written to this memory
system.physmem.bytes_written::total 67105600 # Number of bytes written to this memory
system.physmem.bytes_written::writebacks 65156928 # Number of bytes written to this memory
system.physmem.bytes_written::total 65156928 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 802 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2149692 # Number of read requests responded to by this memory
system.physmem.num_reads::total 2150494 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1048525 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1048525 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 19506 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 52284363 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 52303869 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 19506 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 19506 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 25502008 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 25502008 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 25502008 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 19506 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 52284363 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 77805877 # Total bandwidth to/from this memory (bytes/s)
system.physmem.num_reads::cpu.data 1958861 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1959663 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1018077 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1018077 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 19566 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 47788276 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 47807841 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 19566 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 19566 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 24836956 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 24836956 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 24836956 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 19566 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 47788276 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 72644797 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
system.cpu.numCycles 5262769980 # number of cpu cycles simulated
system.cpu.numCycles 5246772452 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1819780127 # Number of instructions committed
@ -86,18 +86,18 @@ system.cpu.num_mem_refs 611922547 # nu
system.cpu.num_load_insts 449492741 # Number of load instructions
system.cpu.num_store_insts 162429806 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 5262769980 # Number of busy cycles
system.cpu.num_busy_cycles 5246772452 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 1 # number of replacements
system.cpu.icache.tagsinuse 612.470356 # Cycle average of tags in use
system.cpu.icache.tagsinuse 612.458646 # Cycle average of tags in use
system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 2277278.937656 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 612.470356 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.299058 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.299058 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::cpu.inst 612.458646 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.299052 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.299052 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1826377708 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1826377708 # number of demand (read+write) hits
@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 802 # n
system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses
system.cpu.icache.overall_misses::total 802 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 44120000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 44120000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 44120000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 44120000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 44120000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 44120000 # number of overall miss cycles
system.cpu.icache.ReadReq_miss_latency::cpu.inst 44182000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 44182000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 44182000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 44182000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 44182000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 44182000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1826378510 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1826378510 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1826378510 # number of demand (read+write) accesses
@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000
system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55012.468828 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 55012.468828 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55012.468828 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 55012.468828 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55012.468828 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 55012.468828 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55089.775561 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 55089.775561 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55089.775561 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 55089.775561 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55089.775561 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 55089.775561 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 802
system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42516000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 42516000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42516000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 42516000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42516000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 42516000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42578000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 42578000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42578000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 42578000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42578000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 42578000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53012.468828 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53012.468828 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53012.468828 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 53012.468828 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53012.468828 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53012.468828 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53089.775561 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53089.775561 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53089.775561 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 53089.775561 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53089.775561 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53089.775561 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 9107638 # number of replacements
system.cpu.dcache.tagsinuse 4079.313701 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4079.262869 # Cycle average of tags in use
system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 40977019000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4079.313701 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.995926 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.995926 # Average percentage of cache occupancy
system.cpu.dcache.warmup_cycle 40977439000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4079.262869 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.995914 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.995914 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits
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@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 9111734 # n
system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses
system.cpu.dcache.overall_misses::total 9111734 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency::total 151059345000 # number of ReadReq miss cycles
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system.cpu.dcache.demand_miss_latency::total 208750732000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 208750732000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 208750732000 # number of overall miss cycles
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system.cpu.dcache.ReadReq_miss_latency::total 143374726000 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::total 57377180000 # number of WriteReq miss cycles
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system.cpu.dcache.demand_miss_latency::total 200751906000 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency::total 200751906000 # number of overall miss cycles
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@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.015053
system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses
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system.cpu.dcache.ReadReq_avg_miss_latency::total 20915.353925 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30535.529714 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 30535.529714 # average WriteReq miss latency
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system.cpu.dcache.demand_avg_miss_latency::total 22910.099439 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22910.099439 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 22910.099439 # average overall miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::total 30369.222789 # average WriteReq miss latency
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system.cpu.dcache.demand_avg_miss_latency::total 22032.239528 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22032.239528 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 22032.239528 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -232,8 +232,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.writebacks::writebacks 3389919 # number of writebacks
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system.cpu.dcache.writebacks::writebacks 3693497 # number of writebacks
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system.cpu.dcache.ReadReq_mshr_misses::total 7222414 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889320 # number of WriteReq MSHR misses
@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9111734
system.cpu.dcache.demand_mshr_misses::total 9111734 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9111734 # number of overall MSHR misses
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system.cpu.dcache.WriteReq_mshr_miss_latency::total 53912747000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency::total 190527264000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 190527264000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 190527264000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128929898000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 128929898000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182528438000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 182528438000 # number of overall MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses
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@ -258,65 +258,65 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053
system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20032.239528 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20032.239528 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.tagsinuse 30159.988647 # Cycle average of tags in use
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system.cpu.l2cache.warmup_cycle 218167128000 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52021.930093 # average ReadReq miss latency
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@ -355,52 +355,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1360883 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 1361685 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 788809 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 788809 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177560 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 1178362 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781301 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 781301 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 2149692 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 2150494 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 1958861 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 1959663 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2149692 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 2150494 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32090000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54446197000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54478287000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31552609000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31552609000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32090000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 85998806000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 86030896000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32090000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 85998806000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 86030896000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_misses::cpu.data 1958861 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 1959663 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32152000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47128224000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47160376000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31253418000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31253418000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32152000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78381642000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 78413794000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32152000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78381642000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 78413794000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188425 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188515 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.417509 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.417509 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163042 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163135 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413536 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413536 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235926 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.235993 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214982 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.215051 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235926 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.235993 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40012.468828 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40007.992605 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40007.995241 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.315666 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.315666 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40012.468828 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40005.175625 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.178345 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40012.468828 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.175625 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.178345 # average overall mshr miss latency
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214982 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.215051 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40089.775561 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40021.930093 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40021.976269 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40001.763725 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40001.763725 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40089.775561 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40013.886641 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40013.917699 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40089.775561 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40013.886641 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40013.917699 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

1334
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

398
tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,39 +1,39 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.399400 # Number of seconds simulated
sim_ticks 2399400439000 # Number of ticks simulated
final_tick 2399400439000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 2.391205 # Number of seconds simulated
sim_ticks 2391205115000 # Number of ticks simulated
final_tick 2391205115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 994913 # Simulator instruction rate (inst/s)
host_op_rate 1110332 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1551375376 # Simulator tick rate (ticks/s)
host_mem_usage 233816 # Number of bytes of host memory used
host_seconds 1546.63 # Real time elapsed on the host
host_inst_rate 1213159 # Simulator instruction rate (inst/s)
host_op_rate 1353897 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1885227488 # Simulator tick rate (ticks/s)
host_mem_usage 231376 # Number of bytes of host memory used
host_seconds 1268.39 # Real time elapsed on the host
sim_insts 1538759601 # Number of instructions simulated
sim_ops 1717270334 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 137819840 # Number of bytes read from this memory
system.physmem.bytes_read::total 137859264 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 125322112 # Number of bytes read from this memory
system.physmem.bytes_read::total 125361536 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 67221184 # Number of bytes written to this memory
system.physmem.bytes_written::total 67221184 # Number of bytes written to this memory
system.physmem.bytes_written::writebacks 65100672 # Number of bytes written to this memory
system.physmem.bytes_written::total 65100672 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2153435 # Number of read requests responded to by this memory
system.physmem.num_reads::total 2154051 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1050331 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1050331 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 16431 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 57439283 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 57455713 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 16431 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 16431 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 28015825 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 28015825 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 28015825 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 16431 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 57439283 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 85471539 # Total bandwidth to/from this memory (bytes/s)
system.physmem.num_reads::cpu.data 1958158 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1958774 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1017198 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1017198 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 16487 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 52409604 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 52426091 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 16487 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 16487 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 27225047 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 27225047 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 27225047 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 16487 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 52409604 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 79651138 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -77,7 +77,7 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.numCycles 4798800878 # number of cpu cycles simulated
system.cpu.numCycles 4782410230 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1538759601 # Number of instructions committed
@ -96,18 +96,18 @@ system.cpu.num_mem_refs 660773815 # nu
system.cpu.num_load_insts 485926769 # Number of load instructions
system.cpu.num_store_insts 174847046 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 4798800878 # Number of busy cycles
system.cpu.num_busy_cycles 4782410230 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 7 # number of replacements
system.cpu.icache.tagsinuse 514.980115 # Cycle average of tags in use
system.cpu.icache.tagsinuse 514.976015 # Cycle average of tags in use
system.cpu.icache.total_refs 1544564952 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 638 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 2420948.200627 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 514.980115 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.251455 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.251455 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::cpu.inst 514.976015 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.251453 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.251453 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1544564952 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1544564952 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1544564952 # number of demand (read+write) hits
@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst 638 # n
system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses
system.cpu.icache.overall_misses::total 638 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 34189000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 34189000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 34189000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 34189000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 34189000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 34189000 # number of overall miss cycles
system.cpu.icache.ReadReq_miss_latency::cpu.inst 34233000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 34233000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 34233000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 34233000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 34233000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 34233000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1544565590 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1544565590 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1544565590 # number of demand (read+write) accesses
@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000
system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53587.774295 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 53587.774295 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 53587.774295 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 53587.774295 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 53587.774295 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 53587.774295 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53656.739812 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 53656.739812 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 53656.739812 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 53656.739812 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 53656.739812 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 53656.739812 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 638
system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32913000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 32913000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32913000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 32913000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32913000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 32913000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32957000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 32957000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32957000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 32957000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32957000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 32957000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51587.774295 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51587.774295 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51587.774295 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 51587.774295 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51587.774295 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 51587.774295 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51656.739812 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51656.739812 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51656.739812 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 51656.739812 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51656.739812 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 51656.739812 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 9111140 # number of replacements
system.cpu.dcache.tagsinuse 4083.564925 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4083.522356 # Cycle average of tags in use
system.cpu.dcache.total_refs 645855059 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 9115236 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 70.854453 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 25914432000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4083.564925 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.996964 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.996964 # Average percentage of cache occupancy
system.cpu.dcache.warmup_cycle 25914401000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4083.522356 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.996954 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.996954 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 475158039 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 475158039 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits
@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data 9115236 # n
system.cpu.dcache.demand_misses::total 9115236 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses
system.cpu.dcache.overall_misses::total 9115236 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency::total 151247261000 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::total 57698979000 # number of WriteReq miss cycles
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system.cpu.dcache.demand_miss_latency::total 208946240000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 208946240000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 208946240000 # number of overall miss cycles
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system.cpu.dcache.ReadReq_miss_latency::total 143391866000 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::total 57359006000 # number of WriteReq miss cycles
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system.cpu.dcache.demand_miss_latency::total 200750872000 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency::total 200750872000 # number of overall miss cycles
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system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.013917
system.cpu.dcache.demand_miss_rate::total 0.013917 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.013917 # miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20930.727931 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 20930.727931 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30542.312438 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 30542.312438 # average WriteReq miss latency
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system.cpu.dcache.demand_avg_miss_latency::total 22922.746048 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22922.746048 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 22922.746048 # average overall miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.639580 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.639580 # average ReadReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.351514 # average WriteReq miss latency
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system.cpu.dcache.demand_avg_miss_latency::total 22023.661483 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22023.661483 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 22023.661483 # average overall miss latency
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -250,8 +250,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.ReadReq_mshr_misses::total 7226087 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses
@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9115236
system.cpu.dcache.demand_mshr_misses::total 9115236 # number of demand (read+write) MSHR misses
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system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses
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system.cpu.dcache.WriteReq_mshr_miss_latency::total 53920681000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency::total 190715768000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 190715768000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::total 182520400000 # number of overall MSHR miss cycles
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@ -276,68 +276,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013917
system.cpu.dcache.demand_mshr_miss_rate::total 0.013917 # mshr miss rate for demand accesses
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28542.312438 # average WriteReq mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20922.746048 # average overall mshr miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20023.661483 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2138446 # number of replacements
system.cpu.l2cache.tagsinuse 30623.782374 # Cycle average of tags in use
system.cpu.l2cache.total_refs 8443619 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 2168151 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 3.894387 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 435858689000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 14787.769987 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.data 15820.243429 # Average occupied blocks per requestor
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system.cpu.l2cache.tagsinuse 30987.094489 # Cycle average of tags in use
system.cpu.l2cache.total_refs 8967572 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 1955843 # Sample count of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 154026636000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 15648.493745 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 24.153175 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 15314.447570 # Average occupied blocks per requestor
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@ -347,27 +347,27 @@ system.cpu.l2cache.overall_accesses::cpu.inst 638
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system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.811989 # average overall miss latency
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system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52005.853313 # average ReadReq miss latency
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@ -376,52 +376,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.l2cache.writebacks::writebacks 1050331 # number of writebacks
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system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 789028 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 789028 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177282 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 1177898 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 780876 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 780876 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 2153435 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 2154051 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 1958158 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 1958774 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2153435 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 2154051 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24663000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54579316000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54603979000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31561986000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31561986000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24663000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86141302000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 86165965000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24663000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86141302000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 86165965000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_misses::cpu.data 1958158 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 1958774 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24707000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47098171000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47122878000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31238317000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31238317000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24707000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78336488000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 78361195000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24707000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78336488000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 78361195000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188817 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188885 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.417663 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.417663 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162921 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.162992 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413348 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413348 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.236246 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.236297 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.214875 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.236246 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.236297 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40037.337662 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40002.225142 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40002.240988 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40001.097553 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40001.097553 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40037.337662 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40001.811989 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40001.822148 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40037.337662 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40001.811989 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40001.822148 # average overall mshr miss latency
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.214875 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40108.766234 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40005.853313 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40005.907133 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40004.196569 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40004.196569 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40108.766234 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40005.192635 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.225207 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40108.766234 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.192635 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.225207 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

398
tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,41 +1,41 @@
---------- Begin Simulation Statistics ----------
sim_seconds 5.891582 # Number of seconds simulated
sim_ticks 5891581948000 # Number of ticks simulated
final_tick 5891581948000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 5.882581 # Number of seconds simulated
sim_ticks 5882580524000 # Number of ticks simulated
final_tick 5882580524000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 701685 # Simulator instruction rate (inst/s)
host_op_rate 1093289 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1374310212 # Simulator tick rate (ticks/s)
host_mem_usage 228764 # Number of bytes of host memory used
host_seconds 4286.94 # Real time elapsed on the host
host_inst_rate 472403 # Simulator instruction rate (inst/s)
host_op_rate 736047 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 923827707 # Simulator tick rate (ticks/s)
host_mem_usage 227772 # Number of bytes of host memory used
host_seconds 6367.62 # Real time elapsed on the host
sim_insts 3008081022 # Number of instructions simulated
sim_ops 4686862594 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 139043584 # Number of bytes read from this memory
system.physmem.bytes_read::total 139086784 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 125326976 # Number of bytes read from this memory
system.physmem.bytes_read::total 125370176 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 67393856 # Number of bytes written to this memory
system.physmem.bytes_written::total 67393856 # Number of bytes written to this memory
system.physmem.bytes_written::writebacks 65178944 # Number of bytes written to this memory
system.physmem.bytes_written::total 65178944 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2172556 # Number of read requests responded to by this memory
system.physmem.num_reads::total 2173231 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1053029 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1053029 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7332 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 23600382 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 23607714 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7332 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7332 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 11439009 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 11439009 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 11439009 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7332 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 23600382 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 35046723 # Total bandwidth to/from this memory (bytes/s)
system.physmem.num_reads::cpu.data 1958234 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1958909 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1018421 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1018421 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7344 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 21304762 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 21312105 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7344 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7344 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 11079992 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 11079992 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 11079992 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7344 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 21304762 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 32392097 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.numCycles 11783163896 # number of cpu cycles simulated
system.cpu.numCycles 11765161048 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 3008081022 # Number of instructions committed
@ -54,18 +54,18 @@ system.cpu.num_mem_refs 1677713082 # nu
system.cpu.num_load_insts 1239184745 # Number of load instructions
system.cpu.num_store_insts 438528337 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 11783163896 # Number of busy cycles
system.cpu.num_busy_cycles 11765161048 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 10 # number of replacements
system.cpu.icache.tagsinuse 555.725129 # Cycle average of tags in use
system.cpu.icache.tagsinuse 555.705054 # Cycle average of tags in use
system.cpu.icache.total_refs 4013232208 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 5945529.197037 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 555.725129 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.271350 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.271350 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::cpu.inst 555.705054 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.271340 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.271340 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 4013232208 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 4013232208 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 4013232208 # number of demand (read+write) hits
@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 675 # n
system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses
system.cpu.icache.overall_misses::total 675 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 37130000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 37130000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 37130000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 37130000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 37130000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 37130000 # number of overall miss cycles
system.cpu.icache.ReadReq_miss_latency::cpu.inst 37156000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 37156000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 37156000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 37156000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 37156000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 37156000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 4013232883 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 4013232883 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 4013232883 # number of demand (read+write) accesses
@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000
system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55007.407407 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 55007.407407 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55007.407407 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 55007.407407 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55007.407407 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 55007.407407 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55045.925926 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 55045.925926 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55045.925926 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 55045.925926 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55045.925926 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 55045.925926 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 675
system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35780000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 35780000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35780000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 35780000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35780000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 35780000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35806000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 35806000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35806000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 35806000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35806000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 35806000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53007.407407 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53007.407407 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53007.407407 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 53007.407407 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53007.407407 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53007.407407 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53045.925926 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53045.925926 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53045.925926 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53045.925926 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 9108581 # number of replacements
system.cpu.dcache.tagsinuse 4084.604436 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4084.587031 # Cycle average of tags in use
system.cpu.dcache.total_refs 1668600405 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 58853994000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4084.604436 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.997218 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.997218 # Average percentage of cache occupancy
system.cpu.dcache.warmup_cycle 58853920000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4084.587031 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.997214 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1231961895 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1231961895 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 436638510 # number of WriteReq hits
@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 9112677 # n
system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses
system.cpu.dcache.overall_misses::total 9112677 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 151971083000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 151971083000 # number of ReadReq miss cycles
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system.cpu.dcache.overall_miss_latency::total 209712206000 # number of overall miss cycles
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system.cpu.dcache.ReadReq_miss_latency::total 143328541000 # number of ReadReq miss cycles
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@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.005432
system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses
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system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30553.655440 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 30553.655440 # average WriteReq miss latency
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system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.443895 # average overall miss latency
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@ -200,8 +200,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9112677
system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses
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system.cpu.dcache.WriteReq_mshr_miss_latency::total 53961469000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency::total 191486852000 # number of demand (read+write) MSHR miss cycles
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@ -226,65 +226,65 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432
system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.tagsinuse 30849.854795 # Cycle average of tags in use
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system.cpu.l2cache.sampled_refs 1955980 # Sample count of references to valid blocks.
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system.cpu.l2cache.occ_blocks::cpu.inst 25.641016 # Average occupied blocks per requestor
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@ -294,27 +294,27 @@ system.cpu.l2cache.overall_accesses::cpu.inst 675
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@ -323,52 +323,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.l2cache.demand_mshr_misses::total 2173231 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 1958234 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 1958909 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2172556 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 2173231 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27005000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 55308603000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 55335608000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31593690000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31593690000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27005000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86902293000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 86929298000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27005000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86902293000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 86929298000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_misses::cpu.data 1958234 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 1958909 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27031000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47077613000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47104644000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31251874000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31251874000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27031000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78329487000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 78356518000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27031000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78329487000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 78356518000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.191436 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.191512 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.417944 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.417944 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162947 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163025 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413421 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413421 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.238410 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.238467 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214891 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.214949 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.238410 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.238467 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40007.407407 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.002170 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.005783 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.063304 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.063304 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40007.407407 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.024395 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.026688 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40007.407407 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.024395 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.026688 # average overall mshr miss latency
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214891 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.214949 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40045.925926 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.045032 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.071331 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.094715 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.094715 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40045.925926 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.064854 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.080657 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40045.925926 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.064854 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.080657 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

536
tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
View file

@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.041975 # Number of seconds simulated
sim_ticks 41974805000 # Number of ticks simulated
final_tick 41974805000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.041949 # Number of seconds simulated
sim_ticks 41948719000 # Number of ticks simulated
final_tick 41948719000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 82989 # Simulator instruction rate (inst/s)
host_op_rate 82989 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 37903288 # Simulator tick rate (ticks/s)
host_mem_usage 220440 # Number of bytes of host memory used
host_seconds 1107.42 # Real time elapsed on the host
host_inst_rate 82495 # Simulator instruction rate (inst/s)
host_op_rate 82495 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 37654494 # Simulator tick rate (ticks/s)
host_mem_usage 221732 # Number of bytes of host memory used
host_seconds 1114.04 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated
sim_ops 91903056 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 178816 # Nu
system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory
system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 4260079 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3269009 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 7529088 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 4260079 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 4260079 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 4260079 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3269009 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 7529088 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 4262728 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3271041 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 7533770 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 4262728 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 4262728 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 4262728 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3271041 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 7533770 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 4938 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 4938 # Reqs generatd by CPU via cache - shady
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 41974753000 # Total gap between requests
system.physmem.totGap 41948681000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
@ -98,13 +98,13 @@ system.physmem.neitherpktsize::5 0 # ca
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 3879 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 789 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 235 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 24 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::0 3467 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 991 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 438 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
@ -164,14 +164,14 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 15273921 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 109715921 # Sum of mem lat for all requests
system.physmem.totQLat 18563928 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 107349928 # Sum of mem lat for all requests
system.physmem.totBusLat 19752000 # Total cycles spent in databus access
system.physmem.totBankLat 74690000 # Total cycles spent in bank access
system.physmem.avgQLat 3093.14 # Average queueing delay per request
system.physmem.avgBankLat 15125.56 # Average bank access latency per request
system.physmem.totBankLat 69034000 # Total cycles spent in bank access
system.physmem.avgQLat 3759.40 # Average queueing delay per request
system.physmem.avgBankLat 13980.15 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 22218.70 # Average memory access latency
system.physmem.avgMemAccLat 21739.56 # Average memory access latency
system.physmem.avgRdBW 7.53 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 7.53 # Average consumed read bandwidth in MB/s
@ -184,27 +184,27 @@ system.physmem.readRowHits 4458 # Nu
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 90.28 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 8500355.00 # Average gap between requests
system.physmem.avgGap 8495075.13 # Average gap between requests
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 19996215 # DTB read hits
system.cpu.dtb.read_hits 19996251 # DTB read hits
system.cpu.dtb.read_misses 10 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 19996225 # DTB read accesses
system.cpu.dtb.write_hits 6501907 # DTB write hits
system.cpu.dtb.read_accesses 19996261 # DTB read accesses
system.cpu.dtb.write_hits 6501863 # DTB write hits
system.cpu.dtb.write_misses 23 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 6501930 # DTB write accesses
system.cpu.dtb.data_hits 26498122 # DTB hits
system.cpu.dtb.write_accesses 6501886 # DTB write accesses
system.cpu.dtb.data_hits 26498114 # DTB hits
system.cpu.dtb.data_misses 33 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 26498155 # DTB accesses
system.cpu.itb.fetch_hits 10035744 # ITB hits
system.cpu.dtb.data_accesses 26498147 # DTB accesses
system.cpu.itb.fetch_hits 10035746 # ITB hits
system.cpu.itb.fetch_misses 49 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 10035793 # ITB accesses
system.cpu.itb.fetch_accesses 10035795 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -218,26 +218,26 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 389 # Number of system calls
system.cpu.numCycles 83949611 # number of cpu cycles simulated
system.cpu.numCycles 83897439 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.lookups 13564912 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 9782242 # Number of conditional branches predicted
system.cpu.branch_predictor.lookups 13564910 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 9782241 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 4497823 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 7992579 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 3850502 # Number of BTB hits
system.cpu.branch_predictor.BTBLookups 7992573 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 3850501 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 1029619 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 122 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 48.175964 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 5999728 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.BTBHitPct 48.175988 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 5999726 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 7565184 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 73745301 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileReads 73745307 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 136320773 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 2206799 # Number of Reads from FP Register File
system.cpu.regfile_manager.intRegFileAccesses 136320779 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 2206802 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 8058687 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 38528717 # Number of Registers Read Through Forwarding Logic
system.cpu.regfile_manager.floatRegFileAccesses 8058690 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 38528710 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 26769089 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 3520477 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 976488 # Number of Branches Incorrectly Predicted As Not Taken).
@ -248,12 +248,12 @@ system.cpu.execution_unit.executions 57470360 # Nu
system.cpu.mult_div_unit.multiplies 458258 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 83639616 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.threadCycles 83635742 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 11375 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 7667023 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 76282588 # Number of cycles cpu stages are processed.
system.cpu.activity 90.867113 # Percentage of cycles cpu is active
system.cpu.timesIdled 10897 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 7614848 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 76282591 # Number of cycles cpu stages are processed.
system.cpu.activity 90.923623 # Percentage of cycles cpu is active
system.cpu.comLoads 19996198 # Number of Load instructions committed
system.cpu.comStores 6501103 # Number of Store instructions committed
system.cpu.comBranches 10240685 # Number of Branches instructions committed
@ -265,144 +265,144 @@ system.cpu.committedInsts 91903056 # Nu
system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total)
system.cpu.cpi 0.913458 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.cpi 0.912891 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 0.913458 # CPI: Total CPI of All Threads
system.cpu.ipc 1.094741 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.cpi_total 0.912891 # CPI: Total CPI of All Threads
system.cpu.ipc 1.095421 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 1.094741 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 27728071 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 56221540 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 66.970578 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 34502106 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 49447505 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 58.901411 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 33971546 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 49978065 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 59.533409 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 65920043 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 18029568 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 21.476655 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 30005535 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 53944076 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 64.257684 # Percentage of cycles stage was utilized (processing insts).
system.cpu.ipc_total 1.095421 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 27675918 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 56221521 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 67.012202 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 34449958 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 49447481 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 58.938010 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 33919397 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 49978042 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 59.570402 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 65867839 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 18029600 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 21.490048 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 29953374 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 53944065 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 64.297630 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 8127 # number of replacements
system.cpu.icache.tagsinuse 1492.468291 # Cycle average of tags in use
system.cpu.icache.total_refs 10023999 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 1492.667941 # Cycle average of tags in use
system.cpu.icache.total_refs 10023995 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 10012 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1001.198462 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 1001.198062 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1492.468291 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.728744 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.728744 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 10023999 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 10023999 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 10023999 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 10023999 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 10023999 # number of overall hits
system.cpu.icache.overall_hits::total 10023999 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 11743 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 11743 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 11743 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 11743 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 11743 # number of overall misses
system.cpu.icache.overall_misses::total 11743 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 259067500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 259067500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 259067500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 259067500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 259067500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 259067500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 10035742 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 10035742 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 10035742 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 10035742 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::total 10035742 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::total 0.001170 # miss rate for ReadReq accesses
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system.cpu.icache.overall_miss_rate::total 0.001170 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22061.440858 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 22061.440858 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22061.440858 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 22061.440858 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22061.440858 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 22061.440858 # average overall miss latency
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system.cpu.icache.ReadReq_hits::total 10023995 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 10023995 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 10023995 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::total 10023995 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 11751 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 11751 # number of ReadReq misses
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system.cpu.icache.demand_misses::total 11751 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 11751 # number of overall misses
system.cpu.icache.overall_misses::total 11751 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 259062500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 259062500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 259062500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 259062500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 259062500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 259062500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 10035746 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 10035746 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 10035746 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 10035746 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 10035746 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 10035746 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::total 0.001171 # miss rate for ReadReq accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.001171 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.001171 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22045.996085 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 22045.996085 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22045.996085 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 22045.996085 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22045.996085 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 22045.996085 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked
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system.cpu.icache.overall_mshr_hits::total 1731 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_hits::cpu.inst 1739 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 1739 # number of overall MSHR hits
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system.cpu.icache.ReadReq_mshr_miss_latency::total 209799500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 209799500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 209799500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 209799500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 209799500 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000998 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000998 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000998 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21012.235318 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21012.235318 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21012.235318 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 21012.235318 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21012.235318 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 21012.235318 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20954.804235 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20954.804235 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20954.804235 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20954.804235 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 20954.804235 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.tagsinuse 1441.629591 # Cycle average of tags in use
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system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
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@ -411,40 +411,40 @@ system.cpu.dcache.demand_accesses::cpu.data 26497301 #
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system.cpu.dcache.overall_avg_miss_latency::cpu.data 41412.293853 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 41412.293853 # average overall miss latency
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.dcache.overall_mshr_hits::cpu.data 3895 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 3895 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 100 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 100 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6348 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 6348 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 6448 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 6448 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 6448 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 6448 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses
@ -453,14 +453,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223
system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23282500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 23282500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 80468500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 80468500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 103751000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 103751000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 103751000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 103751000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22783000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 22783000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 82274500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 82274500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 105057500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 105057500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 105057500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 105057500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses
@ -469,28 +469,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084
system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49015.789474 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49015.789474 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46034.610984 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46034.610984 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46671.614935 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 46671.614935 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46671.614935 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 46671.614935 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47964.210526 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47964.210526 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47067.791762 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47067.791762 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 47259.334233 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 47259.334233 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 47259.334233 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 47259.334233 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 2189.948520 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 2190.279989 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7285 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.219683 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 17.843388 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 1821.063413 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 351.041719 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::writebacks 17.844336 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 1821.341583 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 351.094069 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.055574 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.010713 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.066832 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.055583 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.010715 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.066842 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 7218 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 7271 # number of ReadReq hits
@ -515,17 +515,17 @@ system.cpu.l2cache.demand_misses::total 4938 # nu
system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses
system.cpu.l2cache.overall_misses::total 4938 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 127870000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22259000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 150129000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 78446500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 78446500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 127870000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 100705500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 228575500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 127870000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 100705500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 228575500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 127295000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21759500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 149054500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 80257000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 80257000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 127295000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 102016500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 229311500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 127295000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 102016500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 229311500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 10012 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 10487 # number of ReadReq accesses(hits+misses)
@ -550,17 +550,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.403596 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.279065 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.403596 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 45765.926986 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52746.445498 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 46681.902985 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 45555.458769 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 45555.458769 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 45765.926986 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46970.848881 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 46289.084650 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 45765.926986 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46970.848881 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 46289.084650 # average overall miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 45560.128848 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 51562.796209 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 46347.792289 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 46606.852497 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 46606.852497 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 45560.128848 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47582.322761 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 46438.132847 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 45560.128848 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47582.322761 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 46438.132847 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -580,17 +580,17 @@ system.cpu.l2cache.demand_mshr_misses::total 4938
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 92500808 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16940683 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 109441491 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 57047489 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 57047489 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 92500808 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 73988172 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 166488980 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 92500808 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 73988172 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 166488980 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 91926812 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16443678 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 108370490 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 59040867 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 59040867 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 91926812 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 75484545 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 167411357 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 91926812 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 75484545 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 167411357 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.279065 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.306665 # mshr miss rate for ReadReq accesses
@ -602,17 +602,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.403596
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.279065 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.403596 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33106.946314 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40143.798578 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34030.314366 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33128.623113 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33128.623113 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33106.946314 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34509.408582 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33715.872823 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33106.946314 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34509.408582 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33715.872823 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32901.507516 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38966.061611 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33697.291667 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 34286.217770 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 34286.217770 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32901.507516 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35207.343750 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33902.664439 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32901.507516 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35207.343750 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33902.664439 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

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tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
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tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
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tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
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tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
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@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000020 # Number of seconds simulated
sim_ticks 19841500 # Number of ticks simulated
final_tick 19841500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.000019 # Number of seconds simulated
sim_ticks 18769500 # Number of ticks simulated
final_tick 18769500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 31060 # Simulator instruction rate (inst/s)
host_op_rate 31057 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 96425663 # Simulator tick rate (ticks/s)
host_mem_usage 216044 # Number of bytes of host memory used
host_seconds 0.21 # Real time elapsed on the host
host_inst_rate 10228 # Simulator instruction rate (inst/s)
host_op_rate 10227 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 30039955 # Simulator tick rate (ticks/s)
host_mem_usage 216300 # Number of bytes of host memory used
host_seconds 0.62 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19200 # Nu
system.physmem.num_reads::cpu.inst 300 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory
system.physmem.num_reads::total 468 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 967668775 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 541894514 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1509563289 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 967668775 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 967668775 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 967668775 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 541894514 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1509563289 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 1022936146 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 572844242 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1595780388 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1022936146 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1022936146 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1022936146 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 572844242 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1595780388 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 469 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 469 # Reqs generatd by CPU via cache - shady
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 19827000 # Total gap between requests
system.physmem.totGap 18755000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
@ -98,8 +98,8 @@ system.physmem.neitherpktsize::5 0 # ca
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 334 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 108 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::0 304 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 138 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
@ -164,47 +164,47 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 1719468 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 11463468 # Sum of mem lat for all requests
system.physmem.totQLat 1862969 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 11662969 # Sum of mem lat for all requests
system.physmem.totBusLat 1876000 # Total cycles spent in databus access
system.physmem.totBankLat 7868000 # Total cycles spent in bank access
system.physmem.avgQLat 3666.24 # Average queueing delay per request
system.physmem.avgBankLat 16776.12 # Average bank access latency per request
system.physmem.totBankLat 7924000 # Total cycles spent in bank access
system.physmem.avgQLat 3972.22 # Average queueing delay per request
system.physmem.avgBankLat 16895.52 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 24442.36 # Average memory access latency
system.physmem.avgRdBW 1509.56 # Average achieved read bandwidth in MB/s
system.physmem.avgMemAccLat 24867.74 # Average memory access latency
system.physmem.avgRdBW 1595.78 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 1509.56 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedRdBW 1595.78 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 9.43 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.58 # Average read queue length over time
system.physmem.busUtil 9.97 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.62 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
system.physmem.readRowHits 401 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 85.50 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 42275.05 # Average gap between requests
system.physmem.avgGap 39989.34 # Average gap between requests
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 1184 # DTB read hits
system.cpu.dtb.read_hits 1183 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 1191 # DTB read accesses
system.cpu.dtb.write_hits 900 # DTB write hits
system.cpu.dtb.read_accesses 1190 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 903 # DTB write accesses
system.cpu.dtb.data_hits 2084 # DTB hits
system.cpu.dtb.write_accesses 868 # DTB write accesses
system.cpu.dtb.data_hits 2048 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 2094 # DTB accesses
system.cpu.itb.fetch_hits 908 # ITB hits
system.cpu.dtb.data_accesses 2058 # DTB accesses
system.cpu.itb.fetch_hits 909 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 925 # ITB accesses
system.cpu.itb.fetch_accesses 926 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -218,42 +218,42 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 39684 # number of cpu cycles simulated
system.cpu.numCycles 37540 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.lookups 1606 # Number of BP lookups
system.cpu.branch_predictor.lookups 1605 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 1125 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 713 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 1186 # Number of BTB lookups
system.cpu.branch_predictor.BTBLookups 1185 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 314 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 126 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 26.475548 # BTB Hit Percentage
system.cpu.branch_predictor.BTBHitPct 26.497890 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 464 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 1142 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 5205 # Number of Reads from Int. Register File
system.cpu.branch_predictor.predictedNotTaken 1141 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 5235 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 4567 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 9772 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 9802 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 8 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 2 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 10 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 2961 # Number of Registers Read Through Forwarding Logic
system.cpu.regfile_manager.regForwards 2929 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 2181 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 284 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 368 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 652 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 399 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 62.036156 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 4463 # Number of Instructions Executed.
system.cpu.execution_unit.executions 4462 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 11913 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.threadCycles 11564 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 522 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 32282 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 7402 # Number of cycles cpu stages are processed.
system.cpu.activity 18.652354 # Percentage of cycles cpu is active
system.cpu.timesIdled 496 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 30143 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 7397 # Number of cycles cpu stages are processed.
system.cpu.activity 19.704315 # Percentage of cycles cpu is active
system.cpu.comLoads 1183 # Number of Load instructions committed
system.cpu.comStores 865 # Number of Store instructions committed
system.cpu.comBranches 1050 # Number of Branches instructions committed
@ -265,144 +265,144 @@ system.cpu.committedInsts 6390 # Nu
system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total)
system.cpu.cpi 6.210329 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.cpi 5.874804 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 6.210329 # CPI: Total CPI of All Threads
system.cpu.ipc 0.161022 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.cpi_total 5.874804 # CPI: Total CPI of All Threads
system.cpu.ipc 0.170218 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 0.161022 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 34772 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 4912 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 12.377784 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 35806 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 3878 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 9.772200 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 35512 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 4172 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 10.513053 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 38344 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 1340 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 3.376676 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 35226 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 4458 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 11.233747 # Percentage of cycles stage was utilized (processing insts).
system.cpu.ipc_total 0.170218 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 32631 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 4909 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 13.076718 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 33667 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 3873 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 10.316995 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 33372 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 4168 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 11.102824 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 36235 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 1305 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 3.476292 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 33023 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 4517 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 12.032499 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 142.150123 # Cycle average of tags in use
system.cpu.icache.total_refs 558 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 143.255742 # Cycle average of tags in use
system.cpu.icache.total_refs 556 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1.853821 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 1.847176 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 142.150123 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.069409 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.069409 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 558 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 558 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 558 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 558 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 558 # number of overall hits
system.cpu.icache.overall_hits::total 558 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 350 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 350 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses
system.cpu.icache.overall_misses::total 350 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 17305000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 17305000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 17305000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 17305000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 17305000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 17305000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 908 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 908 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 908 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 908 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 908 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.385463 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.385463 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.385463 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.385463 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.385463 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.385463 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49442.857143 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 49442.857143 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 49442.857143 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 49442.857143 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 49442.857143 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 49442.857143 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.occ_blocks::cpu.inst 143.255742 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.069949 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.069949 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 556 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 556 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 556 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 556 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 556 # number of overall hits
system.cpu.icache.overall_hits::total 556 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 353 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 353 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 353 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 353 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 353 # number of overall misses
system.cpu.icache.overall_misses::total 353 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 17380500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 17380500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 17380500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 17380500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 17380500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 17380500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 909 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 909 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 909 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 909 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 909 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.388339 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.388339 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.388339 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.388339 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.388339 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.388339 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49236.543909 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 49236.543909 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 49236.543909 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 49236.543909 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 49236.543909 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 49236.543909 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 48 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 48 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 48 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 48 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 48 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 51 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 51 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 51 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 51 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 51 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 302 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14791500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 14791500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14791500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 14791500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14791500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 14791500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.332599 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.332599 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.332599 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48978.476821 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48978.476821 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48978.476821 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 48978.476821 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48978.476821 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 48978.476821 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14765000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 14765000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14765000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 14765000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14765000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 14765000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.332233 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.332233 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.332233 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.332233 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.332233 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.332233 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48890.728477 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48890.728477 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48890.728477 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 48890.728477 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48890.728477 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 48890.728477 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 104.047429 # Cycle average of tags in use
system.cpu.dcache.total_refs 1700 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 104.285094 # Cycle average of tags in use
system.cpu.dcache.total_refs 1601 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 10.119048 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 9.529762 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 104.047429 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.025402 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.025402 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::cpu.data 104.285094 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.025460 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits
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system.cpu.dcache.overall_hits::cpu.data 1601 # number of overall hits
system.cpu.dcache.overall_hits::total 1601 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses
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system.cpu.dcache.ReadReq_miss_latency::total 5354000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 11296500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 11296500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 16650500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 16650500 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency::total 16650500 # number of overall miss cycles
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system.cpu.dcache.WriteReq_miss_latency::total 14914000 # number of WriteReq miss cycles
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system.cpu.dcache.demand_miss_latency::total 20268500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 20268500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 20268500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
@ -413,36 +413,36 @@ system.cpu.dcache.overall_accesses::cpu.data 2048
system.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081995 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.081995 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.290173 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.290173 # miss rate for WriteReq accesses
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system.cpu.dcache.demand_miss_rate::total 0.169922 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.169922 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.169922 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55195.876289 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 55195.876289 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45005.976096 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 45005.976096 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 47846.264368 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 47846.264368 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 47846.264368 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 47846.264368 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 2586 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 37 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 69.891892 # average number of cycles each access was blocked
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.404624 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.404624 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.218262 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.218262 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.218262 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.218262 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55201.030928 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 55201.030928 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42611.428571 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 42611.428571 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 45343.400447 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 45343.400447 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 45343.400447 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 45343.400447 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 134 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 134 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 178 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 178 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 180 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 180 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 180 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 180 # number of overall MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 277 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 277 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 279 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 279 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 279 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 279 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
@ -451,14 +451,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168
system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5078500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5078500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3447000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3447000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8525500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 8525500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8525500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 8525500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5079000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5079000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3674000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3674000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8753000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 8753000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8753000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 8753000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
@ -467,26 +467,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031
system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53457.894737 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53457.894737 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47219.178082 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47219.178082 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50747.023810 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 50747.023810 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50747.023810 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 50747.023810 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53463.157895 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53463.157895 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50328.767123 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50328.767123 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52101.190476 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 52101.190476 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52101.190476 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52101.190476 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 199.193487 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 200.317780 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 142.245680 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 56.947807 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.inst 143.356757 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 56.961023 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.004375 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.001738 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.006079 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.006113 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
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system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
@ -504,17 +504,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu
system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses
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system.cpu.l2cache.ReadReq_miss_latency::total 19450000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_latency::total 19424000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3596500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 3596500 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses)
@ -537,17 +537,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997872 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses
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system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48083.056478 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52389.473684 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 49116.161616 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 46157.534247 # average ReadExReq miss latency
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system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48083.056478 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::total 48655.650320 # average overall miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47995.016611 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52394.736842 # average ReadReq miss latency
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system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47995.016611 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51035.714286 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47995.016611 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51035.714286 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 49084.221748 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -567,17 +567,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469
system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
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system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2447596 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10688499 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6239216 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 16927715 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10688499 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6239216 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 16927715 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10662000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3792120 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14454120 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2674096 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2674096 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10662000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6466216 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 17128216 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10662000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6466216 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 17128216 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses
@ -589,17 +589,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35509.963455 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39911.789474 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36565.957071 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33528.712329 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33528.712329 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35509.963455 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37138.190476 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36093.208955 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35509.963455 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37138.190476 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36093.208955 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35421.926910 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39917.052632 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36500.303030 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36631.452055 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36631.452055 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35421.926910 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38489.380952 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36520.716418 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35421.926910 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38489.380952 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36520.716418 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

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@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000019 # Number of seconds simulated
sim_ticks 19373000 # Number of ticks simulated
final_tick 19373000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 18578000 # Number of ticks simulated
final_tick 18578000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 54522 # Simulator instruction rate (inst/s)
host_op_rate 54510 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 181593348 # Simulator tick rate (ticks/s)
host_mem_usage 216696 # Number of bytes of host memory used
host_seconds 0.11 # Real time elapsed on the host
host_inst_rate 97793 # Simulator instruction rate (inst/s)
host_op_rate 97754 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 312246493 # Simulator tick rate (ticks/s)
host_mem_usage 216964 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host
sim_insts 5814 # Number of instructions simulated
sim_ops 5814 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 20288 # Nu
system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
system.physmem.num_reads::total 455 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1047230682 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 455892221 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1503122903 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1047230682 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1047230682 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1047230682 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 455892221 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1503122903 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 1092044354 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 475401012 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1567445365 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1092044354 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1092044354 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1092044354 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 475401012 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1567445365 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 455 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 455 # Reqs generatd by CPU via cache - shady
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 19298000 # Total gap between requests
system.physmem.totGap 18503000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
@ -98,9 +98,9 @@ system.physmem.neitherpktsize::5 0 # ca
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 311 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 114 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::0 292 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 131 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 24 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 2404453 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 12694453 # Sum of mem lat for all requests
system.physmem.totQLat 2353954 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 12657954 # Sum of mem lat for all requests
system.physmem.totBusLat 1820000 # Total cycles spent in databus access
system.physmem.totBankLat 8470000 # Total cycles spent in bank access
system.physmem.avgQLat 5284.51 # Average queueing delay per request
system.physmem.avgBankLat 18615.38 # Average bank access latency per request
system.physmem.totBankLat 8484000 # Total cycles spent in bank access
system.physmem.avgQLat 5173.53 # Average queueing delay per request
system.physmem.avgBankLat 18646.15 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 27899.90 # Average memory access latency
system.physmem.avgRdBW 1503.12 # Average achieved read bandwidth in MB/s
system.physmem.avgMemAccLat 27819.68 # Average memory access latency
system.physmem.avgRdBW 1567.45 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 1503.12 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedRdBW 1567.45 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 9.39 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.66 # Average read queue length over time
system.physmem.busUtil 9.80 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.68 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
system.physmem.readRowHits 357 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 78.46 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 42413.19 # Average gap between requests
system.physmem.avgGap 40665.93 # Average gap between requests
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
@ -204,7 +204,7 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 8 # Number of system calls
system.cpu.numCycles 38747 # number of cpu cycles simulated
system.cpu.numCycles 37157 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.lookups 1146 # Number of BP lookups
@ -217,13 +217,13 @@ system.cpu.branch_predictor.RASInCorrect 32 # Nu
system.cpu.branch_predictor.BTBHitPct 34.843206 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 393 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 753 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 5096 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileReads 5127 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 3396 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 8492 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 8523 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 3 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 1 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 4 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 1320 # Number of Registers Read Through Forwarding Logic
system.cpu.regfile_manager.regForwards 1290 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 2235 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 260 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 336 # Number of Branches Incorrectly Predicted As Not Taken).
@ -234,12 +234,12 @@ system.cpu.execution_unit.executions 3144 # Nu
system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 9675 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.threadCycles 9465 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 483 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 33362 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 5385 # Number of cycles cpu stages are processed.
system.cpu.activity 13.897850 # Percentage of cycles cpu is active
system.cpu.timesIdled 477 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 31782 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 5375 # Number of cycles cpu stages are processed.
system.cpu.activity 14.465646 # Percentage of cycles cpu is active
system.cpu.comLoads 1163 # Number of Load instructions committed
system.cpu.comStores 925 # Number of Store instructions committed
system.cpu.comBranches 915 # Number of Branches instructions committed
@ -251,144 +251,144 @@ system.cpu.committedInsts 5814 # Nu
system.cpu.committedOps 5814 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 5814 # Number of Instructions committed (Total)
system.cpu.cpi 6.664431 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.cpi 6.390953 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 6.664431 # CPI: Total CPI of All Threads
system.cpu.ipc 0.150050 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.cpi_total 6.390953 # CPI: Total CPI of All Threads
system.cpu.ipc 0.156471 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 0.150050 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 35122 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 3625 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 9.355563 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 35925 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 2822 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 7.283145 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 35963 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 2784 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 7.185072 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 37505 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 1242 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 3.205409 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 35843 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 2904 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 7.494774 # Percentage of cycles stage was utilized (processing insts).
system.cpu.ipc_total 0.156471 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 33517 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 3640 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 9.796270 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 34336 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 2821 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 7.592109 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 34391 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 2766 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 7.444089 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 35931 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 1226 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 3.299513 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 34254 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 2903 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 7.812794 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 13 # number of replacements
system.cpu.icache.tagsinuse 148.105671 # Cycle average of tags in use
system.cpu.icache.tagsinuse 149.857420 # Cycle average of tags in use
system.cpu.icache.total_refs 410 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1.285266 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 148.105671 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.072317 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.072317 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::cpu.inst 149.857420 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.073173 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.073173 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 410 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 410 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 410 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 410 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 410 # number of overall hits
system.cpu.icache.overall_hits::total 410 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 344 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 344 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 344 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 344 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 344 # number of overall misses
system.cpu.icache.overall_misses::total 344 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 18000000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 18000000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 18000000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 18000000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 18000000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 18000000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 754 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 754 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 754 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 754 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 754 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 754 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.456233 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.456233 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.456233 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.456233 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.456233 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.456233 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52325.581395 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 52325.581395 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 52325.581395 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 52325.581395 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 52325.581395 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 52325.581395 # average overall miss latency
system.cpu.icache.ReadReq_misses::cpu.inst 346 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 346 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 346 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 346 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 346 # number of overall misses
system.cpu.icache.overall_misses::total 346 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 18065500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 18065500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 18065500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 18065500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 18065500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 18065500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 756 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 756 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::total 756 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::total 756 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::total 0.457672 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::total 0.457672 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.457672 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.457672 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52212.427746 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 52212.427746 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 52212.427746 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 52212.427746 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 52212.427746 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 52212.427746 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 34 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.ReadReq_mshr_hits::total 25 # number of ReadReq MSHR hits
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system.cpu.icache.demand_mshr_hits::total 25 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 25 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 25 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_hits::cpu.inst 27 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 27 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 319 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 319 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 319 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16448000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 16448000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16448000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 16448000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16448000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 16448000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.423077 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.423077 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.423077 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51561.128527 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51561.128527 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51561.128527 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 51561.128527 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51561.128527 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 51561.128527 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16466000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 16466000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16466000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 16466000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16466000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 16466000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.421958 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.421958 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.421958 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.421958 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.421958 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.421958 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51617.554859 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51617.554859 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51617.554859 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 51617.554859 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51617.554859 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 51617.554859 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 89.430963 # Cycle average of tags in use
system.cpu.dcache.total_refs 1834 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 89.860913 # Cycle average of tags in use
system.cpu.dcache.total_refs 1644 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 13.289855 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 11.913043 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 89.430963 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.021834 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits::total 1072 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::total 762 # number of WriteReq hits
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system.cpu.dcache.overall_hits::total 1834 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 91 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 91 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 163 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 163 # number of WriteReq misses
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system.cpu.dcache.demand_misses::total 254 # number of demand (read+write) misses
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system.cpu.dcache.ReadReq_miss_latency::total 5497500 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::total 8188000 # number of WriteReq miss cycles
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system.cpu.dcache.demand_miss_latency::total 13685500 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency::total 13685500 # number of overall miss cycles
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system.cpu.dcache.occ_percent::cpu.data 0.021939 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.021939 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1070 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1070 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::total 574 # number of WriteReq hits
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system.cpu.dcache.overall_hits::total 1644 # number of overall hits
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system.cpu.dcache.ReadReq_misses::total 93 # number of ReadReq misses
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system.cpu.dcache.demand_misses::total 444 # number of demand (read+write) misses
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system.cpu.dcache.overall_misses::total 444 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency::total 5589000 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::total 14658500 # number of WriteReq miss cycles
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system.cpu.dcache.demand_miss_latency::total 20247500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 20247500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 20247500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
@ -397,38 +397,38 @@ system.cpu.dcache.demand_accesses::cpu.data 2088 #
system.cpu.dcache.demand_accesses::total 2088 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2088 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2088 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.078246 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.078246 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.176216 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.176216 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.121648 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.121648 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.121648 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.121648 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60412.087912 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 60412.087912 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 50233.128834 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 50233.128834 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 53879.921260 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 53879.921260 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 53879.921260 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 53879.921260 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 2069 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 23 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 89.956522 # average number of cycles each access was blocked
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079966 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.079966 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.379459 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.379459 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.212644 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.212644 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.212644 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.212644 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60096.774194 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 60096.774194 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41762.108262 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 41762.108262 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 45602.477477 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 45602.477477 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 45602.477477 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 45602.477477 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 99 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 99 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 112 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 112 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 116 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 116 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 116 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 116 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 300 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 300 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 306 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 306 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 306 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 306 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses
@ -437,14 +437,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138
system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5201000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5201000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2605000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2605000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7806000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7806000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7806000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7806000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5155000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5155000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2618500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2618500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7773500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7773500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7773500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7773500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
@ -453,26 +453,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092
system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59781.609195 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59781.609195 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51078.431373 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51078.431373 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56565.217391 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 56565.217391 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56565.217391 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 56565.217391 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59252.873563 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59252.873563 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51343.137255 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51343.137255 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56329.710145 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 56329.710145 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56329.710145 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 56329.710145 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 205.347343 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 207.494837 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 149.740781 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 55.606562 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.004570 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.001697 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.006267 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::cpu.inst 151.607312 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 55.887525 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.004627 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.001706 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.006332 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
@ -490,17 +490,17 @@ system.cpu.l2cache.demand_misses::total 455 # nu
system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
system.cpu.l2cache.overall_misses::total 455 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16102500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5107500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 21210000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2551000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 2551000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 16102500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 7658500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 23761000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 16102500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 7658500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 23761000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16120500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5061500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 21182000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2564500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 2564500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 16120500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 7626000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 23746500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 16120500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 7626000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 23746500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses)
@ -523,17 +523,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995624 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50796.529968 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58706.896552 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50019.607843 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50019.607843 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50796.529968 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55496.376812 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52221.978022 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50796.529968 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55496.376812 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52221.978022 # average overall miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50853.312303 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58178.160920 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52430.693069 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50284.313725 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50284.313725 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50853.312303 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55260.869565 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52190.109890 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50853.312303 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55260.869565 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52190.109890 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -553,17 +553,17 @@ system.cpu.l2cache.demand_mshr_misses::total 455
system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12097521 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4026597 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16124118 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1915572 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1915572 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12097521 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5942169 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 18039690 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12097521 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5942169 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 18039690 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12117017 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3982094 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16099111 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1929572 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1929572 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12117017 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5911666 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 18028683 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12117017 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5911666 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 18028683 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses
@ -575,17 +575,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38162.526814 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46282.724138 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39911.183168 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37560.235294 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37560.235294 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38162.526814 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43059.195652 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39647.670330 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38162.526814 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43059.195652 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39647.670330 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38224.028391 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45771.195402 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39849.284653 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37834.745098 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37834.745098 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38224.028391 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42838.159420 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39623.479121 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38224.028391 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42838.159420 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39623.479121 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

878
tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
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977
tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
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File diff suppressed because it is too large Load diff

508
tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
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@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000018 # Number of seconds simulated
sim_ticks 17991500 # Number of ticks simulated
final_tick 17991500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.000016 # Number of seconds simulated
sim_ticks 16282500 # Number of ticks simulated
final_tick 16282500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 44971 # Simulator instruction rate (inst/s)
host_op_rate 44961 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 151823718 # Simulator tick rate (ticks/s)
host_mem_usage 222708 # Number of bytes of host memory used
host_inst_rate 46082 # Simulator instruction rate (inst/s)
host_op_rate 46072 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 140796560 # Simulator tick rate (ticks/s)
host_mem_usage 222960 # Number of bytes of host memory used
host_seconds 0.12 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 18496 # Nu
system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
system.physmem.num_reads::total 423 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1028041019 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 476669538 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1504710558 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1028041019 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1028041019 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1028041019 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 476669538 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1504710558 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 1135943498 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 526700445 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1662643943 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1135943498 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1135943498 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1135943498 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 526700445 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1662643943 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 423 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 423 # Reqs generatd by CPU via cache - shady
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 17940000 # Total gap between requests
system.physmem.totGap 16231000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 281 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 113 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 25 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::0 254 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 122 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 36 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
@ -164,48 +164,48 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 1964422 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 11356422 # Sum of mem lat for all requests
system.physmem.totQLat 2301921 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 11301921 # Sum of mem lat for all requests
system.physmem.totBusLat 1692000 # Total cycles spent in databus access
system.physmem.totBankLat 7700000 # Total cycles spent in bank access
system.physmem.avgQLat 4644.02 # Average queueing delay per request
system.physmem.avgBankLat 18203.31 # Average bank access latency per request
system.physmem.totBankLat 7308000 # Total cycles spent in bank access
system.physmem.avgQLat 5441.89 # Average queueing delay per request
system.physmem.avgBankLat 17276.60 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 26847.33 # Average memory access latency
system.physmem.avgRdBW 1504.71 # Average achieved read bandwidth in MB/s
system.physmem.avgMemAccLat 26718.49 # Average memory access latency
system.physmem.avgRdBW 1662.64 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 1504.71 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedRdBW 1662.64 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 9.40 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.63 # Average read queue length over time
system.physmem.busUtil 10.39 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.69 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
system.physmem.readRowHits 336 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 79.43 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 42411.35 # Average gap between requests
system.physmem.avgGap 38371.16 # Average gap between requests
system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.numCycles 35984 # number of cpu cycles simulated
system.cpu.numCycles 32566 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.lookups 1634 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 1036 # Number of conditional branches predicted
system.cpu.branch_predictor.lookups 1630 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 1034 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 901 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 1169 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 438 # Number of BTB hits
system.cpu.branch_predictor.BTBLookups 1165 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 436 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 67 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 4 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 37.467921 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 505 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 1129 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 5626 # Number of Reads from Int. Register File
system.cpu.branch_predictor.BTBHitPct 37.424893 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 503 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 1127 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 5631 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 3988 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 9614 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 9619 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 1682 # Number of Registers Read Through Forwarding Logic
system.cpu.regfile_manager.regForwards 1675 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 1483 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 334 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 504 # Number of Branches Incorrectly Predicted As Not Taken).
@ -216,12 +216,12 @@ system.cpu.execution_unit.executions 3966 # Nu
system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 9941 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.threadCycles 9640 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 470 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 29760 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 6224 # Number of cycles cpu stages are processed.
system.cpu.activity 17.296576 # Percentage of cycles cpu is active
system.cpu.timesIdled 478 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 26364 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 6202 # Number of cycles cpu stages are processed.
system.cpu.activity 19.044402 # Percentage of cycles cpu is active
system.cpu.comLoads 715 # Number of Load instructions committed
system.cpu.comStores 673 # Number of Store instructions committed
system.cpu.comBranches 1115 # Number of Branches instructions committed
@ -233,144 +233,144 @@ system.cpu.committedInsts 5327 # Nu
system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total)
system.cpu.cpi 6.755022 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.cpi 6.113385 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 6.755022 # CPI: Total CPI of All Threads
system.cpu.ipc 0.148038 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.cpi_total 6.113385 # CPI: Total CPI of All Threads
system.cpu.ipc 0.163576 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 0.148038 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 31416 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 4568 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 12.694531 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 32782 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 3202 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 8.898399 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 32940 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 3044 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 8.459315 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 35002 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 982 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 2.728991 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 32815 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 3169 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 8.806692 # Percentage of cycles stage was utilized (processing insts).
system.cpu.ipc_total 0.163576 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 28007 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 4559 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 13.999263 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 29377 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 3189 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 9.792422 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 29532 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 3034 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 9.316465 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 31591 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 975 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 2.993920 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 29408 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 3158 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 9.697230 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 138.057869 # Cycle average of tags in use
system.cpu.icache.total_refs 829 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 143.411463 # Cycle average of tags in use
system.cpu.icache.total_refs 814 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 2.848797 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 2.797251 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 138.057869 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.067411 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.067411 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 829 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 829 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 829 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 829 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 829 # number of overall hits
system.cpu.icache.overall_hits::total 829 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 348 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 348 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 348 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 348 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 348 # number of overall misses
system.cpu.icache.overall_misses::total 348 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 18017500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 18017500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 18017500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 18017500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 18017500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 18017500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1177 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1177 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1177 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1177 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1177 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1177 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.295667 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.295667 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.295667 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.295667 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.295667 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.295667 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51774.425287 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 51774.425287 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 51774.425287 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 51774.425287 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 51774.425287 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 51774.425287 # average overall miss latency
system.cpu.icache.occ_blocks::cpu.inst 143.411463 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.070025 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.070025 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 814 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 814 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 814 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 814 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 814 # number of overall hits
system.cpu.icache.overall_hits::total 814 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses
system.cpu.icache.overall_misses::total 364 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 18418500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 18418500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 18418500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 18418500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 18418500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 18418500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1178 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1178 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1178 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1178 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1178 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1178 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.308998 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.308998 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.308998 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.308998 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.308998 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.308998 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50600.274725 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 50600.274725 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 50600.274725 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 50600.274725 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 50600.274725 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 50600.274725 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 148 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 49.333333 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 57 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 57 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 57 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 57 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 57 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 73 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 73 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 73 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15219500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 15219500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15219500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 15219500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15219500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 15219500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.247239 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.247239 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.247239 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.247239 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.247239 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.247239 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52300.687285 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52300.687285 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52300.687285 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 52300.687285 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52300.687285 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52300.687285 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15194000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 15194000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15194000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 15194000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15194000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 15194000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.247029 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.247029 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.247029 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.247029 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.247029 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.247029 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52213.058419 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52213.058419 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52213.058419 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 52213.058419 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52213.058419 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52213.058419 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 83.298060 # Cycle average of tags in use
system.cpu.dcache.total_refs 1045 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 85.214129 # Cycle average of tags in use
system.cpu.dcache.total_refs 914 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 7.740741 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 6.770370 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 83.298060 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.020336 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.020336 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::cpu.data 85.214129 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.020804 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.020804 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 391 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 391 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 1045 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1045 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1045 # number of overall hits
system.cpu.dcache.overall_hits::total 1045 # number of overall hits
system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 260 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 914 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 914 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 914 # number of overall hits
system.cpu.dcache.overall_hits::total 914 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 61 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 282 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 282 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 343 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 343 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 343 # number of overall misses
system.cpu.dcache.overall_misses::total 343 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3323500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 3323500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 13337500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 13337500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 16661000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 16661000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 16661000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 16661000 # number of overall miss cycles
system.cpu.dcache.WriteReq_misses::cpu.data 413 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 413 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 474 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses
system.cpu.dcache.overall_misses::total 474 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3347500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 3347500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 19185000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 19185000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 22532500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 22532500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 22532500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 22532500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
@ -381,36 +381,36 @@ system.cpu.dcache.overall_accesses::cpu.data 1388
system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085315 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.085315 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.419019 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.419019 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.247118 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.247118 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.247118 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.247118 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54483.606557 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 54483.606557 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47296.099291 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 47296.099291 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 48574.344023 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 48574.344023 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 48574.344023 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 48574.344023 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 3752 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 83.377778 # average number of cycles each access was blocked
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.613670 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.613670 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54877.049180 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 54877.049180 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46452.784504 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 46452.784504 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 47536.919831 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 47536.919831 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 47536.919831 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 47536.919831 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 405 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 32 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.656250 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 201 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 201 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 208 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 208 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 208 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 208 # number of overall MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 332 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 332 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 339 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 339 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 339 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 339 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses
@ -419,14 +419,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135
system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3959500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3959500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6874500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 6874500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6874500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 6874500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2939000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2939000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4153500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4153500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7092500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7092500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7092500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7092500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
@ -435,26 +435,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262
system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53981.481481 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53981.481481 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48882.716049 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48882.716049 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50922.222222 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 50922.222222 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50922.222222 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 50922.222222 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54425.925926 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54425.925926 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51277.777778 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51277.777778 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52537.037037 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 52537.037037 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52537.037037 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52537.037037 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 163.809669 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 169.991473 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 137.551022 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 26.258647 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.004198 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.000801 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.004999 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::cpu.inst 142.874602 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 27.116871 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.004360 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.000828 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.005188 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits
@ -475,17 +475,17 @@ system.cpu.l2cache.demand_misses::total 423 # nu
system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses
system.cpu.l2cache.overall_misses::total 423 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14901000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2848500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 17749500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3876000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 3876000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 14901000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 6724500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 21625500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 14901000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 6724500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 21625500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14875500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2872500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 17748000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4070000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 4070000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 14875500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 6942500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 21818000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 14875500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 6942500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 21818000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses)
@ -508,17 +508,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.992958 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51560.553633 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53745.283019 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 51899.122807 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 47851.851852 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 47851.851852 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51560.553633 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50182.835821 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 51124.113475 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51560.553633 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50182.835821 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 51124.113475 # average overall miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51472.318339 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54198.113208 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 51894.736842 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50246.913580 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50246.913580 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51472.318339 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51809.701493 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 51579.196217 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51472.318339 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51809.701493 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 51579.196217 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -538,17 +538,17 @@ system.cpu.l2cache.demand_mshr_misses::total 423
system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11259441 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2182574 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13442015 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2846130 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2846130 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11259441 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5028704 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 16288145 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11259441 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5028704 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 16288145 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11235436 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2207572 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13443008 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3066568 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3066568 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11235436 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5274140 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 16509576 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11235436 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5274140 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 16509576 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses
@ -560,17 +560,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38960.003460 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41180.641509 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39304.137427 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35137.407407 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35137.407407 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38960.003460 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37527.641791 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38506.252955 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38960.003460 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37527.641791 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38506.252955 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38876.941176 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41652.301887 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39307.040936 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37858.864198 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37858.864198 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38876.941176 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39359.253731 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39029.730496 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38876.941176 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39359.253731 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39029.730496 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

861
tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
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tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
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tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
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@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000024 # Number of seconds simulated
sim_ticks 24110500 # Number of ticks simulated
final_tick 24110500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.000023 # Number of seconds simulated
sim_ticks 22522500 # Number of ticks simulated
final_tick 22522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 94813 # Simulator instruction rate (inst/s)
host_op_rate 94805 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 150747979 # Simulator tick rate (ticks/s)
host_mem_usage 222632 # Number of bytes of host memory used
host_seconds 0.16 # Real time elapsed on the host
host_inst_rate 65265 # Simulator instruction rate (inst/s)
host_op_rate 65259 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 96930117 # Simulator tick rate (ticks/s)
host_mem_usage 222888 # Number of bytes of host memory used
host_seconds 0.23 # Real time elapsed on the host
sim_insts 15162 # Number of instructions simulated
sim_ops 15162 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19072 # Nu
system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
system.physmem.num_reads::total 436 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 791024657 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 366313432 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1157338089 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 791024657 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 791024657 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 791024657 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 366313432 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1157338089 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 846797647 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 392141192 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1238938839 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 846797647 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 846797647 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 846797647 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 392141192 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1238938839 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 436 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 436 # Reqs generatd by CPU via cache - shady
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 24077000 # Total gap between requests
system.physmem.totGap 22489000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 305 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 107 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::0 279 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 111 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 35 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
@ -164,49 +164,49 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 1670434 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 11016434 # Sum of mem lat for all requests
system.physmem.totQLat 1783436 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 10779436 # Sum of mem lat for all requests
system.physmem.totBusLat 1744000 # Total cycles spent in databus access
system.physmem.totBankLat 7602000 # Total cycles spent in bank access
system.physmem.avgQLat 3831.27 # Average queueing delay per request
system.physmem.avgBankLat 17435.78 # Average bank access latency per request
system.physmem.totBankLat 7252000 # Total cycles spent in bank access
system.physmem.avgQLat 4090.45 # Average queueing delay per request
system.physmem.avgBankLat 16633.03 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 25267.05 # Average memory access latency
system.physmem.avgRdBW 1157.34 # Average achieved read bandwidth in MB/s
system.physmem.avgMemAccLat 24723.48 # Average memory access latency
system.physmem.avgRdBW 1238.94 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 1157.34 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedRdBW 1238.94 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 7.23 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.46 # Average read queue length over time
system.physmem.busUtil 7.74 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.48 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
system.physmem.readRowHits 359 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.34 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 55222.48 # Average gap between requests
system.physmem.avgGap 51580.28 # Average gap between requests
system.cpu.workload.num_syscalls 18 # Number of system calls
system.cpu.numCycles 48222 # number of cpu cycles simulated
system.cpu.numCycles 45046 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.lookups 5021 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 3412 # Number of conditional branches predicted
system.cpu.branch_predictor.lookups 5017 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 3408 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 2378 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 3518 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 2142 # Number of BTB hits
system.cpu.branch_predictor.BTBLookups 3514 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 2140 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 176 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 5 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 60.886868 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 2318 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 2703 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 14367 # Number of Reads from Int. Register File
system.cpu.branch_predictor.BTBHitPct 60.899260 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 2316 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 2701 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 14466 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 11099 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 25466 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 25565 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 5027 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 3931 # Number of Address Generations
system.cpu.regfile_manager.regForwards 4899 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 3932 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 1367 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 948 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 2315 # Number of Branches Incorrectly Predicted
@ -216,12 +216,12 @@ system.cpu.execution_unit.executions 11058 # Nu
system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 22133 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.threadCycles 21840 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 497 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 30866 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 17356 # Number of cycles cpu stages are processed.
system.cpu.activity 35.991871 # Percentage of cycles cpu is active
system.cpu.timesIdled 501 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 27681 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 17365 # Number of cycles cpu stages are processed.
system.cpu.activity 38.549483 # Percentage of cycles cpu is active
system.cpu.comLoads 2225 # Number of Load instructions committed
system.cpu.comStores 1448 # Number of Store instructions committed
system.cpu.comBranches 3358 # Number of Branches instructions committed
@ -233,146 +233,146 @@ system.cpu.committedInsts 15162 # Nu
system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total)
system.cpu.cpi 3.180451 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.cpi 2.970980 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 3.180451 # CPI: Total CPI of All Threads
system.cpu.ipc 0.314421 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.cpi_total 2.970980 # CPI: Total CPI of All Threads
system.cpu.ipc 0.336589 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 0.314421 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 35090 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 13132 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 27.232384 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 39034 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 9188 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 19.053544 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 39406 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 8816 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 18.282112 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 45338 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 2884 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 5.980673 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 38904 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 9318 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 19.323131 # Percentage of cycles stage was utilized (processing insts).
system.cpu.ipc_total 0.336589 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 31894 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 13152 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 29.196821 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 35835 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 9211 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 20.447987 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 36237 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 8809 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 19.555565 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 42168 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 2878 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 6.389025 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 35732 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 9314 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 20.676642 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 166.100833 # Cycle average of tags in use
system.cpu.icache.total_refs 2586 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 171.605866 # Cycle average of tags in use
system.cpu.icache.total_refs 2584 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 8.648829 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 8.642140 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 166.100833 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.081104 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.081104 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 2586 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 2586 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 2586 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 2586 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 2586 # number of overall hits
system.cpu.icache.overall_hits::total 2586 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 369 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 369 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 369 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 369 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 369 # number of overall misses
system.cpu.icache.overall_misses::total 369 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 18278500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 18278500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 18278500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 18278500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 18278500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 18278500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 2955 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 2955 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 2955 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 2955 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 2955 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 2955 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124873 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.124873 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.124873 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.124873 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.124873 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.124873 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49535.230352 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 49535.230352 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 49535.230352 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 49535.230352 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 49535.230352 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 49535.230352 # average overall miss latency
system.cpu.icache.occ_blocks::cpu.inst 171.605866 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.083792 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.083792 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 2584 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 2584 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 2584 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 2584 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 2584 # number of overall hits
system.cpu.icache.overall_hits::total 2584 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 372 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 372 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 372 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 372 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 372 # number of overall misses
system.cpu.icache.overall_misses::total 372 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 18064500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 18064500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 18064500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 18064500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 18064500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 18064500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 2956 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 2956 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 2956 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 2956 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 2956 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 2956 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.125846 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.125846 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.125846 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.125846 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.125846 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.125846 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48560.483871 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 48560.483871 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 48560.483871 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 48560.483871 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 48560.483871 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 48560.483871 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 85 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 42.500000 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 68 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 71 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 71 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 71 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 71 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 301 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14783500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 14783500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14783500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 14783500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14783500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 14783500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.101861 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.101861 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.101861 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.101861 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.101861 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.101861 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49114.617940 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49114.617940 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49114.617940 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 49114.617940 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49114.617940 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 49114.617940 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14600500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 14600500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14600500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 14600500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14600500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 14600500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.101827 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.101827 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.101827 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.101827 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.101827 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.101827 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48506.644518 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48506.644518 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48506.644518 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 48506.644518 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48506.644518 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 48506.644518 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 97.064476 # Cycle average of tags in use
system.cpu.dcache.total_refs 3314 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 99.150895 # Cycle average of tags in use
system.cpu.dcache.total_refs 3193 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 24.014493 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 23.137681 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 97.064476 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.023697 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.023697 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::cpu.data 99.150895 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.024207 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 1020 # number of WriteReq hits
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system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
system.cpu.dcache.demand_hits::cpu.data 3308 # number of demand (read+write) hits
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system.cpu.dcache.overall_hits::cpu.data 3308 # number of overall hits
system.cpu.dcache.overall_hits::total 3308 # number of overall hits
system.cpu.dcache.demand_hits::cpu.data 3187 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 3187 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 3187 # number of overall hits
system.cpu.dcache.overall_hits::total 3187 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 58 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 58 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 301 # number of WriteReq misses
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system.cpu.dcache.ReadReq_miss_latency::cpu.data 3241000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 3241000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 14317500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 14317500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 17558500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 17558500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 17558500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 17558500 # number of overall miss cycles
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system.cpu.dcache.demand_misses::total 480 # number of demand (read+write) misses
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system.cpu.dcache.ReadReq_miss_latency::cpu.data 3300500 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::cpu.data 19262500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 19262500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 22563000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 22563000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 22563000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 22563000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
@ -385,36 +385,36 @@ system.cpu.dcache.overall_accesses::cpu.data 3667
system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_miss_rate::total 0.026067 # miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_miss_rate::total 0.208738 # miss rate for WriteReq accesses
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system.cpu.dcache.demand_miss_rate::total 0.097900 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.097900 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.097900 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55879.310345 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 55879.310345 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47566.445183 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 47566.445183 # average WriteReq miss latency
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system.cpu.dcache.demand_avg_miss_latency::total 48909.470752 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 48909.470752 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 48909.470752 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 3701 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 82.244444 # average number of cycles each access was blocked
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.292649 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.292649 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.130897 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.130897 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.130897 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.130897 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56905.172414 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 56905.172414 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45645.734597 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 45645.734597 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 47006.250000 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 47006.250000 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 47006.250000 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 47006.250000 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 680 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 34 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 20 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 216 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 216 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 221 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 221 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 221 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 221 # number of overall MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 337 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 337 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 342 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 342 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 342 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 342 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses
@ -423,14 +423,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138
system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2840500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2840500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4329000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4329000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7169500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7169500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7169500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7169500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2900000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2900000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4513000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4513000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7413000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7413000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7413000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7413000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
@ -439,26 +439,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633
system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53594.339623 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53594.339623 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50929.411765 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50929.411765 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51952.898551 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51952.898551 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51952.898551 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51952.898551 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54716.981132 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54716.981132 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53094.117647 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53094.117647 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53717.391304 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53717.391304 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53717.391304 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53717.391304 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 196.769171 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 202.986818 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 351 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.005698 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 165.497362 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 31.271809 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_percent::cpu.data 0.000954 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.006005 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::cpu.inst 170.969481 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 32.017336 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.005218 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.000977 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
@ -476,17 +476,17 @@ system.cpu.l2cache.demand_misses::total 437 # nu
system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
system.cpu.l2cache.overall_misses::total 437 # number of overall misses
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system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2786000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 17286500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4241500 # number of ReadExReq miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.inst 14500500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 7027500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 21528000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14317500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2845500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 17163000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4425000 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses)
@ -509,17 +509,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995444 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48496.655518 # average ReadReq miss latency
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system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48496.655518 # average overall miss latency
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system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53688.679245 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 48758.522727 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52058.823529 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52058.823529 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47884.615385 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52684.782609 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47884.615385 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52684.782609 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 49400.457666 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -539,17 +539,17 @@ system.cpu.l2cache.demand_mshr_misses::total 437
system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses
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system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3166632 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3166632 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10728482 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5289200 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 16017682 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10728482 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5289200 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 16017682 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10547482 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2181568 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12729050 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3382064 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3382064 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10547482 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5563632 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 16111114 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10547482 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5563632 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 16111114 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses
@ -561,17 +561,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35881.210702 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40048.452830 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36508.664773 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37254.494118 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37254.494118 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35881.210702 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38327.536232 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36653.734554 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35881.210702 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38327.536232 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36653.734554 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35275.859532 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41161.660377 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36162.073864 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39788.988235 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39788.988235 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35275.859532 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40316.173913 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36867.537757 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35275.859532 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40316.173913 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36867.537757 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

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tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
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730
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
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@ -1,730 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000088 # Number of seconds simulated
sim_ticks 87707000 # Number of ticks simulated
final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1518076 # Simulator instruction rate (inst/s)
host_op_rate 1518015 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 196560583 # Simulator tick rate (ticks/s)
host_mem_usage 1157868 # Number of bytes of host memory used
host_seconds 0.45 # Real time elapsed on the host
sim_insts 677327 # Number of instructions simulated
sim_ops 677327 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 3968 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory
system.physmem.bytes_read::total 35776 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 18048 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 3968 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst 128 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 22272 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu0.inst 282 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 62 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory
system.physmem.num_reads::total 559 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu0.inst 205776050 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 120400880 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 45241543 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 14594046 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 1459405 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 9486130 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst 1459405 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data 9486130 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 407903588 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 205776050 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 45241543 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 1459405 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst 1459405 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 253936402 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 205776050 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 120400880 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 45241543 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 14594046 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 1459405 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 9486130 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst 1459405 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data 9486130 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 407903588 # Total bandwidth to/from this memory (bytes/s)
system.cpu0.workload.num_syscalls 89 # Number of system calls
system.cpu0.numCycles 175415 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 175326 # Number of instructions committed
system.cpu0.committedOps 175326 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 120376 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu0.num_func_calls 390 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 28824 # number of instructions that are conditional controls
system.cpu0.num_int_insts 120376 # number of integer instructions
system.cpu0.num_fp_insts 0 # number of float instructions
system.cpu0.num_int_register_reads 349286 # number of times the integer registers were read
system.cpu0.num_int_register_writes 121983 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu0.num_mem_refs 82397 # number of memory refs
system.cpu0.num_load_insts 54591 # Number of load instructions
system.cpu0.num_store_insts 27806 # Number of store instructions
system.cpu0.num_idle_cycles 0 # Number of idle cycles
system.cpu0.num_busy_cycles 175415 # Number of busy cycles
system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0 # Percentage of idle cycles
system.cpu0.icache.replacements 215 # number of replacements
system.cpu0.icache.tagsinuse 222.772698 # Cycle average of tags in use
system.cpu0.icache.total_refs 174921 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 374.563169 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst 222.772698 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.435103 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 174921 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 174921 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 174921 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 174921 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 174921 # number of overall hits
system.cpu0.icache.overall_hits::total 174921 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses
system.cpu0.icache.overall_misses::total 467 # number of overall misses
system.cpu0.icache.ReadReq_accesses::cpu0.inst 175388 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 175388 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 175388 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 175388 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 175388 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 175388 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002663 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.002663 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002663 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.002663 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002663 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.002663 # miss rate for overall accesses
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.replacements 2 # number of replacements
system.cpu0.dcache.tagsinuse 150.745494 # Cycle average of tags in use
system.cpu0.dcache.total_refs 81883 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 490.317365 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data 150.745494 # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data 0.294425 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total 0.294425 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 54430 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 54430 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 27578 # number of WriteReq hits
system.cpu0.dcache.SwapReq_hits::cpu0.data 15 # number of SwapReq hits
system.cpu0.dcache.SwapReq_hits::total 15 # number of SwapReq hits
system.cpu0.dcache.demand_hits::cpu0.data 82008 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 82008 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 82008 # number of overall hits
system.cpu0.dcache.overall_hits::total 82008 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 151 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 151 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 177 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 177 # number of WriteReq misses
system.cpu0.dcache.SwapReq_misses::cpu0.data 27 # number of SwapReq misses
system.cpu0.dcache.SwapReq_misses::total 27 # number of SwapReq misses
system.cpu0.dcache.demand_misses::cpu0.data 328 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 328 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 328 # number of overall misses
system.cpu0.dcache.overall_misses::total 328 # number of overall misses
system.cpu0.dcache.ReadReq_accesses::cpu0.data 54581 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 54581 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 27755 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 27755 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 82336 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 82336 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 82336 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 82336 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002767 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.002767 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006377 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.006377 # miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.642857 # miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_miss_rate::total 0.642857 # miss rate for SwapReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.003984 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.003984 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.003984 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.003984 # miss rate for overall accesses
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
system.cpu0.dcache.writebacks::total 1 # number of writebacks
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.numCycles 173295 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 167398 # Number of instructions committed
system.cpu1.committedOps 167398 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 109926 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu1.num_func_calls 633 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 32743 # number of instructions that are conditional controls
system.cpu1.num_int_insts 109926 # number of integer instructions
system.cpu1.num_fp_insts 0 # number of float instructions
system.cpu1.num_int_register_reads 270038 # number of times the integer registers were read
system.cpu1.num_int_register_writes 100721 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu1.num_mem_refs 53394 # number of memory refs
system.cpu1.num_load_insts 40652 # Number of load instructions
system.cpu1.num_store_insts 12742 # Number of store instructions
system.cpu1.num_idle_cycles 7873.724337 # Number of idle cycles
system.cpu1.num_busy_cycles 165421.275663 # Number of busy cycles
system.cpu1.not_idle_fraction 0.954565 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.045435 # Percentage of idle cycles
system.cpu1.icache.replacements 278 # number of replacements
system.cpu1.icache.tagsinuse 76.751702 # Cycle average of tags in use
system.cpu1.icache.total_refs 167072 # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs 358 # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs 466.681564 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst 76.751702 # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst 0.149906 # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total 0.149906 # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst 167072 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 167072 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 167072 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 167072 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 167072 # number of overall hits
system.cpu1.icache.overall_hits::total 167072 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 358 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 358 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 358 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 358 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 358 # number of overall misses
system.cpu1.icache.overall_misses::total 358 # number of overall misses
system.cpu1.icache.ReadReq_accesses::cpu1.inst 167430 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 167430 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 167430 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 167430 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 167430 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 167430 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.002138 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.002138 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.002138 # miss rate for overall accesses
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.replacements 0 # number of replacements
system.cpu1.dcache.tagsinuse 30.316999 # Cycle average of tags in use
system.cpu1.dcache.total_refs 26731 # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs 26 # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs 1028.115385 # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data 30.316999 # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data 0.059213 # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total 0.059213 # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data 40470 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 40470 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 12563 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 12563 # number of WriteReq hits
system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits
system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits
system.cpu1.dcache.demand_hits::cpu1.data 53033 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 53033 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 53033 # number of overall hits
system.cpu1.dcache.overall_hits::total 53033 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 174 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 174 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 106 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 106 # number of WriteReq misses
system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses
system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses
system.cpu1.dcache.demand_misses::cpu1.data 280 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 280 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 280 # number of overall misses
system.cpu1.dcache.overall_misses::total 280 # number of overall misses
system.cpu1.dcache.ReadReq_accesses::cpu1.data 40644 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 40644 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 12669 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 12669 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 53313 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 53313 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 53313 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 53313 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004281 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.004281 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008367 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.008367 # miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005252 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.005252 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005252 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.005252 # miss rate for overall accesses
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.numCycles 173295 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu2.committedInsts 167334 # Number of instructions committed
system.cpu2.committedOps 167334 # Number of ops (including micro ops) committed
system.cpu2.num_int_alu_accesses 113333 # Number of integer alu accesses
system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu2.num_func_calls 633 # number of times a function call or return occured
system.cpu2.num_conditional_control_insts 31007 # number of instructions that are conditional controls
system.cpu2.num_int_insts 113333 # number of integer instructions
system.cpu2.num_fp_insts 0 # number of float instructions
system.cpu2.num_int_register_reads 290613 # number of times the integer registers were read
system.cpu2.num_int_register_writes 109308 # number of times the integer registers were written
system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu2.num_mem_refs 58537 # number of memory refs
system.cpu2.num_load_insts 42362 # Number of load instructions
system.cpu2.num_store_insts 16175 # Number of store instructions
system.cpu2.num_idle_cycles 7936.951217 # Number of idle cycles
system.cpu2.num_busy_cycles 165358.048783 # Number of busy cycles
system.cpu2.not_idle_fraction 0.954200 # Percentage of non-idle cycles
system.cpu2.idle_fraction 0.045800 # Percentage of idle cycles
system.cpu2.icache.replacements 278 # number of replacements
system.cpu2.icache.tagsinuse 74.781015 # Cycle average of tags in use
system.cpu2.icache.total_refs 167008 # Total number of references to valid blocks.
system.cpu2.icache.sampled_refs 358 # Sample count of references to valid blocks.
system.cpu2.icache.avg_refs 466.502793 # Average number of references to valid blocks.
system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu2.icache.occ_blocks::cpu2.inst 74.781015 # Average occupied blocks per requestor
system.cpu2.icache.occ_percent::cpu2.inst 0.146057 # Average percentage of cache occupancy
system.cpu2.icache.occ_percent::total 0.146057 # Average percentage of cache occupancy
system.cpu2.icache.ReadReq_hits::cpu2.inst 167008 # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total 167008 # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst 167008 # number of demand (read+write) hits
system.cpu2.icache.demand_hits::total 167008 # number of demand (read+write) hits
system.cpu2.icache.overall_hits::cpu2.inst 167008 # number of overall hits
system.cpu2.icache.overall_hits::total 167008 # number of overall hits
system.cpu2.icache.ReadReq_misses::cpu2.inst 358 # number of ReadReq misses
system.cpu2.icache.ReadReq_misses::total 358 # number of ReadReq misses
system.cpu2.icache.demand_misses::cpu2.inst 358 # number of demand (read+write) misses
system.cpu2.icache.demand_misses::total 358 # number of demand (read+write) misses
system.cpu2.icache.overall_misses::cpu2.inst 358 # number of overall misses
system.cpu2.icache.overall_misses::total 358 # number of overall misses
system.cpu2.icache.ReadReq_accesses::cpu2.inst 167366 # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_accesses::total 167366 # number of ReadReq accesses(hits+misses)
system.cpu2.icache.demand_accesses::cpu2.inst 167366 # number of demand (read+write) accesses
system.cpu2.icache.demand_accesses::total 167366 # number of demand (read+write) accesses
system.cpu2.icache.overall_accesses::cpu2.inst 167366 # number of overall (read+write) accesses
system.cpu2.icache.overall_accesses::total 167366 # number of overall (read+write) accesses
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002139 # miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_miss_rate::total 0.002139 # miss rate for ReadReq accesses
system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002139 # miss rate for demand accesses
system.cpu2.icache.demand_miss_rate::total 0.002139 # miss rate for demand accesses
system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002139 # miss rate for overall accesses
system.cpu2.icache.overall_miss_rate::total 0.002139 # miss rate for overall accesses
system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.icache.fast_writes 0 # number of fast writes performed
system.cpu2.icache.cache_copies 0 # number of cache copies performed
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.dcache.replacements 0 # number of replacements
system.cpu2.dcache.tagsinuse 29.605505 # Cycle average of tags in use
system.cpu2.dcache.total_refs 33613 # Total number of references to valid blocks.
system.cpu2.dcache.sampled_refs 26 # Sample count of references to valid blocks.
system.cpu2.dcache.avg_refs 1292.807692 # Average number of references to valid blocks.
system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu2.dcache.occ_blocks::cpu2.data 29.605505 # Average occupied blocks per requestor
system.cpu2.dcache.occ_percent::cpu2.data 0.057823 # Average percentage of cache occupancy
system.cpu2.dcache.occ_percent::total 0.057823 # Average percentage of cache occupancy
system.cpu2.dcache.ReadReq_hits::cpu2.data 42194 # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total 42194 # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data 15998 # number of WriteReq hits
system.cpu2.dcache.WriteReq_hits::total 15998 # number of WriteReq hits
system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits
system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits
system.cpu2.dcache.demand_hits::cpu2.data 58192 # number of demand (read+write) hits
system.cpu2.dcache.demand_hits::total 58192 # number of demand (read+write) hits
system.cpu2.dcache.overall_hits::cpu2.data 58192 # number of overall hits
system.cpu2.dcache.overall_hits::total 58192 # number of overall hits
system.cpu2.dcache.ReadReq_misses::cpu2.data 160 # number of ReadReq misses
system.cpu2.dcache.ReadReq_misses::total 160 # number of ReadReq misses
system.cpu2.dcache.WriteReq_misses::cpu2.data 109 # number of WriteReq misses
system.cpu2.dcache.WriteReq_misses::total 109 # number of WriteReq misses
system.cpu2.dcache.SwapReq_misses::cpu2.data 55 # number of SwapReq misses
system.cpu2.dcache.SwapReq_misses::total 55 # number of SwapReq misses
system.cpu2.dcache.demand_misses::cpu2.data 269 # number of demand (read+write) misses
system.cpu2.dcache.demand_misses::total 269 # number of demand (read+write) misses
system.cpu2.dcache.overall_misses::cpu2.data 269 # number of overall misses
system.cpu2.dcache.overall_misses::total 269 # number of overall misses
system.cpu2.dcache.ReadReq_accesses::cpu2.data 42354 # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_accesses::total 42354 # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::cpu2.data 16107 # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::total 16107 # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::cpu2.data 66 # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.demand_accesses::cpu2.data 58461 # number of demand (read+write) accesses
system.cpu2.dcache.demand_accesses::total 58461 # number of demand (read+write) accesses
system.cpu2.dcache.overall_accesses::cpu2.data 58461 # number of overall (read+write) accesses
system.cpu2.dcache.overall_accesses::total 58461 # number of overall (read+write) accesses
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003778 # miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_miss_rate::total 0.003778 # miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006767 # miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_miss_rate::total 0.006767 # miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses
system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004601 # miss rate for demand accesses
system.cpu2.dcache.demand_miss_rate::total 0.004601 # miss rate for demand accesses
system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004601 # miss rate for overall accesses
system.cpu2.dcache.overall_miss_rate::total 0.004601 # miss rate for overall accesses
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.numCycles 173294 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu3.committedInsts 167269 # Number of instructions committed
system.cpu3.committedOps 167269 # Number of ops (including micro ops) committed
system.cpu3.num_int_alu_accesses 111554 # Number of integer alu accesses
system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu3.num_func_calls 633 # number of times a function call or return occured
system.cpu3.num_conditional_control_insts 31865 # number of instructions that are conditional controls
system.cpu3.num_int_insts 111554 # number of integer instructions
system.cpu3.num_fp_insts 0 # number of float instructions
system.cpu3.num_int_register_reads 280060 # number of times the integer registers were read
system.cpu3.num_int_register_writes 104916 # number of times the integer registers were written
system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu3.num_mem_refs 55900 # number of memory refs
system.cpu3.num_load_insts 41466 # Number of load instructions
system.cpu3.num_store_insts 14434 # Number of store instructions
system.cpu3.num_idle_cycles 8001.119846 # Number of idle cycles
system.cpu3.num_busy_cycles 165292.880154 # Number of busy cycles
system.cpu3.not_idle_fraction 0.953829 # Percentage of non-idle cycles
system.cpu3.idle_fraction 0.046171 # Percentage of idle cycles
system.cpu3.icache.replacements 279 # number of replacements
system.cpu3.icache.tagsinuse 72.874497 # Cycle average of tags in use
system.cpu3.icache.total_refs 166942 # Total number of references to valid blocks.
system.cpu3.icache.sampled_refs 359 # Sample count of references to valid blocks.
system.cpu3.icache.avg_refs 465.019499 # Average number of references to valid blocks.
system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu3.icache.occ_blocks::cpu3.inst 72.874497 # Average occupied blocks per requestor
system.cpu3.icache.occ_percent::cpu3.inst 0.142333 # Average percentage of cache occupancy
system.cpu3.icache.occ_percent::total 0.142333 # Average percentage of cache occupancy
system.cpu3.icache.ReadReq_hits::cpu3.inst 166942 # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total 166942 # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst 166942 # number of demand (read+write) hits
system.cpu3.icache.demand_hits::total 166942 # number of demand (read+write) hits
system.cpu3.icache.overall_hits::cpu3.inst 166942 # number of overall hits
system.cpu3.icache.overall_hits::total 166942 # number of overall hits
system.cpu3.icache.ReadReq_misses::cpu3.inst 359 # number of ReadReq misses
system.cpu3.icache.ReadReq_misses::total 359 # number of ReadReq misses
system.cpu3.icache.demand_misses::cpu3.inst 359 # number of demand (read+write) misses
system.cpu3.icache.demand_misses::total 359 # number of demand (read+write) misses
system.cpu3.icache.overall_misses::cpu3.inst 359 # number of overall misses
system.cpu3.icache.overall_misses::total 359 # number of overall misses
system.cpu3.icache.ReadReq_accesses::cpu3.inst 167301 # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_accesses::total 167301 # number of ReadReq accesses(hits+misses)
system.cpu3.icache.demand_accesses::cpu3.inst 167301 # number of demand (read+write) accesses
system.cpu3.icache.demand_accesses::total 167301 # number of demand (read+write) accesses
system.cpu3.icache.overall_accesses::cpu3.inst 167301 # number of overall (read+write) accesses
system.cpu3.icache.overall_accesses::total 167301 # number of overall (read+write) accesses
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002146 # miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_miss_rate::total 0.002146 # miss rate for ReadReq accesses
system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002146 # miss rate for demand accesses
system.cpu3.icache.demand_miss_rate::total 0.002146 # miss rate for demand accesses
system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002146 # miss rate for overall accesses
system.cpu3.icache.overall_miss_rate::total 0.002146 # miss rate for overall accesses
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.icache.fast_writes 0 # number of fast writes performed
system.cpu3.icache.cache_copies 0 # number of cache copies performed
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.dcache.replacements 0 # number of replacements
system.cpu3.dcache.tagsinuse 28.795404 # Cycle average of tags in use
system.cpu3.dcache.total_refs 30236 # Total number of references to valid blocks.
system.cpu3.dcache.sampled_refs 27 # Sample count of references to valid blocks.
system.cpu3.dcache.avg_refs 1119.851852 # Average number of references to valid blocks.
system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu3.dcache.occ_blocks::cpu3.data 28.795404 # Average occupied blocks per requestor
system.cpu3.dcache.occ_percent::cpu3.data 0.056241 # Average percentage of cache occupancy
system.cpu3.dcache.occ_percent::total 0.056241 # Average percentage of cache occupancy
system.cpu3.dcache.ReadReq_hits::cpu3.data 41301 # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total 41301 # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data 14260 # number of WriteReq hits
system.cpu3.dcache.WriteReq_hits::total 14260 # number of WriteReq hits
system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits
system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits
system.cpu3.dcache.demand_hits::cpu3.data 55561 # number of demand (read+write) hits
system.cpu3.dcache.demand_hits::total 55561 # number of demand (read+write) hits
system.cpu3.dcache.overall_hits::cpu3.data 55561 # number of overall hits
system.cpu3.dcache.overall_hits::total 55561 # number of overall hits
system.cpu3.dcache.ReadReq_misses::cpu3.data 157 # number of ReadReq misses
system.cpu3.dcache.ReadReq_misses::total 157 # number of ReadReq misses
system.cpu3.dcache.WriteReq_misses::cpu3.data 102 # number of WriteReq misses
system.cpu3.dcache.WriteReq_misses::total 102 # number of WriteReq misses
system.cpu3.dcache.SwapReq_misses::cpu3.data 55 # number of SwapReq misses
system.cpu3.dcache.SwapReq_misses::total 55 # number of SwapReq misses
system.cpu3.dcache.demand_misses::cpu3.data 259 # number of demand (read+write) misses
system.cpu3.dcache.demand_misses::total 259 # number of demand (read+write) misses
system.cpu3.dcache.overall_misses::cpu3.data 259 # number of overall misses
system.cpu3.dcache.overall_misses::total 259 # number of overall misses
system.cpu3.dcache.ReadReq_accesses::cpu3.data 41458 # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_accesses::total 41458 # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::cpu3.data 14362 # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::total 14362 # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::cpu3.data 70 # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.demand_accesses::cpu3.data 55820 # number of demand (read+write) accesses
system.cpu3.dcache.demand_accesses::total 55820 # number of demand (read+write) accesses
system.cpu3.dcache.overall_accesses::cpu3.data 55820 # number of overall (read+write) accesses
system.cpu3.dcache.overall_accesses::total 55820 # number of overall (read+write) accesses
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003787 # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_miss_rate::total 0.003787 # miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007102 # miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_miss_rate::total 0.007102 # miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.785714 # miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_miss_rate::total 0.785714 # miss rate for SwapReq accesses
system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004640 # miss rate for demand accesses
system.cpu3.dcache.demand_miss_rate::total 0.004640 # miss rate for demand accesses
system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004640 # miss rate for overall accesses
system.cpu3.dcache.overall_miss_rate::total 0.004640 # miss rate for overall accesses
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.replacements 0 # number of replacements
system.l2c.tagsinuse 366.582542 # Cycle average of tags in use
system.l2c.total_refs 1220 # Total number of references to valid blocks.
system.l2c.sampled_refs 421 # Sample count of references to valid blocks.
system.l2c.avg_refs 2.897862 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data 55.207595 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst 59.511852 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 6.721145 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.inst 1.930661 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.data 0.935410 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu3.inst 0.977573 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu3.data 0.905640 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.005594 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst 356 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.inst 357 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
system.l2c.Writeback_hits::total 1 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits
system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst 356 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
system.l2c.demand_hits::total 1220 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst 185 # number of overall hits
system.l2c.overall_hits::cpu0.data 5 # number of overall hits
system.l2c.overall_hits::cpu1.inst 296 # number of overall hits
system.l2c.overall_hits::cpu1.data 3 # number of overall hits
system.l2c.overall_hits::cpu2.inst 356 # number of overall hits
system.l2c.overall_hits::cpu2.data 9 # number of overall hits
system.l2c.overall_hits::cpu3.inst 357 # number of overall hits
system.l2c.overall_hits::cpu3.data 9 # number of overall hits
system.l2c.overall_hits::total 1220 # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst 282 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 62 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst 2 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.inst 2 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses
system.l2c.ReadReq_misses::total 423 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 29 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data 19 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 84 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst 2 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst 2 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses
system.l2c.demand_misses::total 559 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst 282 # number of overall misses
system.l2c.overall_misses::cpu0.data 165 # number of overall misses
system.l2c.overall_misses::cpu1.inst 62 # number of overall misses
system.l2c.overall_misses::cpu1.data 20 # number of overall misses
system.l2c.overall_misses::cpu2.inst 2 # number of overall misses
system.l2c.overall_misses::cpu2.data 13 # number of overall misses
system.l2c.overall_misses::cpu3.inst 2 # number of overall misses
system.l2c.overall_misses::cpu3.data 13 # number of overall misses
system.l2c.overall_misses::total 559 # number of overall misses
system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 358 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 10 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst 358 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data 10 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.inst 359 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.data 10 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1643 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 31 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data 19 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 86 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.257456 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.976744 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst 0.005587 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst 0.005587 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

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tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
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