10b70d5452
This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
618 lines
70 KiB
Text
618 lines
70 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.141089 # Number of seconds simulated
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sim_ticks 141089296500 # Number of ticks simulated
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final_tick 141089296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 83115 # Simulator instruction rate (inst/s)
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host_op_rate 83115 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 29414893 # Simulator tick rate (ticks/s)
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host_mem_usage 223012 # Number of bytes of host memory used
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host_seconds 4796.53 # Real time elapsed on the host
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sim_insts 398664595 # Number of instructions simulated
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sim_ops 398664595 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 254016 # Number of bytes read from this memory
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system.physmem.bytes_read::total 468992 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 214976 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 214976 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 3359 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 1523688 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 1800392 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 3324079 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1523688 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1523688 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1523688 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 1800392 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 3324079 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 7328 # Total number of read requests seen
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system.physmem.writeReqs 0 # Total number of write requests seen
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system.physmem.cpureqs 7328 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 468992 # Total number of bytes read from memory
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system.physmem.bytesWritten 0 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 468992 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 465 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 464 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 518 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 520 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 382 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 398 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 457 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 444 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 407 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 457 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 588 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 397 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 529 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 418 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 396 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 488 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 141089244500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 7328 # Categorize read packet sizes
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system.physmem.readPktSize::7 0 # Categorize read packet sizes
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system.physmem.readPktSize::8 0 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # categorize write packet sizes
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system.physmem.writePktSize::1 0 # categorize write packet sizes
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system.physmem.writePktSize::2 0 # categorize write packet sizes
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system.physmem.writePktSize::3 0 # categorize write packet sizes
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system.physmem.writePktSize::4 0 # categorize write packet sizes
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system.physmem.writePktSize::5 0 # categorize write packet sizes
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system.physmem.writePktSize::6 0 # categorize write packet sizes
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system.physmem.writePktSize::7 0 # categorize write packet sizes
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system.physmem.writePktSize::8 0 # categorize write packet sizes
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system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
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system.physmem.rdQLenPdf::0 4661 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 1890 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 520 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 190 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 66 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.totQLat 39617295 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 175175295 # Sum of mem lat for all requests
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system.physmem.totBusLat 29312000 # Total cycles spent in databus access
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system.physmem.totBankLat 106246000 # Total cycles spent in bank access
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system.physmem.avgQLat 5406.29 # Average queueing delay per request
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system.physmem.avgBankLat 14498.64 # Average bank access latency per request
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system.physmem.avgBusLat 4000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 23904.93 # Average memory access latency
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system.physmem.avgRdBW 3.32 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 3.32 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 0.02 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.00 # Average read queue length over time
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system.physmem.avgWrQLen 0.00 # Average write queue length over time
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system.physmem.readRowHits 6442 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 87.91 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 19253444.94 # Average gap between requests
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 94754611 # DTB read hits
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system.cpu.dtb.read_misses 21 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 94754632 # DTB read accesses
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system.cpu.dtb.write_hits 73521102 # DTB write hits
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system.cpu.dtb.write_misses 35 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 73521137 # DTB write accesses
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system.cpu.dtb.data_hits 168275713 # DTB hits
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system.cpu.dtb.data_misses 56 # DTB misses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_accesses 168275769 # DTB accesses
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system.cpu.itb.fetch_hits 49091192 # ITB hits
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system.cpu.itb.fetch_misses 88817 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 49180009 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 215 # Number of system calls
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system.cpu.numCycles 282178594 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.branch_predictor.lookups 53863325 # Number of BP lookups
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system.cpu.branch_predictor.condPredicted 30909619 # Number of conditional branches predicted
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system.cpu.branch_predictor.condIncorrect 16029157 # Number of conditional branches incorrect
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system.cpu.branch_predictor.BTBLookups 33388385 # Number of BTB lookups
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system.cpu.branch_predictor.BTBHits 15622160 # Number of BTB hits
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system.cpu.branch_predictor.usedRAS 8007516 # Number of times the RAS was used to get a target.
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system.cpu.branch_predictor.RASInCorrect 19 # Number of incorrect RAS predictions.
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system.cpu.branch_predictor.BTBHitPct 46.789205 # BTB Hit Percentage
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system.cpu.branch_predictor.predictedTaken 29654286 # Number of Branches Predicted As Taken (True).
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system.cpu.branch_predictor.predictedNotTaken 24209039 # Number of Branches Predicted As Not Taken (False).
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system.cpu.regfile_manager.intRegFileReads 280812298 # Number of Reads from Int. Register File
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system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File
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system.cpu.regfile_manager.intRegFileAccesses 440148157 # Total Accesses (Read+Write) to the Int. Register File
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system.cpu.regfile_manager.floatRegFileReads 119908557 # Number of Reads from FP Register File
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system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File
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system.cpu.regfile_manager.floatRegFileAccesses 220105038 # Total Accesses (Read+Write) to the FP Register File
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system.cpu.regfile_manager.regForwards 100451904 # Number of Registers Read Through Forwarding Logic
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system.cpu.agen_unit.agens 168699560 # Number of Address Generations
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system.cpu.execution_unit.predictedTakenIncorrect 14461353 # Number of Branches Incorrectly Predicted As Taken.
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system.cpu.execution_unit.predictedNotTakenIncorrect 1567145 # Number of Branches Incorrectly Predicted As Not Taken).
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system.cpu.execution_unit.mispredicted 16028498 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.predicted 28559053 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.mispredictPct 35.948370 # Percentage of Incorrect Branches Predicts
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system.cpu.execution_unit.executions 205751378 # Number of Instructions Executed.
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system.cpu.mult_div_unit.multiplies 2124332 # Number of Multipy Operations Executed
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system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
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system.cpu.contextSwitches 1 # Number of context switches
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system.cpu.threadCycles 281883987 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
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system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
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system.cpu.timesIdled 7632 # Number of times that the entire CPU went into an idle state and unscheduled itself
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system.cpu.idleCycles 13336617 # Number of cycles cpu's stages were not processed
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system.cpu.runCycles 268841977 # Number of cycles cpu stages are processed.
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system.cpu.activity 95.273696 # Percentage of cycles cpu is active
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system.cpu.comLoads 94754489 # Number of Load instructions committed
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system.cpu.comStores 73520729 # Number of Store instructions committed
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system.cpu.comBranches 44587532 # Number of Branches instructions committed
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system.cpu.comNops 23089775 # Number of Nop instructions committed
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system.cpu.comNonSpec 215 # Number of Non-Speculative instructions committed
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system.cpu.comInts 112239074 # Number of Integer instructions committed
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system.cpu.comFloats 50439198 # Number of Floating Point instructions committed
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system.cpu.committedInsts 398664595 # Number of Instructions committed (Per-Thread)
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system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread)
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system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
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system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total)
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system.cpu.cpi 0.707810 # CPI: Cycles Per Instruction (Per-Thread)
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system.cpu.smt_cpi nan # CPI: Total SMT-CPI
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system.cpu.cpi_total 0.707810 # CPI: Total CPI of All Threads
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system.cpu.ipc 1.412809 # IPC: Instructions Per Cycle (Per-Thread)
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system.cpu.smt_ipc nan # IPC: Total SMT-IPC
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system.cpu.ipc_total 1.412809 # IPC: Total IPC of All Threads
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system.cpu.stage0.idleCycles 78396963 # Number of cycles 0 instructions are processed.
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system.cpu.stage0.runCycles 203781631 # Number of cycles 1+ instructions are processed.
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system.cpu.stage0.utilization 72.217254 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage1.idleCycles 108683745 # Number of cycles 0 instructions are processed.
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system.cpu.stage1.runCycles 173494849 # Number of cycles 1+ instructions are processed.
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system.cpu.stage1.utilization 61.484058 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage2.idleCycles 104474173 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage2.runCycles 177704421 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage2.utilization 62.975869 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage3.idleCycles 183396585 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage3.runCycles 98782009 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage3.utilization 35.006911 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage4.idleCycles 92487828 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage4.runCycles 189690766 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage4.utilization 67.223656 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.icache.replacements 1982 # number of replacements
|
|
system.cpu.icache.tagsinuse 1831.235862 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 49086683 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 3910 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 12554.138875 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 1831.235862 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.894158 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.894158 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 49086683 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 49086683 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 49086683 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 49086683 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 49086683 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 49086683 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 4508 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 4508 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 4508 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 4508 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 4508 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 4508 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 196984000 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 196984000 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 196984000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 196984000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 196984000 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 196984000 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 49091191 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 49091191 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 49091191 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 49091191 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 49091191 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 49091191 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000092 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000092 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000092 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000092 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000092 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000092 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43696.539485 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 43696.539485 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 43696.539485 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 43696.539485 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 43696.539485 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 43696.539485 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 220 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 598 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 598 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 598 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 598 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 598 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 598 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3910 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 3910 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 3910 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 3910 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 3910 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 3910 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 172100500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 172100500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 172100500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 172100500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 172100500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 172100500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 44015.473146 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 44015.473146 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 44015.473146 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 44015.473146 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 44015.473146 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 44015.473146 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 764 # number of replacements
|
|
system.cpu.dcache.tagsinuse 3285.555145 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 168254416 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 40523.703276 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 3285.555145 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.802137 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.802137 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 94753185 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 94753185 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 73501231 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 73501231 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 168254416 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 168254416 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 168254416 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 168254416 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1304 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1304 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 19498 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 19498 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 20802 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 20802 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 20802 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 20802 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 64930000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 64930000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 710139000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 710139000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 775069000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 775069000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 775069000 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 775069000 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 168275218 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 168275218 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 168275218 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 168275218 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000014 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.000014 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000265 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.000265 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.000124 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.000124 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.000124 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.000124 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49792.944785 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 49792.944785 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36421.120115 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 36421.120115 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 37259.350062 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 37259.350062 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 37259.350062 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 37259.350062 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 15899 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 535 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.717757 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 649 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 649 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 354 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 354 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16296 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 16296 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 16650 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 16650 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 16650 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 16650 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 4152 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 48068500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 48068500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 153897000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 153897000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 201965500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 201965500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 201965500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 201965500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50598.421053 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50598.421053 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48062.773267 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48062.773267 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48642.943160 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 48642.943160 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48642.943160 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 48642.943160 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 3908.656926 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 760 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 4717 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 0.161119 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 370.653922 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 2910.300742 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 627.702262 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.011311 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.088815 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.019156 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.119283 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 551 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 674 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 551 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 183 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 734 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 551 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 183 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 734 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 3359 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 824 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 4183 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 3145 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 3145 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 3359 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 3969 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 7328 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 3359 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 7328 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 162633000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 45642500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 208275500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 150126000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 150126000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 162633000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 195768500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 358401500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 162633000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 195768500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 358401500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 3910 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 4857 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 649 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 649 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 3205 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 3205 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 3910 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 4152 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 8062 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 3910 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 8062 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.859079 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.870116 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.861231 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981279 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.981279 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.859079 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.955925 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.908956 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.859079 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.908956 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48417.088419 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55391.383495 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 49790.939517 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 47734.817170 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 47734.817170 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48417.088419 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 49324.389015 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 48908.501638 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48417.088419 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 49324.389015 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 48908.501638 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3359 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 824 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 4183 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3145 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 3145 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3359 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 3969 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 7328 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3359 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 120134545 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 35298214 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 155432759 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 111138322 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 111138322 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 120134545 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 146436536 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 266571081 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 120134545 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 146436536 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 266571081 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.859079 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.861231 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981279 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981279 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.859079 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.908956 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.859079 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.908956 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35764.973206 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42837.638350 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37158.202008 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35338.099205 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35338.099205 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35764.973206 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36895.070799 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36377.057997 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35764.973206 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36895.070799 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36377.057997 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|